arch/arm/mach-omap2/io.c

   1 /*
   2  * linux/arch/arm/mach-omap2/io.c
   3  *
   4  * OMAP2 I/O mapping code
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Copyright (C) 2007-2009 Texas Instruments
   8  *
   9  * Author:
  10  *      Juha Yrjola <juha.yrjola@nokia.com>
  11  *      Syed Khasim <x0khasim@ti.com>
  12  *
  13  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19 #include <linux/module.h>
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/io.h>
  23 #include <linux/clk.h>
  24
  25 #include <asm/tlb.h>
  26 #include <asm/mach/map.h>
  27
  28 #include <linux/omap-dma.h>
  29
  30 #include "omap_hwmod.h"
  31 #include "soc.h"
  32 #include "iomap.h"
  33 #include "voltage.h"
  34 #include "powerdomain.h"
  35 #include "clockdomain.h"
  36 #include "common.h"
  37 #include "clock.h"
  38 #include "clock2xxx.h"
  39 #include "clock3xxx.h"
  40 #include "clock44xx.h"
  41 #include "omap-pm.h"
  42 #include "sdrc.h"
  43 #include "control.h"
  44 #include "serial.h"
  45 #include "sram.h"
  46 #include "cm2xxx.h"
  47 #include "cm3xxx.h"
  48 #include "cm33xx.h"
  49 #include "cm44xx.h"
  50 #include "prm.h"
  51 #include "cm.h"
  52 #include "prcm_mpu44xx.h"
  53 #include "prminst44xx.h"
  54 #include "prm2xxx.h"
  55 #include "prm3xxx.h"
  56 #include "prm33xx.h"
  57 #include "prm44xx.h"
  58 #include "opp2xxx.h"
  59
  60 /*
  61  * omap_clk_soc_init: points to a function that does the SoC-specific
  62  * clock initializations
  63  */
  64 static int (*omap_clk_soc_init)(void);
  65
  66 /*
  67  * The machine specific code may provide the extra mapping besides the
  68  * default mapping provided here.
  69  */
  70
  71 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
  72 static struct map_desc omap24xx_io_desc[] __initdata = {
  73         {
  74                 .virtual        = L3_24XX_VIRT,
  75                 .pfn            = __phys_to_pfn(L3_24XX_PHYS),
  76                 .length         = L3_24XX_SIZE,
  77                 .type           = MT_DEVICE
  78         },
  79         {
  80                 .virtual        = L4_24XX_VIRT,
  81                 .pfn            = __phys_to_pfn(L4_24XX_PHYS),
  82                 .length         = L4_24XX_SIZE,
  83                 .type           = MT_DEVICE
  84         },
  85 };
  86
  87 #ifdef CONFIG_SOC_OMAP2420
  88 static struct map_desc omap242x_io_desc[] __initdata = {
  89         {
  90                 .virtual        = DSP_MEM_2420_VIRT,
  91                 .pfn            = __phys_to_pfn(DSP_MEM_2420_PHYS),
  92                 .length         = DSP_MEM_2420_SIZE,
  93                 .type           = MT_DEVICE
  94         },
  95         {
  96                 .virtual        = DSP_IPI_2420_VIRT,
  97                 .pfn            = __phys_to_pfn(DSP_IPI_2420_PHYS),
  98                 .length         = DSP_IPI_2420_SIZE,
  99                 .type           = MT_DEVICE
 100         },
 101         {
 102                 .virtual        = DSP_MMU_2420_VIRT,
 103                 .pfn            = __phys_to_pfn(DSP_MMU_2420_PHYS),
 104                 .length         = DSP_MMU_2420_SIZE,
 105                 .type           = MT_DEVICE
 106         },
 107 };
 108
 109 #endif
 110
 111 #ifdef CONFIG_SOC_OMAP2430
 112 static struct map_desc omap243x_io_desc[] __initdata = {
 113         {
 114                 .virtual        = L4_WK_243X_VIRT,
 115                 .pfn            = __phys_to_pfn(L4_WK_243X_PHYS),
 116                 .length         = L4_WK_243X_SIZE,
 117                 .type           = MT_DEVICE
 118         },
 119         {
 120                 .virtual        = OMAP243X_GPMC_VIRT,
 121                 .pfn            = __phys_to_pfn(OMAP243X_GPMC_PHYS),
 122                 .length         = OMAP243X_GPMC_SIZE,
 123                 .type           = MT_DEVICE
 124         },
 125         {
 126                 .virtual        = OMAP243X_SDRC_VIRT,
 127                 .pfn            = __phys_to_pfn(OMAP243X_SDRC_PHYS),
 128                 .length         = OMAP243X_SDRC_SIZE,
 129                 .type           = MT_DEVICE
 130         },
 131         {
 132                 .virtual        = OMAP243X_SMS_VIRT,
 133                 .pfn            = __phys_to_pfn(OMAP243X_SMS_PHYS),
 134                 .length         = OMAP243X_SMS_SIZE,
 135                 .type           = MT_DEVICE
 136         },
 137 };
 138 #endif
 139 #endif
 140
 141 #ifdef  CONFIG_ARCH_OMAP3
 142 static struct map_desc omap34xx_io_desc[] __initdata = {
 143         {
 144                 .virtual        = L3_34XX_VIRT,
 145                 .pfn            = __phys_to_pfn(L3_34XX_PHYS),
 146                 .length         = L3_34XX_SIZE,
 147                 .type           = MT_DEVICE
 148         },
 149         {
 150                 .virtual        = L4_34XX_VIRT,
 151                 .pfn            = __phys_to_pfn(L4_34XX_PHYS),
 152                 .length         = L4_34XX_SIZE,
 153                 .type           = MT_DEVICE
 154         },
 155         {
 156                 .virtual        = OMAP34XX_GPMC_VIRT,
 157                 .pfn            = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
 158                 .length         = OMAP34XX_GPMC_SIZE,
 159                 .type           = MT_DEVICE
 160         },
 161         {
 162                 .virtual        = OMAP343X_SMS_VIRT,
 163                 .pfn            = __phys_to_pfn(OMAP343X_SMS_PHYS),
 164                 .length         = OMAP343X_SMS_SIZE,
 165                 .type           = MT_DEVICE
 166         },
 167         {
 168                 .virtual        = OMAP343X_SDRC_VIRT,
 169                 .pfn            = __phys_to_pfn(OMAP343X_SDRC_PHYS),
 170                 .length         = OMAP343X_SDRC_SIZE,
 171                 .type           = MT_DEVICE
 172         },
 173         {
 174                 .virtual        = L4_PER_34XX_VIRT,
 175                 .pfn            = __phys_to_pfn(L4_PER_34XX_PHYS),
 176                 .length         = L4_PER_34XX_SIZE,
 177                 .type           = MT_DEVICE
 178         },
 179         {
 180                 .virtual        = L4_EMU_34XX_VIRT,
 181                 .pfn            = __phys_to_pfn(L4_EMU_34XX_PHYS),
 182                 .length         = L4_EMU_34XX_SIZE,
 183                 .type           = MT_DEVICE
 184         },
 185 };
 186 #endif
 187
 188 #ifdef CONFIG_SOC_TI81XX
 189 static struct map_desc omapti81xx_io_desc[] __initdata = {
 190         {
 191                 .virtual        = L4_34XX_VIRT,
 192                 .pfn            = __phys_to_pfn(L4_34XX_PHYS),
 193                 .length         = L4_34XX_SIZE,
 194                 .type           = MT_DEVICE
 195         }
 196 };
 197 #endif
 198
 199 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 200 static struct map_desc omapam33xx_io_desc[] __initdata = {
 201         {
 202                 .virtual        = L4_34XX_VIRT,
 203                 .pfn            = __phys_to_pfn(L4_34XX_PHYS),
 204                 .length         = L4_34XX_SIZE,
 205                 .type           = MT_DEVICE
 206         },
 207         {
 208                 .virtual        = L4_WK_AM33XX_VIRT,
 209                 .pfn            = __phys_to_pfn(L4_WK_AM33XX_PHYS),
 210                 .length         = L4_WK_AM33XX_SIZE,
 211                 .type           = MT_DEVICE
 212         }
 213 };
 214 #endif
 215
 216 #ifdef  CONFIG_ARCH_OMAP4
 217 static struct map_desc omap44xx_io_desc[] __initdata = {
 218         {
 219                 .virtual        = L3_44XX_VIRT,
 220                 .pfn            = __phys_to_pfn(L3_44XX_PHYS),
 221                 .length         = L3_44XX_SIZE,
 222                 .type           = MT_DEVICE,
 223         },
 224         {
 225                 .virtual        = L4_44XX_VIRT,
 226                 .pfn            = __phys_to_pfn(L4_44XX_PHYS),
 227                 .length         = L4_44XX_SIZE,
 228                 .type           = MT_DEVICE,
 229         },
 230         {
 231                 .virtual        = L4_PER_44XX_VIRT,
 232                 .pfn            = __phys_to_pfn(L4_PER_44XX_PHYS),
 233                 .length         = L4_PER_44XX_SIZE,
 234                 .type           = MT_DEVICE,
 235         },
 236 };
 237 #endif
 238
 239 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
 240 static struct map_desc omap54xx_io_desc[] __initdata = {
 241         {
 242                 .virtual        = L3_54XX_VIRT,
 243                 .pfn            = __phys_to_pfn(L3_54XX_PHYS),
 244                 .length         = L3_54XX_SIZE,
 245                 .type           = MT_DEVICE,
 246         },
 247         {
 248                 .virtual        = L4_54XX_VIRT,
 249                 .pfn            = __phys_to_pfn(L4_54XX_PHYS),
 250                 .length         = L4_54XX_SIZE,
 251                 .type           = MT_DEVICE,
 252         },
 253         {
 254                 .virtual        = L4_WK_54XX_VIRT,
 255                 .pfn            = __phys_to_pfn(L4_WK_54XX_PHYS),
 256                 .length         = L4_WK_54XX_SIZE,
 257                 .type           = MT_DEVICE,
 258         },
 259         {
 260                 .virtual        = L4_PER_54XX_VIRT,
 261                 .pfn            = __phys_to_pfn(L4_PER_54XX_PHYS),
 262                 .length         = L4_PER_54XX_SIZE,
 263                 .type           = MT_DEVICE,
 264         },
 265 };
 266 #endif
 267
 268 #ifdef CONFIG_SOC_OMAP2420
 269 void __init omap242x_map_io(void)
 270 {
 271         iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
 272         iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
 273 }
 274 #endif
 275
 276 #ifdef CONFIG_SOC_OMAP2430
 277 void __init omap243x_map_io(void)
 278 {
 279         iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
 280         iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
 281 }
 282 #endif
 283
 284 #ifdef CONFIG_ARCH_OMAP3
 285 void __init omap3_map_io(void)
 286 {
 287         iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
 288 }
 289 #endif
 290
 291 #ifdef CONFIG_SOC_TI81XX
 292 void __init ti81xx_map_io(void)
 293 {
 294         iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
 295 }
 296 #endif
 297
 298 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 299 void __init am33xx_map_io(void)
 300 {
 301         iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
 302 }
 303 #endif
 304
 305 #ifdef CONFIG_ARCH_OMAP4
 306 void __init omap4_map_io(void)
 307 {
 308         iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
 309 }
 310 #endif
 311
 312 #if defined(CONFIG_SOC_OMAP5) ||  defined(CONFIG_SOC_DRA7XX)
 313 void __init omap5_map_io(void)
 314 {
 315         iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
 316 }
 317 #endif
 318 /*
 319  * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
 320  *
 321  * Sets the CORE DPLL3 M2 divider to the same value that it's at
 322  * currently.  This has the effect of setting the SDRC SDRAM AC timing
 323  * registers to the values currently defined by the kernel.  Currently
 324  * only defined for OMAP3; will return 0 if called on OMAP2.  Returns
 325  * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
 326  * or passes along the return value of clk_set_rate().
 327  */
 328 static int __init _omap2_init_reprogram_sdrc(void)
 329 {
 330         struct clk *dpll3_m2_ck;
 331         int v = -EINVAL;
 332         long rate;
 333
 334         if (!cpu_is_omap34xx())
 335                 return 0;
 336
 337         dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
 338         if (IS_ERR(dpll3_m2_ck))
 339                 return -EINVAL;
 340
 341         rate = clk_get_rate(dpll3_m2_ck);
 342         pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
 343         v = clk_set_rate(dpll3_m2_ck, rate);
 344         if (v)
 345                 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
 346
 347         clk_put(dpll3_m2_ck);
 348
 349         return v;
 350 }
 351
 352 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
 353 {
 354         return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
 355 }
 356
 357 static void __init omap_hwmod_init_postsetup(void)
 358 {
 359         u8 postsetup_state;
 360
 361         /* Set the default postsetup state for all hwmods */
 362 #ifdef CONFIG_PM
 363         postsetup_state = _HWMOD_STATE_IDLE;
 364 #else
 365         postsetup_state = _HWMOD_STATE_ENABLED;
 366 #endif
 367         omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
 368
 369         omap_pm_if_early_init();
 370 }
 371
 372 static void __init __maybe_unused omap_common_late_init(void)
 373 {
 374         omap_mux_late_init();
 375         omap2_common_pm_late_init();
 376         omap_soc_device_init();
 377 }
 378
 379 #ifdef CONFIG_SOC_OMAP2420
 380 void __init omap2420_init_early(void)
 381 {
 382         omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
 383         omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
 384                                OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
 385         omap2_control_base_init();
 386         omap2xxx_check_revision();
 387         omap2_prcm_base_init();
 388         omap2xxx_voltagedomains_init();
 389         omap242x_powerdomains_init();
 390         omap242x_clockdomains_init();
 391         omap2420_hwmod_init();
 392         omap_hwmod_init_postsetup();
 393         omap_clk_soc_init = omap2420_dt_clk_init;
 394         rate_table = omap2420_rate_table;
 395 }
 396
 397 void __init omap2420_init_late(void)
 398 {
 399         omap_common_late_init();
 400         omap2_pm_init();
 401         omap2_clk_enable_autoidle_all();
 402 }
 403 #endif
 404
 405 #ifdef CONFIG_SOC_OMAP2430
 406 void __init omap2430_init_early(void)
 407 {
 408         omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
 409         omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
 410                                OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
 411         omap2_control_base_init();
 412         omap2xxx_check_revision();
 413         omap2_prcm_base_init();
 414         omap2xxx_voltagedomains_init();
 415         omap243x_powerdomains_init();
 416         omap243x_clockdomains_init();
 417         omap2430_hwmod_init();
 418         omap_hwmod_init_postsetup();
 419         omap_clk_soc_init = omap2430_dt_clk_init;
 420         rate_table = omap2430_rate_table;
 421 }
 422
 423 void __init omap2430_init_late(void)
 424 {
 425         omap_common_late_init();
 426         omap2_pm_init();
 427         omap2_clk_enable_autoidle_all();
 428 }
 429 #endif
 430
 431 /*
 432  * Currently only board-omap3beagle.c should call this because of the
 433  * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
 434  */
 435 #ifdef CONFIG_ARCH_OMAP3
 436 void __init omap3_init_early(void)
 437 {
 438         omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
 439         omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
 440                                OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
 441         /* XXX: remove these once OMAP3 is DT only */
 442         if (!of_have_populated_dt()) {
 443                 omap2_set_globals_control(
 444                         OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE));
 445                 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
 446                 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE),
 447                                      NULL);
 448         }
 449         omap2_control_base_init();
 450         omap3xxx_check_revision();
 451         omap3xxx_check_features();
 452         omap2_prcm_base_init();
 453         /* XXX: remove these once OMAP3 is DT only */
 454         if (!of_have_populated_dt()) {
 455                 omap3xxx_prm_init(NULL);
 456                 omap3xxx_cm_init(NULL);
 457         }
 458         omap3xxx_voltagedomains_init();
 459         omap3xxx_powerdomains_init();
 460         omap3xxx_clockdomains_init();
 461         omap3xxx_hwmod_init();
 462         omap_hwmod_init_postsetup();
 463         if (!of_have_populated_dt()) {
 464                 omap3_control_legacy_iomap_init();
 465                 if (soc_is_am35xx())
 466                         omap_clk_soc_init = am35xx_clk_legacy_init;
 467                 else if (cpu_is_omap3630())
 468                         omap_clk_soc_init = omap36xx_clk_legacy_init;
 469                 else if (omap_rev() == OMAP3430_REV_ES1_0)
 470                         omap_clk_soc_init = omap3430es1_clk_legacy_init;
 471                 else
 472                         omap_clk_soc_init = omap3430_clk_legacy_init;
 473         }
 474 }
 475
 476 void __init omap3430_init_early(void)
 477 {
 478         omap3_init_early();
 479         if (of_have_populated_dt())
 480                 omap_clk_soc_init = omap3430_dt_clk_init;
 481 }
 482
 483 void __init omap35xx_init_early(void)
 484 {
 485         omap3_init_early();
 486         if (of_have_populated_dt())
 487                 omap_clk_soc_init = omap3430_dt_clk_init;
 488 }
 489
 490 void __init omap3630_init_early(void)
 491 {
 492         omap3_init_early();
 493         if (of_have_populated_dt())
 494                 omap_clk_soc_init = omap3630_dt_clk_init;
 495 }
 496
 497 void __init am35xx_init_early(void)
 498 {
 499         omap3_init_early();
 500         if (of_have_populated_dt())
 501                 omap_clk_soc_init = am35xx_dt_clk_init;
 502 }
 503
 504 void __init omap3_init_late(void)
 505 {
 506         omap_common_late_init();
 507         omap3_pm_init();
 508         omap2_clk_enable_autoidle_all();
 509 }
 510
 511 void __init omap3430_init_late(void)
 512 {
 513         omap_common_late_init();
 514         omap3_pm_init();
 515         omap2_clk_enable_autoidle_all();
 516 }
 517
 518 void __init omap35xx_init_late(void)
 519 {
 520         omap_common_late_init();
 521         omap3_pm_init();
 522         omap2_clk_enable_autoidle_all();
 523 }
 524
 525 void __init omap3630_init_late(void)
 526 {
 527         omap_common_late_init();
 528         omap3_pm_init();
 529         omap2_clk_enable_autoidle_all();
 530 }
 531
 532 void __init am35xx_init_late(void)
 533 {
 534         omap_common_late_init();
 535         omap3_pm_init();
 536         omap2_clk_enable_autoidle_all();
 537 }
 538
 539 void __init ti81xx_init_late(void)
 540 {
 541         omap_common_late_init();
 542         omap2_clk_enable_autoidle_all();
 543 }
 544 #endif
 545
 546 #ifdef CONFIG_SOC_TI81XX
 547 void __init ti814x_init_early(void)
 548 {
 549         omap2_set_globals_tap(TI814X_CLASS,
 550                               OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
 551         omap2_control_base_init();
 552         omap3xxx_check_revision();
 553         ti81xx_check_features();
 554         omap2_prcm_base_init();
 555         omap3xxx_voltagedomains_init();
 556         omap3xxx_powerdomains_init();
 557         ti81xx_clockdomains_init();
 558         ti81xx_hwmod_init();
 559         omap_hwmod_init_postsetup();
 560         if (of_have_populated_dt())
 561                 omap_clk_soc_init = ti81xx_dt_clk_init;
 562 }
 563
 564 void __init ti816x_init_early(void)
 565 {
 566         omap2_set_globals_tap(TI816X_CLASS,
 567                               OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
 568         omap2_control_base_init();
 569         omap3xxx_check_revision();
 570         ti81xx_check_features();
 571         omap2_prcm_base_init();
 572         omap3xxx_voltagedomains_init();
 573         omap3xxx_powerdomains_init();
 574         ti81xx_clockdomains_init();
 575         ti81xx_hwmod_init();
 576         omap_hwmod_init_postsetup();
 577         if (of_have_populated_dt())
 578                 omap_clk_soc_init = ti81xx_dt_clk_init;
 579 }
 580 #endif
 581
 582 #ifdef CONFIG_SOC_AM33XX
 583 void __init am33xx_init_early(void)
 584 {
 585         omap2_set_globals_tap(AM335X_CLASS,
 586                               AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
 587         omap2_control_base_init();
 588         omap3xxx_check_revision();
 589         am33xx_check_features();
 590         omap2_prcm_base_init();
 591         am33xx_powerdomains_init();
 592         am33xx_clockdomains_init();
 593         am33xx_hwmod_init();
 594         omap_hwmod_init_postsetup();
 595         omap_clk_soc_init = am33xx_dt_clk_init;
 596 }
 597
 598 void __init am33xx_init_late(void)
 599 {
 600         omap_common_late_init();
 601 }
 602 #endif
 603
 604 #ifdef CONFIG_SOC_AM43XX
 605 void __init am43xx_init_early(void)
 606 {
 607         omap2_set_globals_tap(AM335X_CLASS,
 608                               AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
 609         omap2_control_base_init();
 610         omap3xxx_check_revision();
 611         am33xx_check_features();
 612         omap2_prcm_base_init();
 613         am43xx_powerdomains_init();
 614         am43xx_clockdomains_init();
 615         am43xx_hwmod_init();
 616         omap_hwmod_init_postsetup();
 617         omap_l2_cache_init();
 618         omap_clk_soc_init = am43xx_dt_clk_init;
 619 }
 620
 621 void __init am43xx_init_late(void)
 622 {
 623         omap_common_late_init();
 624 }
 625 #endif
 626
 627 #ifdef CONFIG_ARCH_OMAP4
 628 void __init omap4430_init_early(void)
 629 {
 630         omap2_set_globals_tap(OMAP443X_CLASS,
 631                               OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
 632         omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
 633         omap2_control_base_init();
 634         omap4xxx_check_revision();
 635         omap4xxx_check_features();
 636         omap2_prcm_base_init();
 637         omap4_pm_init_early();
 638         omap44xx_voltagedomains_init();
 639         omap44xx_powerdomains_init();
 640         omap44xx_clockdomains_init();
 641         omap44xx_hwmod_init();
 642         omap_hwmod_init_postsetup();
 643         omap_l2_cache_init();
 644         omap_clk_soc_init = omap4xxx_dt_clk_init;
 645 }
 646
 647 void __init omap4430_init_late(void)
 648 {
 649         omap_common_late_init();
 650         omap4_pm_init();
 651         omap2_clk_enable_autoidle_all();
 652 }
 653 #endif
 654
 655 #ifdef CONFIG_SOC_OMAP5
 656 void __init omap5_init_early(void)
 657 {
 658         omap2_set_globals_tap(OMAP54XX_CLASS,
 659                               OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
 660         omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
 661         omap2_control_base_init();
 662         omap4_pm_init_early();
 663         omap2_prcm_base_init();
 664         omap5xxx_check_revision();
 665         omap54xx_voltagedomains_init();
 666         omap54xx_powerdomains_init();
 667         omap54xx_clockdomains_init();
 668         omap54xx_hwmod_init();
 669         omap_hwmod_init_postsetup();
 670         omap_clk_soc_init = omap5xxx_dt_clk_init;
 671 }
 672
 673 void __init omap5_init_late(void)
 674 {
 675         omap_common_late_init();
 676         omap4_pm_init();
 677         omap2_clk_enable_autoidle_all();
 678 }
 679 #endif
 680
 681 #ifdef CONFIG_SOC_DRA7XX
 682 void __init dra7xx_init_early(void)
 683 {
 684         omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
 685         omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
 686         omap2_control_base_init();
 687         omap4_pm_init_early();
 688         omap2_prcm_base_init();
 689         dra7xxx_check_revision();
 690         dra7xx_powerdomains_init();
 691         dra7xx_clockdomains_init();
 692         dra7xx_hwmod_init();
 693         omap_hwmod_init_postsetup();
 694         omap_clk_soc_init = dra7xx_dt_clk_init;
 695 }
 696
 697 void __init dra7xx_init_late(void)
 698 {
 699         omap_common_late_init();
 700         omap4_pm_init();
 701         omap2_clk_enable_autoidle_all();
 702 }
 703 #endif
 704
 705
 706 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
 707                                       struct omap_sdrc_params *sdrc_cs1)
 708 {
 709         omap_sram_init();
 710
 711         if (cpu_is_omap24xx() || omap3_has_sdrc()) {
 712                 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
 713                 _omap2_init_reprogram_sdrc();
 714         }
 715 }
 716
 717 int __init omap_clk_init(void)
 718 {
 719         int ret = 0;
 720
 721         if (!omap_clk_soc_init)
 722                 return 0;
 723
 724         ti_clk_init_features();
 725
 726         if (of_have_populated_dt()) {
 727                 ret = omap_control_init();
 728                 if (ret)
 729                         return ret;
 730
 731                 ret = omap_prcm_init();
 732                 if (ret)
 733                         return ret;
 734
 735                 of_clk_init(NULL);
 736
 737                 ti_dt_clk_init_retry_clks();
 738
 739                 ti_dt_clockdomains_setup();
 740         }
 741
 742         ret = omap_clk_soc_init();
 743
 744         return ret;
 745 }