2 * OMAP4 SMP source file. It contains platform specific functions
3 * needed for the linux smp kernel.
5 * Copyright (C) 2009 Texas Instruments, Inc.
8 * Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * Platform file needed for the OMAP4 SMP. This file is based on arm
11 * realview smp platform.
12 * * Copyright (c) 2002 ARM Limited.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
18 #include <linux/init.h>
19 #include <linux/device.h>
20 #include <linux/smp.h>
22 #include <linux/irqchip/arm-gic.h>
24 #include <asm/smp_scu.h>
26 #include "omap-secure.h"
27 #include "omap-wakeupgen.h"
28 #include <asm/cputype.h>
33 #include "clockdomain.h"
36 #define CPU_MASK 0xff0ffff0
37 #define CPU_CORTEX_A9 0x410FC090
38 #define CPU_CORTEX_A15 0x410FC0F0
40 #define OMAP5_CORE_COUNT 0x2
44 /* SCU base address */
45 static void __iomem
*scu_base
;
47 static DEFINE_SPINLOCK(boot_lock
);
49 void __iomem
*omap4_get_scu_base(void)
54 static void omap4_secondary_init(unsigned int cpu
)
57 * Configure ACTRL and enable NS SMP bit access on CPU1 on HS device.
58 * OMAP44XX EMU/HS devices - CPU0 SMP bit access is enabled in PPA
59 * init and for CPU1, a secure PPA API provided. CPU0 must be ON
60 * while executing NS_SMP API on CPU1 and PPA version must be 1.4.0+.
61 * OMAP443X GP devices- SMP bit isn't accessible.
62 * OMAP446X GP devices - SMP bit access is enabled on both CPUs.
64 if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP
))
65 omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX
,
69 * Configure the CNTFRQ register for the secondary cpu's which
70 * indicates the frequency of the cpu local timers.
72 if (soc_is_omap54xx() || soc_is_dra7xx())
76 * Synchronise with the boot thread.
78 spin_lock(&boot_lock
);
79 spin_unlock(&boot_lock
);
82 static int omap4_boot_secondary(unsigned int cpu
, struct task_struct
*idle
)
84 static struct clockdomain
*cpu1_clkdm
;
86 static struct powerdomain
*cpu1_pwrdm
;
87 void __iomem
*base
= omap_get_wakeupgen_base();
90 * Set synchronisation state between this boot processor
91 * and the secondary one
93 spin_lock(&boot_lock
);
96 * Update the AuxCoreBoot0 with boot state for secondary core.
97 * omap4_secondary_startup() routine will hold the secondary core till
98 * the AuxCoreBoot1 register is updated with cpu state
99 * A barrier is added to ensure that write buffer is drained
101 if (omap_secure_apis_support())
102 omap_modify_auxcoreboot0(0x200, 0xfffffdff);
104 __raw_writel(0x20, base
+ OMAP_AUX_CORE_BOOT_0
);
106 if (!cpu1_clkdm
&& !cpu1_pwrdm
) {
107 cpu1_clkdm
= clkdm_lookup("mpu1_clkdm");
108 cpu1_pwrdm
= pwrdm_lookup("cpu1_pwrdm");
112 * The SGI(Software Generated Interrupts) are not wakeup capable
113 * from low power states. This is known limitation on OMAP4 and
114 * needs to be worked around by using software forced clockdomain
115 * wake-up. To wakeup CPU1, CPU0 forces the CPU1 clockdomain to
116 * software force wakeup. The clockdomain is then put back to
117 * hardware supervised mode.
118 * More details can be found in OMAP4430 TRM - Version J
120 * 4.3.4.2 Power States of CPU0 and CPU1
122 if (booted
&& cpu1_pwrdm
&& cpu1_clkdm
) {
124 * GIC distributor control register has changed between
125 * CortexA9 r1pX and r2pX. The Control Register secure
126 * banked version is now composed of 2 bits:
127 * bit 0 == Secure Enable
128 * bit 1 == Non-Secure Enable
129 * The Non-Secure banked register has not changed
130 * Because the ROM Code is based on the r1pX GIC, the CPU1
131 * GIC restoration will cause a problem to CPU0 Non-Secure SW.
132 * The workaround must be:
133 * 1) Before doing the CPU1 wakeup, CPU0 must disable
134 * the GIC distributor
135 * 2) CPU1 must re-enable the GIC distributor on
138 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD
)) {
144 * Ensure that CPU power state is set to ON to avoid CPU
145 * powerdomain transition on wfi
147 clkdm_wakeup(cpu1_clkdm
);
148 omap_set_pwrdm_state(cpu1_pwrdm
, PWRDM_POWER_ON
);
149 clkdm_allow_idle(cpu1_clkdm
);
151 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD
)) {
152 while (gic_dist_disabled()) {
156 gic_timer_retrigger();
164 arch_send_wakeup_ipi_mask(cpumask_of(cpu
));
167 * Now the secondary core is starting up let it run its
168 * calibrations, then wait for it to finish
170 spin_unlock(&boot_lock
);
176 * Initialise the CPU possible map early - this describes the CPUs
177 * which may be present or become present in the system.
179 static void __init
omap4_smp_init_cpus(void)
181 unsigned int i
= 0, ncores
= 1, cpu_id
;
183 /* Use ARM cpuid check here, as SoC detection will not work so early */
184 cpu_id
= read_cpuid_id() & CPU_MASK
;
185 if (cpu_id
== CPU_CORTEX_A9
) {
187 * Currently we can't call ioremap here because
188 * SoC detection won't work until after init_early.
190 scu_base
= OMAP2_L4_IO_ADDRESS(scu_a9_get_base());
192 ncores
= scu_get_core_count(scu_base
);
193 } else if (cpu_id
== CPU_CORTEX_A15
) {
194 ncores
= OMAP5_CORE_COUNT
;
198 if (ncores
> nr_cpu_ids
) {
199 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
204 for (i
= 0; i
< ncores
; i
++)
205 set_cpu_possible(i
, true);
208 static void __init
omap4_smp_prepare_cpus(unsigned int max_cpus
)
210 void *startup_addr
= omap4_secondary_startup
;
211 void __iomem
*base
= omap_get_wakeupgen_base();
214 * Initialise the SCU and wake up the secondary core using
215 * wakeup_secondary().
218 scu_enable(scu_base
);
220 if (cpu_is_omap446x()) {
221 startup_addr
= omap4460_secondary_startup
;
222 pm44xx_errata
|= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD
;
226 * Write the address of secondary startup routine into the
227 * AuxCoreBoot1 where ROM code will jump and start executing
228 * on secondary core once out of WFE
229 * A barrier is added to ensure that write buffer is drained
231 if (omap_secure_apis_support())
232 omap_auxcoreboot_addr(virt_to_phys(startup_addr
));
234 __raw_writel(virt_to_phys(omap5_secondary_startup
),
235 base
+ OMAP_AUX_CORE_BOOT_1
);
239 struct smp_operations omap4_smp_ops __initdata
= {
240 .smp_init_cpus
= omap4_smp_init_cpus
,
241 .smp_prepare_cpus
= omap4_smp_prepare_cpus
,
242 .smp_secondary_init
= omap4_secondary_init
,
243 .smp_boot_secondary
= omap4_boot_secondary
,
244 #ifdef CONFIG_HOTPLUG_CPU
245 .cpu_die
= omap4_cpu_die
,