2 * OMAP WakeupGen Source file
4 * OMAP WakeupGen is the interrupt controller extension used along
5 * with ARM GIC to wake the CPU out from low power states on
6 * external interrupts. It is responsible for generating wakeup
7 * event from the incoming interrupts and enable bits. It is
8 * implemented in MPU always ON power domain. During normal operation,
9 * WakeupGen delivers external interrupts directly to the GIC.
11 * Copyright (C) 2011 Texas Instruments, Inc.
12 * Santosh Shilimkar <santosh.shilimkar@ti.com>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
19 #include <linux/kernel.h>
20 #include <linux/init.h>
22 #include <linux/irq.h>
23 #include <linux/platform_device.h>
24 #include <linux/cpu.h>
25 #include <linux/notifier.h>
26 #include <linux/cpu_pm.h>
28 #include <asm/hardware/gic.h>
30 #include <mach/omap-wakeupgen.h>
31 #include <mach/omap-secure.h>
34 #include "omap4-sar-layout.h"
37 #define MAX_NR_REG_BANKS 5
39 #define WKG_MASK_ALL 0x00000000
40 #define WKG_UNMASK_ALL 0xffffffff
41 #define CPU_ENA_OFFSET 0x400
44 #define OMAP4_NR_BANKS 4
45 #define OMAP4_NR_IRQS 128
47 static void __iomem
*wakeupgen_base
;
48 static void __iomem
*sar_base
;
49 static DEFINE_SPINLOCK(wakeupgen_lock
);
50 static unsigned int irq_target_cpu
[MAX_IRQS
];
51 static unsigned int irq_banks
= MAX_NR_REG_BANKS
;
52 static unsigned int max_irqs
= MAX_IRQS
;
53 static unsigned int omap_secure_apis
;
56 * Static helper functions.
58 static inline u32
wakeupgen_readl(u8 idx
, u32 cpu
)
60 return __raw_readl(wakeupgen_base
+ OMAP_WKG_ENB_A_0
+
61 (cpu
* CPU_ENA_OFFSET
) + (idx
* 4));
64 static inline void wakeupgen_writel(u32 val
, u8 idx
, u32 cpu
)
66 __raw_writel(val
, wakeupgen_base
+ OMAP_WKG_ENB_A_0
+
67 (cpu
* CPU_ENA_OFFSET
) + (idx
* 4));
70 static inline void sar_writel(u32 val
, u32 offset
, u8 idx
)
72 __raw_writel(val
, sar_base
+ offset
+ (idx
* 4));
75 static inline int _wakeupgen_get_irq_info(u32 irq
, u32
*bit_posn
, u8
*reg_index
)
80 * PPIs and SGIs are not supported.
82 if (irq
< OMAP44XX_IRQ_GIC_START
)
86 * Subtract the GIC offset.
88 spi_irq
= irq
- OMAP44XX_IRQ_GIC_START
;
89 if (spi_irq
> MAX_IRQS
) {
90 pr_err("omap wakeupGen: Invalid IRQ%d\n", irq
);
95 * Each WakeupGen register controls 32 interrupt.
96 * i.e. 1 bit per SPI IRQ
98 *reg_index
= spi_irq
>> 5;
99 *bit_posn
= spi_irq
%= 32;
104 static void _wakeupgen_clear(unsigned int irq
, unsigned int cpu
)
109 if (_wakeupgen_get_irq_info(irq
, &bit_number
, &i
))
112 val
= wakeupgen_readl(i
, cpu
);
113 val
&= ~BIT(bit_number
);
114 wakeupgen_writel(val
, i
, cpu
);
117 static void _wakeupgen_set(unsigned int irq
, unsigned int cpu
)
122 if (_wakeupgen_get_irq_info(irq
, &bit_number
, &i
))
125 val
= wakeupgen_readl(i
, cpu
);
126 val
|= BIT(bit_number
);
127 wakeupgen_writel(val
, i
, cpu
);
131 * Architecture specific Mask extension
133 static void wakeupgen_mask(struct irq_data
*d
)
137 spin_lock_irqsave(&wakeupgen_lock
, flags
);
138 _wakeupgen_clear(d
->irq
, irq_target_cpu
[d
->irq
]);
139 spin_unlock_irqrestore(&wakeupgen_lock
, flags
);
143 * Architecture specific Unmask extension
145 static void wakeupgen_unmask(struct irq_data
*d
)
149 spin_lock_irqsave(&wakeupgen_lock
, flags
);
150 _wakeupgen_set(d
->irq
, irq_target_cpu
[d
->irq
]);
151 spin_unlock_irqrestore(&wakeupgen_lock
, flags
);
154 #ifdef CONFIG_HOTPLUG_CPU
155 static DEFINE_PER_CPU(u32
[MAX_NR_REG_BANKS
], irqmasks
);
157 static void _wakeupgen_save_masks(unsigned int cpu
)
161 for (i
= 0; i
< irq_banks
; i
++)
162 per_cpu(irqmasks
, cpu
)[i
] = wakeupgen_readl(i
, cpu
);
165 static void _wakeupgen_restore_masks(unsigned int cpu
)
169 for (i
= 0; i
< irq_banks
; i
++)
170 wakeupgen_writel(per_cpu(irqmasks
, cpu
)[i
], i
, cpu
);
173 static void _wakeupgen_set_all(unsigned int cpu
, unsigned int reg
)
177 for (i
= 0; i
< irq_banks
; i
++)
178 wakeupgen_writel(reg
, i
, cpu
);
182 * Mask or unmask all interrupts on given CPU.
183 * 0 = Mask all interrupts on the 'cpu'
184 * 1 = Unmask all interrupts on the 'cpu'
185 * Ensure that the initial mask is maintained. This is faster than
186 * iterating through GIC registers to arrive at the correct masks.
188 static void wakeupgen_irqmask_all(unsigned int cpu
, unsigned int set
)
192 spin_lock_irqsave(&wakeupgen_lock
, flags
);
194 _wakeupgen_save_masks(cpu
);
195 _wakeupgen_set_all(cpu
, WKG_MASK_ALL
);
197 _wakeupgen_set_all(cpu
, WKG_UNMASK_ALL
);
198 _wakeupgen_restore_masks(cpu
);
200 spin_unlock_irqrestore(&wakeupgen_lock
, flags
);
205 static inline void omap4_irq_save_context(void)
209 if (omap_rev() == OMAP4430_REV_ES1_0
)
212 for (i
= 0; i
< irq_banks
; i
++) {
213 /* Save the CPUx interrupt mask for IRQ 0 to 127 */
214 val
= wakeupgen_readl(i
, 0);
215 sar_writel(val
, WAKEUPGENENB_OFFSET_CPU0
, i
);
216 val
= wakeupgen_readl(i
, 1);
217 sar_writel(val
, WAKEUPGENENB_OFFSET_CPU1
, i
);
220 * Disable the secure interrupts for CPUx. The restore
221 * code blindly restores secure and non-secure interrupt
222 * masks from SAR RAM. Secure interrupts are not suppose
223 * to be enabled from HLOS. So overwrite the SAR location
224 * so that the secure interrupt remains disabled.
226 sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU0
, i
);
227 sar_writel(0x0, WAKEUPGENENB_SECURE_OFFSET_CPU1
, i
);
230 /* Save AuxBoot* registers */
231 val
= __raw_readl(wakeupgen_base
+ OMAP_AUX_CORE_BOOT_0
);
232 __raw_writel(val
, sar_base
+ AUXCOREBOOT0_OFFSET
);
233 val
= __raw_readl(wakeupgen_base
+ OMAP_AUX_CORE_BOOT_0
);
234 __raw_writel(val
, sar_base
+ AUXCOREBOOT1_OFFSET
);
236 /* Save SyncReq generation logic */
237 val
= __raw_readl(wakeupgen_base
+ OMAP_AUX_CORE_BOOT_0
);
238 __raw_writel(val
, sar_base
+ AUXCOREBOOT0_OFFSET
);
239 val
= __raw_readl(wakeupgen_base
+ OMAP_AUX_CORE_BOOT_0
);
240 __raw_writel(val
, sar_base
+ AUXCOREBOOT1_OFFSET
);
242 /* Save SyncReq generation logic */
243 val
= __raw_readl(wakeupgen_base
+ OMAP_PTMSYNCREQ_MASK
);
244 __raw_writel(val
, sar_base
+ PTMSYNCREQ_MASK_OFFSET
);
245 val
= __raw_readl(wakeupgen_base
+ OMAP_PTMSYNCREQ_EN
);
246 __raw_writel(val
, sar_base
+ PTMSYNCREQ_EN_OFFSET
);
248 /* Set the Backup Bit Mask status */
249 val
= __raw_readl(sar_base
+ SAR_BACKUP_STATUS_OFFSET
);
250 val
|= SAR_BACKUP_STATUS_WAKEUPGEN
;
251 __raw_writel(val
, sar_base
+ SAR_BACKUP_STATUS_OFFSET
);
255 static inline void omap5_irq_save_context(void)
259 for (i
= 0; i
< irq_banks
; i
++) {
260 /* Save the CPUx interrupt mask for IRQ 0 to 159 */
261 val
= wakeupgen_readl(i
, 0);
262 sar_writel(val
, OMAP5_WAKEUPGENENB_OFFSET_CPU0
, i
);
263 val
= wakeupgen_readl(i
, 1);
264 sar_writel(val
, OMAP5_WAKEUPGENENB_OFFSET_CPU1
, i
);
265 sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU0
, i
);
266 sar_writel(0x0, OMAP5_WAKEUPGENENB_SECURE_OFFSET_CPU1
, i
);
269 /* Save AuxBoot* registers */
270 val
= __raw_readl(wakeupgen_base
+ OMAP_AUX_CORE_BOOT_0
);
271 __raw_writel(val
, sar_base
+ OMAP5_AUXCOREBOOT0_OFFSET
);
272 val
= __raw_readl(wakeupgen_base
+ OMAP_AUX_CORE_BOOT_0
);
273 __raw_writel(val
, sar_base
+ OMAP5_AUXCOREBOOT1_OFFSET
);
275 /* Set the Backup Bit Mask status */
276 val
= __raw_readl(sar_base
+ OMAP5_SAR_BACKUP_STATUS_OFFSET
);
277 val
|= SAR_BACKUP_STATUS_WAKEUPGEN
;
278 __raw_writel(val
, sar_base
+ OMAP5_SAR_BACKUP_STATUS_OFFSET
);
283 * Save WakeupGen interrupt context in SAR BANK3. Restore is done by
284 * ROM code. WakeupGen IP is integrated along with GIC to manage the
285 * interrupt wakeups from CPU low power states. It manages
286 * masking/unmasking of Shared peripheral interrupts(SPI). So the
287 * interrupt enable/disable control should be in sync and consistent
288 * at WakeupGen and GIC so that interrupts are not lost.
290 static void irq_save_context(void)
293 sar_base
= omap4_get_sar_ram_base();
295 if (soc_is_omap54xx())
296 omap5_irq_save_context();
298 omap4_irq_save_context();
302 * Clear WakeupGen SAR backup status.
304 static void irq_sar_clear(void)
307 u32 offset
= SAR_BACKUP_STATUS_OFFSET
;
309 if (soc_is_omap54xx())
310 offset
= OMAP5_SAR_BACKUP_STATUS_OFFSET
;
312 val
= __raw_readl(sar_base
+ offset
);
313 val
&= ~SAR_BACKUP_STATUS_WAKEUPGEN
;
314 __raw_writel(val
, sar_base
+ offset
);
318 * Save GIC and Wakeupgen interrupt context using secure API
319 * for HS/EMU devices.
321 static void irq_save_secure_context(void)
324 ret
= omap_secure_dispatcher(OMAP4_HAL_SAVEGIC_INDEX
,
327 if (ret
!= API_HAL_RET_VALUE_OK
)
328 pr_err("GIC and Wakeupgen context save failed\n");
332 #ifdef CONFIG_HOTPLUG_CPU
333 static int __cpuinit
irq_cpu_hotplug_notify(struct notifier_block
*self
,
334 unsigned long action
, void *hcpu
)
336 unsigned int cpu
= (unsigned int)hcpu
;
340 wakeupgen_irqmask_all(cpu
, 0);
343 wakeupgen_irqmask_all(cpu
, 1);
349 static struct notifier_block __refdata irq_hotplug_notifier
= {
350 .notifier_call
= irq_cpu_hotplug_notify
,
353 static void __init
irq_hotplug_init(void)
355 register_hotcpu_notifier(&irq_hotplug_notifier
);
358 static void __init
irq_hotplug_init(void)
363 static int irq_notifier(struct notifier_block
*self
, unsigned long cmd
, void *v
)
366 case CPU_CLUSTER_PM_ENTER
:
367 if (omap_type() == OMAP2_DEVICE_TYPE_GP
)
370 irq_save_secure_context();
372 case CPU_CLUSTER_PM_EXIT
:
373 if (omap_type() == OMAP2_DEVICE_TYPE_GP
)
380 static struct notifier_block irq_notifier_block
= {
381 .notifier_call
= irq_notifier
,
384 static void __init
irq_pm_init(void)
386 /* FIXME: Remove this when MPU OSWR support is added */
387 if (!soc_is_omap54xx())
388 cpu_pm_register_notifier(&irq_notifier_block
);
391 static void __init
irq_pm_init(void)
395 void __iomem
*omap_get_wakeupgen_base(void)
397 return wakeupgen_base
;
400 int omap_secure_apis_support(void)
402 return omap_secure_apis
;
406 * Initialise the wakeupgen module.
408 int __init
omap_wakeupgen_init(void)
411 unsigned int boot_cpu
= smp_processor_id();
413 /* Not supported on OMAP4 ES1.0 silicon */
414 if (omap_rev() == OMAP4430_REV_ES1_0
) {
415 WARN(1, "WakeupGen: Not supported on OMAP4430 ES1.0\n");
419 /* Static mapping, never released */
420 wakeupgen_base
= ioremap(OMAP_WKUPGEN_BASE
, SZ_4K
);
421 if (WARN_ON(!wakeupgen_base
))
424 if (cpu_is_omap44xx()) {
425 irq_banks
= OMAP4_NR_BANKS
;
426 max_irqs
= OMAP4_NR_IRQS
;
427 omap_secure_apis
= 1;
430 /* Clear all IRQ bitmasks at wakeupGen level */
431 for (i
= 0; i
< irq_banks
; i
++) {
432 wakeupgen_writel(0, i
, CPU0_ID
);
433 wakeupgen_writel(0, i
, CPU1_ID
);
437 * Override GIC architecture specific functions to add
438 * OMAP WakeupGen interrupt controller along with GIC
440 gic_arch_extn
.irq_mask
= wakeupgen_mask
;
441 gic_arch_extn
.irq_unmask
= wakeupgen_unmask
;
442 gic_arch_extn
.flags
= IRQCHIP_MASK_ON_SUSPEND
| IRQCHIP_SKIP_SET_WAKE
;
445 * FIXME: Add support to set_smp_affinity() once the core
446 * GIC code has necessary hooks in place.
449 /* Associate all the IRQs to boot CPU like GIC init does. */
450 for (i
= 0; i
< max_irqs
; i
++)
451 irq_target_cpu
[i
] = boot_cpu
;