arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c

   1 /*
   2  * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
   3  *
   4  * Copyright (C) 2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/dmaengine.h>
  14 #include <linux/omap-dma.h>
  15
  16 #include "omap_hwmod.h"
  17 #include "hdq1w.h"
  18
  19 #include "omap_hwmod_common_data.h"
  20
  21 /* UART */
  22
  23 static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
  24         .rev_offs       = 0x50,
  25         .sysc_offs      = 0x54,
  26         .syss_offs      = 0x58,
  27         .sysc_flags     = (SYSC_HAS_SIDLEMODE |
  28                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  29                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  30         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  31         .sysc_fields    = &omap_hwmod_sysc_type1,
  32 };
  33
  34 struct omap_hwmod_class omap2_uart_class = {
  35         .name   = "uart",
  36         .sysc   = &omap2_uart_sysc,
  37 };
  38
  39 /*
  40  * 'dss' class
  41  * display sub-system
  42  */
  43
  44 static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
  45         .rev_offs       = 0x0000,
  46         .sysc_offs      = 0x0010,
  47         .syss_offs      = 0x0014,
  48         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
  49                            SYSS_HAS_RESET_STATUS),
  50         .sysc_fields    = &omap_hwmod_sysc_type1,
  51 };
  52
  53 struct omap_hwmod_class omap2_dss_hwmod_class = {
  54         .name   = "dss",
  55         .sysc   = &omap2_dss_sysc,
  56         .reset  = omap_dss_reset,
  57 };
  58
  59 /*
  60  * 'rfbi' class
  61  * remote frame buffer interface
  62  */
  63
  64 static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
  65         .rev_offs       = 0x0000,
  66         .sysc_offs      = 0x0010,
  67         .syss_offs      = 0x0014,
  68         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
  69                            SYSC_HAS_AUTOIDLE),
  70         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  71         .sysc_fields    = &omap_hwmod_sysc_type1,
  72 };
  73
  74 struct omap_hwmod_class omap2_rfbi_hwmod_class = {
  75         .name   = "rfbi",
  76         .sysc   = &omap2_rfbi_sysc,
  77 };
  78
  79 /*
  80  * 'venc' class
  81  * video encoder
  82  */
  83
  84 struct omap_hwmod_class omap2_venc_hwmod_class = {
  85         .name = "venc",
  86 };
  87
  88
  89 /* Common DMA request line data */
  90 struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
  91         { .name = "rx", .dma_req = 50, },
  92         { .name = "tx", .dma_req = 49, },
  93         { .dma_req = -1 }
  94 };
  95
  96 struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
  97         { .name = "rx", .dma_req = 52, },
  98         { .name = "tx", .dma_req = 51, },
  99         { .dma_req = -1 }
 100 };
 101
 102 struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
 103         { .name = "rx", .dma_req = 54, },
 104         { .name = "tx", .dma_req = 53, },
 105         { .dma_req = -1 }
 106 };
 107
 108 struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
 109         { .name = "tx", .dma_req = 27 },
 110         { .name = "rx", .dma_req = 28 },
 111         { .dma_req = -1 }
 112 };
 113
 114 struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
 115         { .name = "tx", .dma_req = 29 },
 116         { .name = "rx", .dma_req = 30 },
 117         { .dma_req = -1 }
 118 };
 119
 120 struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
 121         { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
 122         { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
 123         { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
 124         { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
 125         { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
 126         { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
 127         { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
 128         { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
 129         { .dma_req = -1 }
 130 };
 131
 132 struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
 133         { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
 134         { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
 135         { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
 136         { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
 137         { .dma_req = -1 }
 138 };
 139
 140 struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
 141         { .name = "rx", .dma_req = 32 },
 142         { .name = "tx", .dma_req = 31 },
 143         { .dma_req = -1 }
 144 };
 145
 146 struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
 147         { .name = "rx", .dma_req = 34 },
 148         { .name = "tx", .dma_req = 33 },
 149         { .dma_req = -1 }
 150 };
 151
 152 struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
 153         { .name = "rx", .dma_req = 18 },
 154         { .name = "tx", .dma_req = 17 },
 155         { .dma_req = -1 }
 156 };
 157
 158 /* Other IP block data */
 159
 160
 161 /*
 162  * omap_hwmod class data
 163  */
 164
 165 struct omap_hwmod_class l3_hwmod_class = {
 166         .name = "l3"
 167 };
 168
 169 struct omap_hwmod_class l4_hwmod_class = {
 170         .name = "l4"
 171 };
 172
 173 struct omap_hwmod_class mpu_hwmod_class = {
 174         .name = "mpu"
 175 };
 176
 177 struct omap_hwmod_class iva_hwmod_class = {
 178         .name = "iva"
 179 };
 180
 181 /* Common MPU IRQ line data */
 182
 183 struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
 184         { .irq = 37 + OMAP_INTC_START, },
 185         { .irq = -1 },
 186 };
 187
 188 struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
 189         { .irq = 38 + OMAP_INTC_START, },
 190         { .irq = -1 },
 191 };
 192
 193 struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
 194         { .irq = 39 + OMAP_INTC_START, },
 195         { .irq = -1 },
 196 };
 197
 198 struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
 199         { .irq = 40 + OMAP_INTC_START, },
 200         { .irq = -1 },
 201 };
 202
 203 struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
 204         { .irq = 41 + OMAP_INTC_START, },
 205         { .irq = -1 },
 206 };
 207
 208 struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
 209         { .irq = 42 + OMAP_INTC_START, },
 210         { .irq = -1 },
 211 };
 212
 213 struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
 214         { .irq = 43 + OMAP_INTC_START, },
 215         { .irq = -1 },
 216 };
 217
 218 struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
 219         { .irq = 44 + OMAP_INTC_START, },
 220         { .irq = -1 },
 221 };
 222
 223 struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
 224         { .irq = 45 + OMAP_INTC_START, },
 225         { .irq = -1 },
 226 };
 227
 228 struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
 229         { .irq = 46 + OMAP_INTC_START, },
 230         { .irq = -1 },
 231 };
 232
 233 struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
 234         { .irq = 47 + OMAP_INTC_START, },
 235         { .irq = -1 },
 236 };
 237
 238 struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
 239         { .irq = 72 + OMAP_INTC_START, },
 240         { .irq = -1 },
 241 };
 242
 243 struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
 244         { .irq = 73 + OMAP_INTC_START, },
 245         { .irq = -1 },
 246 };
 247
 248 struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
 249         { .irq = 74 + OMAP_INTC_START, },
 250         { .irq = -1 },
 251 };
 252
 253 struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
 254         { .irq = 25 + OMAP_INTC_START, },
 255         { .irq = -1 },
 256 };
 257
 258 struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
 259         { .irq = 56 + OMAP_INTC_START, },
 260         { .irq = -1 },
 261 };
 262
 263 struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
 264         { .irq = 57 + OMAP_INTC_START, },
 265         { .irq = -1 },
 266 };
 267
 268 struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
 269         { .irq = 29 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK1 */
 270         { .irq = -1 },
 271 };
 272
 273 struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
 274         { .irq = 30 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK2 */
 275         { .irq = -1 },
 276 };
 277
 278 struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
 279         { .irq = 31 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK3 */
 280         { .irq = -1 },
 281 };
 282
 283 struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
 284         { .irq = 32 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK4 */
 285         { .irq = -1 },
 286 };
 287
 288 struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
 289         { .name = "0", .irq = 12 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ0 */
 290         { .name = "1", .irq = 13 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ1 */
 291         { .name = "2", .irq = 14 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ2 */
 292         { .name = "3", .irq = 15 + OMAP_INTC_START, }, /* INT_24XX_SDMA_IRQ3 */
 293         { .irq = -1 },
 294 };
 295
 296 struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
 297         { .irq = 65 + OMAP_INTC_START, },
 298         { .irq = -1 },
 299 };
 300
 301 struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
 302         { .irq = 66 + OMAP_INTC_START, },
 303         { .irq = -1 },
 304 };
 305
 306 struct omap_hwmod_class_sysconfig omap2_hdq1w_sysc = {
 307         .rev_offs       = 0x0,
 308         .sysc_offs      = 0x14,
 309         .syss_offs      = 0x18,
 310         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 311                            SYSS_HAS_RESET_STATUS),
 312         .sysc_fields    = &omap_hwmod_sysc_type1,
 313 };
 314
 315 struct omap_hwmod_class omap2_hdq1w_class = {
 316         .name   = "hdq1w",
 317         .sysc   = &omap2_hdq1w_sysc,
 318         .reset  = &omap_hdq1w_reset,
 319 };
 320
 321 struct omap_hwmod_irq_info omap2_hdq1w_mpu_irqs[] = {
 322         { .irq = 58 + OMAP_INTC_START, },
 323         { .irq = -1 },
 324 };
 325