arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c

   1 /*
   2  *
   3  * Copyright (C) 2013 Texas Instruments Incorporated
   4  *
   5  * Hwmod common for AM335x and AM43x
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/platform_data/gpio-omap.h>
  18 #include <linux/platform_data/spi-omap2-mcspi.h>
  19 #include "omap_hwmod.h"
  20 #include "i2c.h"
  21 #include "mmc.h"
  22 #include "wd_timer.h"
  23 #include "cm33xx.h"
  24 #include "prm33xx.h"
  25 #include "omap_hwmod_33xx_43xx_common_data.h"
  26 #include "prcm43xx.h"
  27
  28 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
  29 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
  30 #define RSTST(oh, rstst) ((oh).prcm.omap4.rstst_offs = (rstst))
  31
  32 /*
  33  * 'l3' class
  34  * instance(s): l3_main, l3_s, l3_instr
  35  */
  36 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
  37         .name           = "l3",
  38 };
  39
  40 struct omap_hwmod am33xx_l3_main_hwmod = {
  41         .name           = "l3_main",
  42         .class          = &am33xx_l3_hwmod_class,
  43         .clkdm_name     = "l3_clkdm",
  44         .flags          = HWMOD_INIT_NO_IDLE,
  45         .main_clk       = "l3_gclk",
  46         .prcm           = {
  47                 .omap4  = {
  48                         .modulemode     = MODULEMODE_SWCTRL,
  49                 },
  50         },
  51 };
  52
  53 /* l3_s */
  54 struct omap_hwmod am33xx_l3_s_hwmod = {
  55         .name           = "l3_s",
  56         .class          = &am33xx_l3_hwmod_class,
  57         .clkdm_name     = "l3s_clkdm",
  58 };
  59
  60 /* l3_instr */
  61 struct omap_hwmod am33xx_l3_instr_hwmod = {
  62         .name           = "l3_instr",
  63         .class          = &am33xx_l3_hwmod_class,
  64         .clkdm_name     = "l3_clkdm",
  65         .flags          = HWMOD_INIT_NO_IDLE,
  66         .main_clk       = "l3_gclk",
  67         .prcm           = {
  68                 .omap4  = {
  69                         .modulemode     = MODULEMODE_SWCTRL,
  70                 },
  71         },
  72 };
  73
  74 /*
  75  * 'l4' class
  76  * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
  77  */
  78 struct omap_hwmod_class am33xx_l4_hwmod_class = {
  79         .name           = "l4",
  80 };
  81
  82 /* l4_ls */
  83 struct omap_hwmod am33xx_l4_ls_hwmod = {
  84         .name           = "l4_ls",
  85         .class          = &am33xx_l4_hwmod_class,
  86         .clkdm_name     = "l4ls_clkdm",
  87         .flags          = HWMOD_INIT_NO_IDLE,
  88         .main_clk       = "l4ls_gclk",
  89         .prcm           = {
  90                 .omap4  = {
  91                         .modulemode     = MODULEMODE_SWCTRL,
  92                 },
  93         },
  94 };
  95
  96 /* l4_wkup */
  97 struct omap_hwmod am33xx_l4_wkup_hwmod = {
  98         .name           = "l4_wkup",
  99         .class          = &am33xx_l4_hwmod_class,
 100         .clkdm_name     = "l4_wkup_clkdm",
 101         .flags          = HWMOD_INIT_NO_IDLE,
 102         .prcm           = {
 103                 .omap4  = {
 104                         .modulemode     = MODULEMODE_SWCTRL,
 105                 },
 106         },
 107 };
 108
 109 /*
 110  * 'mpu' class
 111  */
 112 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
 113         .name   = "mpu",
 114 };
 115
 116 struct omap_hwmod am33xx_mpu_hwmod = {
 117         .name           = "mpu",
 118         .class          = &am33xx_mpu_hwmod_class,
 119         .clkdm_name     = "mpu_clkdm",
 120         .flags          = HWMOD_INIT_NO_IDLE,
 121         .main_clk       = "dpll_mpu_m2_ck",
 122         .prcm           = {
 123                 .omap4  = {
 124                         .modulemode     = MODULEMODE_SWCTRL,
 125                 },
 126         },
 127 };
 128
 129 /*
 130  * 'wakeup m3' class
 131  * Wakeup controller sub-system under wakeup domain
 132  */
 133 struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
 134         .name           = "wkup_m3",
 135 };
 136
 137 /*
 138  * 'pru-icss' class
 139  * Programmable Real-Time Unit and Industrial Communication Subsystem
 140  */
 141 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
 142         .name   = "pruss",
 143 };
 144
 145 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
 146         { .name = "pruss", .rst_shift = 1 },
 147 };
 148
 149 /* pru-icss */
 150 /* Pseudo hwmod for reset control purpose only */
 151 struct omap_hwmod am33xx_pruss_hwmod = {
 152         .name           = "pruss",
 153         .class          = &am33xx_pruss_hwmod_class,
 154         .clkdm_name     = "pruss_ocp_clkdm",
 155         .main_clk       = "pruss_ocp_gclk",
 156         .prcm           = {
 157                 .omap4  = {
 158                         .modulemode     = MODULEMODE_SWCTRL,
 159                 },
 160         },
 161         .rst_lines      = am33xx_pruss_resets,
 162         .rst_lines_cnt  = ARRAY_SIZE(am33xx_pruss_resets),
 163 };
 164
 165 /* gfx */
 166 /* Pseudo hwmod for reset control purpose only */
 167 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
 168         .name   = "gfx",
 169 };
 170
 171 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
 172         { .name = "gfx", .rst_shift = 0, .st_shift = 0},
 173 };
 174
 175 struct omap_hwmod am33xx_gfx_hwmod = {
 176         .name           = "gfx",
 177         .class          = &am33xx_gfx_hwmod_class,
 178         .clkdm_name     = "gfx_l3_clkdm",
 179         .main_clk       = "gfx_fck_div_ck",
 180         .prcm           = {
 181                 .omap4  = {
 182                         .modulemode     = MODULEMODE_SWCTRL,
 183                 },
 184         },
 185         .rst_lines      = am33xx_gfx_resets,
 186         .rst_lines_cnt  = ARRAY_SIZE(am33xx_gfx_resets),
 187 };
 188
 189 /*
 190  * 'prcm' class
 191  * power and reset manager (whole prcm infrastructure)
 192  */
 193 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
 194         .name   = "prcm",
 195 };
 196
 197 /* prcm */
 198 struct omap_hwmod am33xx_prcm_hwmod = {
 199         .name           = "prcm",
 200         .class          = &am33xx_prcm_hwmod_class,
 201         .clkdm_name     = "l4_wkup_clkdm",
 202 };
 203
 204 /*
 205  * 'aes0' class
 206  */
 207 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
 208         .rev_offs       = 0x80,
 209         .sysc_offs      = 0x84,
 210         .syss_offs      = 0x88,
 211         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 212 };
 213
 214 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
 215         .name           = "aes0",
 216         .sysc           = &am33xx_aes0_sysc,
 217 };
 218
 219 struct omap_hwmod am33xx_aes0_hwmod = {
 220         .name           = "aes",
 221         .class          = &am33xx_aes0_hwmod_class,
 222         .clkdm_name     = "l3_clkdm",
 223         .main_clk       = "aes0_fck",
 224         .prcm           = {
 225                 .omap4  = {
 226                         .modulemode     = MODULEMODE_SWCTRL,
 227                 },
 228         },
 229 };
 230
 231 /* sha0 HIB2 (the 'P' (public) device) */
 232 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
 233         .rev_offs       = 0x100,
 234         .sysc_offs      = 0x110,
 235         .syss_offs      = 0x114,
 236         .sysc_flags     = SYSS_HAS_RESET_STATUS,
 237 };
 238
 239 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
 240         .name           = "sha0",
 241         .sysc           = &am33xx_sha0_sysc,
 242 };
 243
 244 struct omap_hwmod am33xx_sha0_hwmod = {
 245         .name           = "sham",
 246         .class          = &am33xx_sha0_hwmod_class,
 247         .clkdm_name     = "l3_clkdm",
 248         .main_clk       = "l3_gclk",
 249         .prcm           = {
 250                 .omap4  = {
 251                         .modulemode     = MODULEMODE_SWCTRL,
 252                 },
 253         },
 254 };
 255
 256 /* ocmcram */
 257 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
 258         .name = "ocmcram",
 259 };
 260
 261 struct omap_hwmod am33xx_ocmcram_hwmod = {
 262         .name           = "ocmcram",
 263         .class          = &am33xx_ocmcram_hwmod_class,
 264         .clkdm_name     = "l3_clkdm",
 265         .flags          = HWMOD_INIT_NO_IDLE,
 266         .main_clk       = "l3_gclk",
 267         .prcm           = {
 268                 .omap4  = {
 269                         .modulemode     = MODULEMODE_SWCTRL,
 270                 },
 271         },
 272 };
 273
 274 /* 'smartreflex' class */
 275 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
 276         .name           = "smartreflex",
 277 };
 278
 279 /* smartreflex0 */
 280 struct omap_hwmod am33xx_smartreflex0_hwmod = {
 281         .name           = "smartreflex0",
 282         .class          = &am33xx_smartreflex_hwmod_class,
 283         .clkdm_name     = "l4_wkup_clkdm",
 284         .main_clk       = "smartreflex0_fck",
 285         .prcm           = {
 286                 .omap4  = {
 287                         .modulemode     = MODULEMODE_SWCTRL,
 288                 },
 289         },
 290 };
 291
 292 /* smartreflex1 */
 293 struct omap_hwmod am33xx_smartreflex1_hwmod = {
 294         .name           = "smartreflex1",
 295         .class          = &am33xx_smartreflex_hwmod_class,
 296         .clkdm_name     = "l4_wkup_clkdm",
 297         .main_clk       = "smartreflex1_fck",
 298         .prcm           = {
 299                 .omap4  = {
 300                         .modulemode     = MODULEMODE_SWCTRL,
 301                 },
 302         },
 303 };
 304
 305 /*
 306  * 'control' module class
 307  */
 308 struct omap_hwmod_class am33xx_control_hwmod_class = {
 309         .name           = "control",
 310 };
 311
 312 /*
 313  * 'cpgmac' class
 314  * cpsw/cpgmac sub system
 315  */
 316 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
 317         .rev_offs       = 0x0,
 318         .sysc_offs      = 0x8,
 319         .syss_offs      = 0x4,
 320         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 321                            SYSS_HAS_RESET_STATUS),
 322         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
 323                            MSTANDBY_NO),
 324         .sysc_fields    = &omap_hwmod_sysc_type3,
 325 };
 326
 327 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
 328         .name           = "cpgmac0",
 329         .sysc           = &am33xx_cpgmac_sysc,
 330 };
 331
 332 struct omap_hwmod am33xx_cpgmac0_hwmod = {
 333         .name           = "cpgmac0",
 334         .class          = &am33xx_cpgmac0_hwmod_class,
 335         .clkdm_name     = "cpsw_125mhz_clkdm",
 336         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
 337         .main_clk       = "cpsw_125mhz_gclk",
 338         .mpu_rt_idx     = 1,
 339         .prcm           = {
 340                 .omap4  = {
 341                         .modulemode     = MODULEMODE_SWCTRL,
 342                 },
 343         },
 344 };
 345
 346 /*
 347  * mdio class
 348  */
 349 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
 350         .name           = "davinci_mdio",
 351 };
 352
 353 struct omap_hwmod am33xx_mdio_hwmod = {
 354         .name           = "davinci_mdio",
 355         .class          = &am33xx_mdio_hwmod_class,
 356         .clkdm_name     = "cpsw_125mhz_clkdm",
 357         .main_clk       = "cpsw_125mhz_gclk",
 358 };
 359
 360 /*
 361  * dcan class
 362  */
 363 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
 364         .name = "d_can",
 365 };
 366
 367 /* dcan0 */
 368 struct omap_hwmod am33xx_dcan0_hwmod = {
 369         .name           = "d_can0",
 370         .class          = &am33xx_dcan_hwmod_class,
 371         .clkdm_name     = "l4ls_clkdm",
 372         .main_clk       = "dcan0_fck",
 373         .prcm           = {
 374                 .omap4  = {
 375                         .modulemode     = MODULEMODE_SWCTRL,
 376                 },
 377         },
 378 };
 379
 380 /* dcan1 */
 381 struct omap_hwmod am33xx_dcan1_hwmod = {
 382         .name           = "d_can1",
 383         .class          = &am33xx_dcan_hwmod_class,
 384         .clkdm_name     = "l4ls_clkdm",
 385         .main_clk       = "dcan1_fck",
 386         .prcm           = {
 387                 .omap4  = {
 388                         .modulemode     = MODULEMODE_SWCTRL,
 389                 },
 390         },
 391 };
 392
 393 /* elm */
 394 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
 395         .rev_offs       = 0x0000,
 396         .sysc_offs      = 0x0010,
 397         .syss_offs      = 0x0014,
 398         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 399                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 400                         SYSS_HAS_RESET_STATUS),
 401         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 402         .sysc_fields    = &omap_hwmod_sysc_type1,
 403 };
 404
 405 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
 406         .name           = "elm",
 407         .sysc           = &am33xx_elm_sysc,
 408 };
 409
 410 struct omap_hwmod am33xx_elm_hwmod = {
 411         .name           = "elm",
 412         .class          = &am33xx_elm_hwmod_class,
 413         .clkdm_name     = "l4ls_clkdm",
 414         .main_clk       = "l4ls_gclk",
 415         .prcm           = {
 416                 .omap4  = {
 417                         .modulemode     = MODULEMODE_SWCTRL,
 418                 },
 419         },
 420 };
 421
 422 /* pwmss  */
 423 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
 424         .rev_offs       = 0x0,
 425         .sysc_offs      = 0x4,
 426         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
 427         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 428                         SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 429                         MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 430         .sysc_fields    = &omap_hwmod_sysc_type2,
 431 };
 432
 433 struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
 434         .name           = "epwmss",
 435         .sysc           = &am33xx_epwmss_sysc,
 436 };
 437
 438 static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
 439         .name           = "ecap",
 440 };
 441
 442 static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
 443         .name           = "eqep",
 444 };
 445
 446 struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
 447         .name           = "ehrpwm",
 448 };
 449
 450 /* epwmss0 */
 451 struct omap_hwmod am33xx_epwmss0_hwmod = {
 452         .name           = "epwmss0",
 453         .class          = &am33xx_epwmss_hwmod_class,
 454         .clkdm_name     = "l4ls_clkdm",
 455         .main_clk       = "l4ls_gclk",
 456         .prcm           = {
 457                 .omap4  = {
 458                         .modulemode     = MODULEMODE_SWCTRL,
 459                 },
 460         },
 461 };
 462
 463 /* ecap0 */
 464 struct omap_hwmod am33xx_ecap0_hwmod = {
 465         .name           = "ecap0",
 466         .class          = &am33xx_ecap_hwmod_class,
 467         .clkdm_name     = "l4ls_clkdm",
 468         .main_clk       = "l4ls_gclk",
 469 };
 470
 471 /* eqep0 */
 472 struct omap_hwmod am33xx_eqep0_hwmod = {
 473         .name           = "eqep0",
 474         .class          = &am33xx_eqep_hwmod_class,
 475         .clkdm_name     = "l4ls_clkdm",
 476         .main_clk       = "l4ls_gclk",
 477 };
 478
 479 /* ehrpwm0 */
 480 struct omap_hwmod am33xx_ehrpwm0_hwmod = {
 481         .name           = "ehrpwm0",
 482         .class          = &am33xx_ehrpwm_hwmod_class,
 483         .clkdm_name     = "l4ls_clkdm",
 484         .main_clk       = "l4ls_gclk",
 485 };
 486
 487 /* epwmss1 */
 488 struct omap_hwmod am33xx_epwmss1_hwmod = {
 489         .name           = "epwmss1",
 490         .class          = &am33xx_epwmss_hwmod_class,
 491         .clkdm_name     = "l4ls_clkdm",
 492         .main_clk       = "l4ls_gclk",
 493         .prcm           = {
 494                 .omap4  = {
 495                         .modulemode     = MODULEMODE_SWCTRL,
 496                 },
 497         },
 498 };
 499
 500 /* ecap1 */
 501 struct omap_hwmod am33xx_ecap1_hwmod = {
 502         .name           = "ecap1",
 503         .class          = &am33xx_ecap_hwmod_class,
 504         .clkdm_name     = "l4ls_clkdm",
 505         .main_clk       = "l4ls_gclk",
 506 };
 507
 508 /* eqep1 */
 509 struct omap_hwmod am33xx_eqep1_hwmod = {
 510         .name           = "eqep1",
 511         .class          = &am33xx_eqep_hwmod_class,
 512         .clkdm_name     = "l4ls_clkdm",
 513         .main_clk       = "l4ls_gclk",
 514 };
 515
 516 /* ehrpwm1 */
 517 struct omap_hwmod am33xx_ehrpwm1_hwmod = {
 518         .name           = "ehrpwm1",
 519         .class          = &am33xx_ehrpwm_hwmod_class,
 520         .clkdm_name     = "l4ls_clkdm",
 521         .main_clk       = "l4ls_gclk",
 522 };
 523
 524 /* epwmss2 */
 525 struct omap_hwmod am33xx_epwmss2_hwmod = {
 526         .name           = "epwmss2",
 527         .class          = &am33xx_epwmss_hwmod_class,
 528         .clkdm_name     = "l4ls_clkdm",
 529         .main_clk       = "l4ls_gclk",
 530         .prcm           = {
 531                 .omap4  = {
 532                         .modulemode     = MODULEMODE_SWCTRL,
 533                 },
 534         },
 535 };
 536
 537 /* ecap2 */
 538 struct omap_hwmod am33xx_ecap2_hwmod = {
 539         .name           = "ecap2",
 540         .class          = &am33xx_ecap_hwmod_class,
 541         .clkdm_name     = "l4ls_clkdm",
 542         .main_clk       = "l4ls_gclk",
 543 };
 544
 545 /* eqep2 */
 546 struct omap_hwmod am33xx_eqep2_hwmod = {
 547         .name           = "eqep2",
 548         .class          = &am33xx_eqep_hwmod_class,
 549         .clkdm_name     = "l4ls_clkdm",
 550         .main_clk       = "l4ls_gclk",
 551 };
 552
 553 /* ehrpwm2 */
 554 struct omap_hwmod am33xx_ehrpwm2_hwmod = {
 555         .name           = "ehrpwm2",
 556         .class          = &am33xx_ehrpwm_hwmod_class,
 557         .clkdm_name     = "l4ls_clkdm",
 558         .main_clk       = "l4ls_gclk",
 559 };
 560
 561 /*
 562  * 'gpio' class: for gpio 0,1,2,3
 563  */
 564 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
 565         .rev_offs       = 0x0000,
 566         .sysc_offs      = 0x0010,
 567         .syss_offs      = 0x0114,
 568         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
 569                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 570                           SYSS_HAS_RESET_STATUS),
 571         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 572                           SIDLE_SMART_WKUP),
 573         .sysc_fields    = &omap_hwmod_sysc_type1,
 574 };
 575
 576 struct omap_hwmod_class am33xx_gpio_hwmod_class = {
 577         .name           = "gpio",
 578         .sysc           = &am33xx_gpio_sysc,
 579         .rev            = 2,
 580 };
 581
 582 struct omap_gpio_dev_attr gpio_dev_attr = {
 583         .bank_width     = 32,
 584         .dbck_flag      = true,
 585 };
 586
 587 /* gpio1 */
 588 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 589         { .role = "dbclk", .clk = "gpio1_dbclk" },
 590 };
 591
 592 struct omap_hwmod am33xx_gpio1_hwmod = {
 593         .name           = "gpio2",
 594         .class          = &am33xx_gpio_hwmod_class,
 595         .clkdm_name     = "l4ls_clkdm",
 596         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 597         .main_clk       = "l4ls_gclk",
 598         .prcm           = {
 599                 .omap4  = {
 600                         .modulemode     = MODULEMODE_SWCTRL,
 601                 },
 602         },
 603         .opt_clks       = gpio1_opt_clks,
 604         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 605         .dev_attr       = &gpio_dev_attr,
 606 };
 607
 608 /* gpio2 */
 609 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 610         { .role = "dbclk", .clk = "gpio2_dbclk" },
 611 };
 612
 613 struct omap_hwmod am33xx_gpio2_hwmod = {
 614         .name           = "gpio3",
 615         .class          = &am33xx_gpio_hwmod_class,
 616         .clkdm_name     = "l4ls_clkdm",
 617         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 618         .main_clk       = "l4ls_gclk",
 619         .prcm           = {
 620                 .omap4  = {
 621                         .modulemode     = MODULEMODE_SWCTRL,
 622                 },
 623         },
 624         .opt_clks       = gpio2_opt_clks,
 625         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 626         .dev_attr       = &gpio_dev_attr,
 627 };
 628
 629 /* gpio3 */
 630 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 631         { .role = "dbclk", .clk = "gpio3_dbclk" },
 632 };
 633
 634 struct omap_hwmod am33xx_gpio3_hwmod = {
 635         .name           = "gpio4",
 636         .class          = &am33xx_gpio_hwmod_class,
 637         .clkdm_name     = "l4ls_clkdm",
 638         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 639         .main_clk       = "l4ls_gclk",
 640         .prcm           = {
 641                 .omap4  = {
 642                         .modulemode     = MODULEMODE_SWCTRL,
 643                 },
 644         },
 645         .opt_clks       = gpio3_opt_clks,
 646         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 647         .dev_attr       = &gpio_dev_attr,
 648 };
 649
 650 /* gpmc */
 651 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
 652         .rev_offs       = 0x0,
 653         .sysc_offs      = 0x10,
 654         .syss_offs      = 0x14,
 655         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 656                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 657         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 658         .sysc_fields    = &omap_hwmod_sysc_type1,
 659 };
 660
 661 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
 662         .name           = "gpmc",
 663         .sysc           = &gpmc_sysc,
 664 };
 665
 666 struct omap_hwmod am33xx_gpmc_hwmod = {
 667         .name           = "gpmc",
 668         .class          = &am33xx_gpmc_hwmod_class,
 669         .clkdm_name     = "l3s_clkdm",
 670         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
 671         .main_clk       = "l3s_gclk",
 672         .prcm           = {
 673                 .omap4  = {
 674                         .modulemode     = MODULEMODE_SWCTRL,
 675                 },
 676         },
 677 };
 678
 679 /* 'i2c' class */
 680 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
 681         .sysc_offs      = 0x0010,
 682         .syss_offs      = 0x0090,
 683         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 684                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 685                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 686         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 687                           SIDLE_SMART_WKUP),
 688         .sysc_fields    = &omap_hwmod_sysc_type1,
 689 };
 690
 691 static struct omap_hwmod_class i2c_class = {
 692         .name           = "i2c",
 693         .sysc           = &am33xx_i2c_sysc,
 694         .rev            = OMAP_I2C_IP_VERSION_2,
 695         .reset          = &omap_i2c_reset,
 696 };
 697
 698 static struct omap_i2c_dev_attr i2c_dev_attr = {
 699         .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
 700 };
 701
 702 /* i2c1 */
 703 struct omap_hwmod am33xx_i2c1_hwmod = {
 704         .name           = "i2c1",
 705         .class          = &i2c_class,
 706         .clkdm_name     = "l4_wkup_clkdm",
 707         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 708         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
 709         .prcm           = {
 710                 .omap4  = {
 711                         .modulemode     = MODULEMODE_SWCTRL,
 712                 },
 713         },
 714         .dev_attr       = &i2c_dev_attr,
 715 };
 716
 717 /* i2c1 */
 718 struct omap_hwmod am33xx_i2c2_hwmod = {
 719         .name           = "i2c2",
 720         .class          = &i2c_class,
 721         .clkdm_name     = "l4ls_clkdm",
 722         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 723         .main_clk       = "dpll_per_m2_div4_ck",
 724         .prcm           = {
 725                 .omap4 = {
 726                         .modulemode     = MODULEMODE_SWCTRL,
 727                 },
 728         },
 729         .dev_attr       = &i2c_dev_attr,
 730 };
 731
 732 /* i2c3 */
 733 struct omap_hwmod am33xx_i2c3_hwmod = {
 734         .name           = "i2c3",
 735         .class          = &i2c_class,
 736         .clkdm_name     = "l4ls_clkdm",
 737         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 738         .main_clk       = "dpll_per_m2_div4_ck",
 739         .prcm           = {
 740                 .omap4  = {
 741                         .modulemode     = MODULEMODE_SWCTRL,
 742                 },
 743         },
 744         .dev_attr       = &i2c_dev_attr,
 745 };
 746
 747 /*
 748  * 'mailbox' class
 749  * mailbox module allowing communication between the on-chip processors using a
 750  * queued mailbox-interrupt mechanism.
 751  */
 752 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
 753         .rev_offs       = 0x0000,
 754         .sysc_offs      = 0x0010,
 755         .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 756                           SYSC_HAS_SOFTRESET),
 757         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 758         .sysc_fields    = &omap_hwmod_sysc_type2,
 759 };
 760
 761 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
 762         .name   = "mailbox",
 763         .sysc   = &am33xx_mailbox_sysc,
 764 };
 765
 766 struct omap_hwmod am33xx_mailbox_hwmod = {
 767         .name           = "mailbox",
 768         .class          = &am33xx_mailbox_hwmod_class,
 769         .clkdm_name     = "l4ls_clkdm",
 770         .main_clk       = "l4ls_gclk",
 771         .prcm = {
 772                 .omap4 = {
 773                         .modulemode     = MODULEMODE_SWCTRL,
 774                 },
 775         },
 776 };
 777
 778 /*
 779  * 'mcasp' class
 780  */
 781 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
 782         .rev_offs       = 0x0,
 783         .sysc_offs      = 0x4,
 784         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 785         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 786         .sysc_fields    = &omap_hwmod_sysc_type3,
 787 };
 788
 789 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
 790         .name           = "mcasp",
 791         .sysc           = &am33xx_mcasp_sysc,
 792 };
 793
 794 /* mcasp0 */
 795 struct omap_hwmod am33xx_mcasp0_hwmod = {
 796         .name           = "mcasp0",
 797         .class          = &am33xx_mcasp_hwmod_class,
 798         .clkdm_name     = "l3s_clkdm",
 799         .main_clk       = "mcasp0_fck",
 800         .prcm           = {
 801                 .omap4  = {
 802                         .modulemode     = MODULEMODE_SWCTRL,
 803                 },
 804         },
 805 };
 806
 807 /* mcasp1 */
 808 struct omap_hwmod am33xx_mcasp1_hwmod = {
 809         .name           = "mcasp1",
 810         .class          = &am33xx_mcasp_hwmod_class,
 811         .clkdm_name     = "l3s_clkdm",
 812         .main_clk       = "mcasp1_fck",
 813         .prcm           = {
 814                 .omap4  = {
 815                         .modulemode     = MODULEMODE_SWCTRL,
 816                 },
 817         },
 818 };
 819
 820 /* 'mmc' class */
 821 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
 822         .rev_offs       = 0x1fc,
 823         .sysc_offs      = 0x10,
 824         .syss_offs      = 0x14,
 825         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 826                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 827                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 828         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 829         .sysc_fields    = &omap_hwmod_sysc_type1,
 830 };
 831
 832 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
 833         .name           = "mmc",
 834         .sysc           = &am33xx_mmc_sysc,
 835 };
 836
 837 /* mmc0 */
 838 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
 839         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 840 };
 841
 842 struct omap_hwmod am33xx_mmc0_hwmod = {
 843         .name           = "mmc1",
 844         .class          = &am33xx_mmc_hwmod_class,
 845         .clkdm_name     = "l4ls_clkdm",
 846         .main_clk       = "mmc_clk",
 847         .prcm           = {
 848                 .omap4  = {
 849                         .modulemode     = MODULEMODE_SWCTRL,
 850                 },
 851         },
 852         .dev_attr       = &am33xx_mmc0_dev_attr,
 853 };
 854
 855 /* mmc1 */
 856 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
 857         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 858 };
 859
 860 struct omap_hwmod am33xx_mmc1_hwmod = {
 861         .name           = "mmc2",
 862         .class          = &am33xx_mmc_hwmod_class,
 863         .clkdm_name     = "l4ls_clkdm",
 864         .main_clk       = "mmc_clk",
 865         .prcm           = {
 866                 .omap4  = {
 867                         .modulemode     = MODULEMODE_SWCTRL,
 868                 },
 869         },
 870         .dev_attr       = &am33xx_mmc1_dev_attr,
 871 };
 872
 873 /* mmc2 */
 874 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
 875         .flags          = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
 876 };
 877 struct omap_hwmod am33xx_mmc2_hwmod = {
 878         .name           = "mmc3",
 879         .class          = &am33xx_mmc_hwmod_class,
 880         .clkdm_name     = "l3s_clkdm",
 881         .main_clk       = "mmc_clk",
 882         .prcm           = {
 883                 .omap4  = {
 884                         .modulemode     = MODULEMODE_SWCTRL,
 885                 },
 886         },
 887         .dev_attr       = &am33xx_mmc2_dev_attr,
 888 };
 889
 890 /*
 891  * 'rtc' class
 892  * rtc subsystem
 893  */
 894 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
 895         .rev_offs       = 0x0074,
 896         .sysc_offs      = 0x0078,
 897         .sysc_flags     = SYSC_HAS_SIDLEMODE,
 898         .idlemodes      = (SIDLE_FORCE | SIDLE_NO |
 899                           SIDLE_SMART | SIDLE_SMART_WKUP),
 900         .sysc_fields    = &omap_hwmod_sysc_type3,
 901 };
 902
 903 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
 904         .name           = "rtc",
 905         .sysc           = &am33xx_rtc_sysc,
 906 };
 907
 908 struct omap_hwmod am33xx_rtc_hwmod = {
 909         .name           = "rtc",
 910         .class          = &am33xx_rtc_hwmod_class,
 911         .clkdm_name     = "l4_rtc_clkdm",
 912         .main_clk       = "clk_32768_ck",
 913         .prcm           = {
 914                 .omap4  = {
 915                         .modulemode     = MODULEMODE_SWCTRL,
 916                 },
 917         },
 918 };
 919
 920 /* 'spi' class */
 921 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
 922         .rev_offs       = 0x0000,
 923         .sysc_offs      = 0x0110,
 924         .syss_offs      = 0x0114,
 925         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 926                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 927                           SYSS_HAS_RESET_STATUS),
 928         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 929         .sysc_fields    = &omap_hwmod_sysc_type1,
 930 };
 931
 932 struct omap_hwmod_class am33xx_spi_hwmod_class = {
 933         .name           = "mcspi",
 934         .sysc           = &am33xx_mcspi_sysc,
 935         .rev            = OMAP4_MCSPI_REV,
 936 };
 937
 938 /* spi0 */
 939 struct omap2_mcspi_dev_attr mcspi_attrib = {
 940         .num_chipselect = 2,
 941 };
 942 struct omap_hwmod am33xx_spi0_hwmod = {
 943         .name           = "spi0",
 944         .class          = &am33xx_spi_hwmod_class,
 945         .clkdm_name     = "l4ls_clkdm",
 946         .main_clk       = "dpll_per_m2_div4_ck",
 947         .prcm           = {
 948                 .omap4  = {
 949                         .modulemode     = MODULEMODE_SWCTRL,
 950                 },
 951         },
 952         .dev_attr       = &mcspi_attrib,
 953 };
 954
 955 /* spi1 */
 956 struct omap_hwmod am33xx_spi1_hwmod = {
 957         .name           = "spi1",
 958         .class          = &am33xx_spi_hwmod_class,
 959         .clkdm_name     = "l4ls_clkdm",
 960         .main_clk       = "dpll_per_m2_div4_ck",
 961         .prcm           = {
 962                 .omap4  = {
 963                         .modulemode     = MODULEMODE_SWCTRL,
 964                 },
 965         },
 966         .dev_attr       = &mcspi_attrib,
 967 };
 968
 969 /*
 970  * 'spinlock' class
 971  * spinlock provides hardware assistance for synchronizing the
 972  * processes running on multiple processors
 973  */
 974
 975 static struct omap_hwmod_class_sysconfig am33xx_spinlock_sysc = {
 976         .rev_offs       = 0x0000,
 977         .sysc_offs      = 0x0010,
 978         .syss_offs      = 0x0014,
 979         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 980                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 981                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 982         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 983         .sysc_fields    = &omap_hwmod_sysc_type1,
 984 };
 985
 986 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
 987         .name           = "spinlock",
 988         .sysc           = &am33xx_spinlock_sysc,
 989 };
 990
 991 struct omap_hwmod am33xx_spinlock_hwmod = {
 992         .name           = "spinlock",
 993         .class          = &am33xx_spinlock_hwmod_class,
 994         .clkdm_name     = "l4ls_clkdm",
 995         .main_clk       = "l4ls_gclk",
 996         .prcm           = {
 997                 .omap4  = {
 998                         .modulemode     = MODULEMODE_SWCTRL,
 999                 },
1000         },
1001 };
1002
1003 /* 'timer 2-7' class */
1004 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1005         .rev_offs       = 0x0000,
1006         .sysc_offs      = 0x0010,
1007         .syss_offs      = 0x0014,
1008         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1009         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1010                           SIDLE_SMART_WKUP),
1011         .sysc_fields    = &omap_hwmod_sysc_type2,
1012 };
1013
1014 struct omap_hwmod_class am33xx_timer_hwmod_class = {
1015         .name           = "timer",
1016         .sysc           = &am33xx_timer_sysc,
1017 };
1018
1019 /* timer1 1ms */
1020 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1021         .rev_offs       = 0x0000,
1022         .sysc_offs      = 0x0010,
1023         .syss_offs      = 0x0014,
1024         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1025                         SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1026                         SYSS_HAS_RESET_STATUS),
1027         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1028         .sysc_fields    = &omap_hwmod_sysc_type1,
1029 };
1030
1031 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1032         .name           = "timer",
1033         .sysc           = &am33xx_timer1ms_sysc,
1034 };
1035
1036 struct omap_hwmod am33xx_timer1_hwmod = {
1037         .name           = "timer1",
1038         .class          = &am33xx_timer1ms_hwmod_class,
1039         .clkdm_name     = "l4_wkup_clkdm",
1040         .main_clk       = "timer1_fck",
1041         .prcm           = {
1042                 .omap4  = {
1043                         .modulemode     = MODULEMODE_SWCTRL,
1044                 },
1045         },
1046 };
1047
1048 struct omap_hwmod am33xx_timer2_hwmod = {
1049         .name           = "timer2",
1050         .class          = &am33xx_timer_hwmod_class,
1051         .clkdm_name     = "l4ls_clkdm",
1052         .main_clk       = "timer2_fck",
1053         .prcm           = {
1054                 .omap4  = {
1055                         .modulemode     = MODULEMODE_SWCTRL,
1056                 },
1057         },
1058 };
1059
1060 struct omap_hwmod am33xx_timer3_hwmod = {
1061         .name           = "timer3",
1062         .class          = &am33xx_timer_hwmod_class,
1063         .clkdm_name     = "l4ls_clkdm",
1064         .main_clk       = "timer3_fck",
1065         .prcm           = {
1066                 .omap4  = {
1067                         .modulemode     = MODULEMODE_SWCTRL,
1068                 },
1069         },
1070 };
1071
1072 struct omap_hwmod am33xx_timer4_hwmod = {
1073         .name           = "timer4",
1074         .class          = &am33xx_timer_hwmod_class,
1075         .clkdm_name     = "l4ls_clkdm",
1076         .main_clk       = "timer4_fck",
1077         .prcm           = {
1078                 .omap4  = {
1079                         .modulemode     = MODULEMODE_SWCTRL,
1080                 },
1081         },
1082 };
1083
1084 struct omap_hwmod am33xx_timer5_hwmod = {
1085         .name           = "timer5",
1086         .class          = &am33xx_timer_hwmod_class,
1087         .clkdm_name     = "l4ls_clkdm",
1088         .main_clk       = "timer5_fck",
1089         .prcm           = {
1090                 .omap4  = {
1091                         .modulemode     = MODULEMODE_SWCTRL,
1092                 },
1093         },
1094 };
1095
1096 struct omap_hwmod am33xx_timer6_hwmod = {
1097         .name           = "timer6",
1098         .class          = &am33xx_timer_hwmod_class,
1099         .clkdm_name     = "l4ls_clkdm",
1100         .main_clk       = "timer6_fck",
1101         .prcm           = {
1102                 .omap4  = {
1103                         .modulemode     = MODULEMODE_SWCTRL,
1104                 },
1105         },
1106 };
1107
1108 struct omap_hwmod am33xx_timer7_hwmod = {
1109         .name           = "timer7",
1110         .class          = &am33xx_timer_hwmod_class,
1111         .clkdm_name     = "l4ls_clkdm",
1112         .main_clk       = "timer7_fck",
1113         .prcm           = {
1114                 .omap4  = {
1115                         .modulemode     = MODULEMODE_SWCTRL,
1116                 },
1117         },
1118 };
1119
1120 /* tpcc */
1121 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1122         .name           = "tpcc",
1123 };
1124
1125 struct omap_hwmod am33xx_tpcc_hwmod = {
1126         .name           = "tpcc",
1127         .class          = &am33xx_tpcc_hwmod_class,
1128         .clkdm_name     = "l3_clkdm",
1129         .main_clk       = "l3_gclk",
1130         .prcm           = {
1131                 .omap4  = {
1132                         .modulemode     = MODULEMODE_SWCTRL,
1133                 },
1134         },
1135 };
1136
1137 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1138         .rev_offs       = 0x0,
1139         .sysc_offs      = 0x10,
1140         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1141                           SYSC_HAS_MIDLEMODE),
1142         .idlemodes      = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1143         .sysc_fields    = &omap_hwmod_sysc_type2,
1144 };
1145
1146 /* 'tptc' class */
1147 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1148         .name           = "tptc",
1149         .sysc           = &am33xx_tptc_sysc,
1150 };
1151
1152 /* tptc0 */
1153 struct omap_hwmod am33xx_tptc0_hwmod = {
1154         .name           = "tptc0",
1155         .class          = &am33xx_tptc_hwmod_class,
1156         .clkdm_name     = "l3_clkdm",
1157         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1158         .main_clk       = "l3_gclk",
1159         .prcm           = {
1160                 .omap4  = {
1161                         .modulemode     = MODULEMODE_SWCTRL,
1162                 },
1163         },
1164 };
1165
1166 /* tptc1 */
1167 struct omap_hwmod am33xx_tptc1_hwmod = {
1168         .name           = "tptc1",
1169         .class          = &am33xx_tptc_hwmod_class,
1170         .clkdm_name     = "l3_clkdm",
1171         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1172         .main_clk       = "l3_gclk",
1173         .prcm           = {
1174                 .omap4  = {
1175                         .modulemode     = MODULEMODE_SWCTRL,
1176                 },
1177         },
1178 };
1179
1180 /* tptc2 */
1181 struct omap_hwmod am33xx_tptc2_hwmod = {
1182         .name           = "tptc2",
1183         .class          = &am33xx_tptc_hwmod_class,
1184         .clkdm_name     = "l3_clkdm",
1185         .flags          = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1186         .main_clk       = "l3_gclk",
1187         .prcm           = {
1188                 .omap4  = {
1189                         .modulemode     = MODULEMODE_SWCTRL,
1190                 },
1191         },
1192 };
1193
1194 /* 'uart' class */
1195 static struct omap_hwmod_class_sysconfig uart_sysc = {
1196         .rev_offs       = 0x50,
1197         .sysc_offs      = 0x54,
1198         .syss_offs      = 0x58,
1199         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1200                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1201         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1202                           SIDLE_SMART_WKUP),
1203         .sysc_fields    = &omap_hwmod_sysc_type1,
1204 };
1205
1206 static struct omap_hwmod_class uart_class = {
1207         .name           = "uart",
1208         .sysc           = &uart_sysc,
1209 };
1210
1211 struct omap_hwmod am33xx_uart1_hwmod = {
1212         .name           = "uart1",
1213         .class          = &uart_class,
1214         .clkdm_name     = "l4_wkup_clkdm",
1215         .flags          = DEBUG_AM33XXUART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
1216         .main_clk       = "dpll_per_m2_div4_wkupdm_ck",
1217         .prcm           = {
1218                 .omap4  = {
1219                         .modulemode     = MODULEMODE_SWCTRL,
1220                 },
1221         },
1222 };
1223
1224 struct omap_hwmod am33xx_uart2_hwmod = {
1225         .name           = "uart2",
1226         .class          = &uart_class,
1227         .clkdm_name     = "l4ls_clkdm",
1228         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1229         .main_clk       = "dpll_per_m2_div4_ck",
1230         .prcm           = {
1231                 .omap4  = {
1232                         .modulemode     = MODULEMODE_SWCTRL,
1233                 },
1234         },
1235 };
1236
1237 /* uart3 */
1238 struct omap_hwmod am33xx_uart3_hwmod = {
1239         .name           = "uart3",
1240         .class          = &uart_class,
1241         .clkdm_name     = "l4ls_clkdm",
1242         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1243         .main_clk       = "dpll_per_m2_div4_ck",
1244         .prcm           = {
1245                 .omap4  = {
1246                         .modulemode     = MODULEMODE_SWCTRL,
1247                 },
1248         },
1249 };
1250
1251 struct omap_hwmod am33xx_uart4_hwmod = {
1252         .name           = "uart4",
1253         .class          = &uart_class,
1254         .clkdm_name     = "l4ls_clkdm",
1255         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1256         .main_clk       = "dpll_per_m2_div4_ck",
1257         .prcm           = {
1258                 .omap4  = {
1259                         .modulemode     = MODULEMODE_SWCTRL,
1260                 },
1261         },
1262 };
1263
1264 struct omap_hwmod am33xx_uart5_hwmod = {
1265         .name           = "uart5",
1266         .class          = &uart_class,
1267         .clkdm_name     = "l4ls_clkdm",
1268         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1269         .main_clk       = "dpll_per_m2_div4_ck",
1270         .prcm           = {
1271                 .omap4  = {
1272                         .modulemode     = MODULEMODE_SWCTRL,
1273                 },
1274         },
1275 };
1276
1277 struct omap_hwmod am33xx_uart6_hwmod = {
1278         .name           = "uart6",
1279         .class          = &uart_class,
1280         .clkdm_name     = "l4ls_clkdm",
1281         .flags          = HWMOD_SWSUP_SIDLE_ACT,
1282         .main_clk       = "dpll_per_m2_div4_ck",
1283         .prcm           = {
1284                 .omap4  = {
1285                         .modulemode     = MODULEMODE_SWCTRL,
1286                 },
1287         },
1288 };
1289
1290 /* 'wd_timer' class */
1291 static struct omap_hwmod_class_sysconfig wdt_sysc = {
1292         .rev_offs       = 0x0,
1293         .sysc_offs      = 0x10,
1294         .syss_offs      = 0x14,
1295         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1296                         SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1297         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1298                         SIDLE_SMART_WKUP),
1299         .sysc_fields    = &omap_hwmod_sysc_type1,
1300 };
1301
1302 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
1303         .name           = "wd_timer",
1304         .sysc           = &wdt_sysc,
1305         .pre_shutdown   = &omap2_wd_timer_disable,
1306 };
1307
1308 /*
1309  * XXX: device.c file uses hardcoded name for watchdog timer
1310  * driver "wd_timer2, so we are also using same name as of now...
1311  */
1312 struct omap_hwmod am33xx_wd_timer1_hwmod = {
1313         .name           = "wd_timer2",
1314         .class          = &am33xx_wd_timer_hwmod_class,
1315         .clkdm_name     = "l4_wkup_clkdm",
1316         .flags          = HWMOD_SWSUP_SIDLE,
1317         .main_clk       = "wdt1_fck",
1318         .prcm           = {
1319                 .omap4  = {
1320                         .modulemode     = MODULEMODE_SWCTRL,
1321                 },
1322         },
1323 };
1324
1325 static void omap_hwmod_am33xx_clkctrl(void)
1326 {
1327         CLKCTRL(am33xx_uart2_hwmod, AM33XX_CM_PER_UART1_CLKCTRL_OFFSET);
1328         CLKCTRL(am33xx_uart3_hwmod, AM33XX_CM_PER_UART2_CLKCTRL_OFFSET);
1329         CLKCTRL(am33xx_uart4_hwmod, AM33XX_CM_PER_UART3_CLKCTRL_OFFSET);
1330         CLKCTRL(am33xx_uart5_hwmod, AM33XX_CM_PER_UART4_CLKCTRL_OFFSET);
1331         CLKCTRL(am33xx_uart6_hwmod, AM33XX_CM_PER_UART5_CLKCTRL_OFFSET);
1332         CLKCTRL(am33xx_dcan0_hwmod, AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1333         CLKCTRL(am33xx_dcan1_hwmod, AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1334         CLKCTRL(am33xx_elm_hwmod, AM33XX_CM_PER_ELM_CLKCTRL_OFFSET);
1335         CLKCTRL(am33xx_epwmss0_hwmod, AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1336         CLKCTRL(am33xx_epwmss1_hwmod, AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1337         CLKCTRL(am33xx_epwmss2_hwmod, AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1338         CLKCTRL(am33xx_gpio1_hwmod, AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1339         CLKCTRL(am33xx_gpio2_hwmod, AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1340         CLKCTRL(am33xx_gpio3_hwmod, AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1341         CLKCTRL(am33xx_i2c2_hwmod, AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1342         CLKCTRL(am33xx_i2c3_hwmod, AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1343         CLKCTRL(am33xx_mailbox_hwmod, AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1344         CLKCTRL(am33xx_mcasp0_hwmod, AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1345         CLKCTRL(am33xx_mcasp1_hwmod, AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1346         CLKCTRL(am33xx_mmc0_hwmod, AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1347         CLKCTRL(am33xx_mmc1_hwmod, AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1348         CLKCTRL(am33xx_spi0_hwmod, AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1349         CLKCTRL(am33xx_spi1_hwmod, AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1350         CLKCTRL(am33xx_spinlock_hwmod, AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1351         CLKCTRL(am33xx_timer2_hwmod, AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1352         CLKCTRL(am33xx_timer3_hwmod, AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1353         CLKCTRL(am33xx_timer4_hwmod, AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1354         CLKCTRL(am33xx_timer5_hwmod, AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1355         CLKCTRL(am33xx_timer6_hwmod, AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1356         CLKCTRL(am33xx_timer7_hwmod, AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1357         CLKCTRL(am33xx_smartreflex0_hwmod,
1358                 AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1359         CLKCTRL(am33xx_smartreflex1_hwmod,
1360                 AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1361         CLKCTRL(am33xx_uart1_hwmod, AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1362         CLKCTRL(am33xx_timer1_hwmod, AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1363         CLKCTRL(am33xx_i2c1_hwmod, AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1364         CLKCTRL(am33xx_wd_timer1_hwmod, AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1365         CLKCTRL(am33xx_rtc_hwmod, AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1366         CLKCTRL(am33xx_mmc2_hwmod, AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1367         CLKCTRL(am33xx_gpmc_hwmod, AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1368         CLKCTRL(am33xx_l4_ls_hwmod, AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1369         CLKCTRL(am33xx_l4_wkup_hwmod, AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1370         CLKCTRL(am33xx_l3_main_hwmod, AM33XX_CM_PER_L3_CLKCTRL_OFFSET);
1371         CLKCTRL(am33xx_tpcc_hwmod, AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1372         CLKCTRL(am33xx_tptc0_hwmod, AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1373         CLKCTRL(am33xx_tptc1_hwmod, AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1374         CLKCTRL(am33xx_tptc2_hwmod, AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1375         CLKCTRL(am33xx_gfx_hwmod, AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1376         CLKCTRL(am33xx_cpgmac0_hwmod, AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1377         CLKCTRL(am33xx_pruss_hwmod, AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1378         CLKCTRL(am33xx_mpu_hwmod , AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1379         CLKCTRL(am33xx_l3_instr_hwmod , AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1380         CLKCTRL(am33xx_ocmcram_hwmod , AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1381         CLKCTRL(am33xx_sha0_hwmod , AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1382         CLKCTRL(am33xx_aes0_hwmod , AM33XX_CM_PER_AES0_CLKCTRL_OFFSET);
1383 }
1384
1385 static void omap_hwmod_am33xx_rst(void)
1386 {
1387         RSTCTRL(am33xx_pruss_hwmod, AM33XX_RM_PER_RSTCTRL_OFFSET);
1388         RSTCTRL(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTCTRL_OFFSET);
1389         RSTST(am33xx_gfx_hwmod, AM33XX_RM_GFX_RSTST_OFFSET);
1390 }
1391
1392 void omap_hwmod_am33xx_reg(void)
1393 {
1394         omap_hwmod_am33xx_clkctrl();
1395         omap_hwmod_am33xx_rst();
1396 }
1397
1398 static void omap_hwmod_am43xx_clkctrl(void)
1399 {
1400         CLKCTRL(am33xx_uart2_hwmod, AM43XX_CM_PER_UART1_CLKCTRL_OFFSET);
1401         CLKCTRL(am33xx_uart3_hwmod, AM43XX_CM_PER_UART2_CLKCTRL_OFFSET);
1402         CLKCTRL(am33xx_uart4_hwmod, AM43XX_CM_PER_UART3_CLKCTRL_OFFSET);
1403         CLKCTRL(am33xx_uart5_hwmod, AM43XX_CM_PER_UART4_CLKCTRL_OFFSET);
1404         CLKCTRL(am33xx_uart6_hwmod, AM43XX_CM_PER_UART5_CLKCTRL_OFFSET);
1405         CLKCTRL(am33xx_dcan0_hwmod, AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET);
1406         CLKCTRL(am33xx_dcan1_hwmod, AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET);
1407         CLKCTRL(am33xx_elm_hwmod, AM43XX_CM_PER_ELM_CLKCTRL_OFFSET);
1408         CLKCTRL(am33xx_epwmss0_hwmod, AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET);
1409         CLKCTRL(am33xx_epwmss1_hwmod, AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET);
1410         CLKCTRL(am33xx_epwmss2_hwmod, AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET);
1411         CLKCTRL(am33xx_gpio1_hwmod, AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET);
1412         CLKCTRL(am33xx_gpio2_hwmod, AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET);
1413         CLKCTRL(am33xx_gpio3_hwmod, AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET);
1414         CLKCTRL(am33xx_i2c2_hwmod, AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET);
1415         CLKCTRL(am33xx_i2c3_hwmod, AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET);
1416         CLKCTRL(am33xx_mailbox_hwmod, AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET);
1417         CLKCTRL(am33xx_mcasp0_hwmod, AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET);
1418         CLKCTRL(am33xx_mcasp1_hwmod, AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET);
1419         CLKCTRL(am33xx_mmc0_hwmod, AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET);
1420         CLKCTRL(am33xx_mmc1_hwmod, AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET);
1421         CLKCTRL(am33xx_spi0_hwmod, AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET);
1422         CLKCTRL(am33xx_spi1_hwmod, AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET);
1423         CLKCTRL(am33xx_spinlock_hwmod, AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET);
1424         CLKCTRL(am33xx_timer2_hwmod, AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET);
1425         CLKCTRL(am33xx_timer3_hwmod, AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET);
1426         CLKCTRL(am33xx_timer4_hwmod, AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET);
1427         CLKCTRL(am33xx_timer5_hwmod, AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET);
1428         CLKCTRL(am33xx_timer6_hwmod, AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET);
1429         CLKCTRL(am33xx_timer7_hwmod, AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET);
1430         CLKCTRL(am33xx_smartreflex0_hwmod,
1431                 AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET);
1432         CLKCTRL(am33xx_smartreflex1_hwmod,
1433                 AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET);
1434         CLKCTRL(am33xx_uart1_hwmod, AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET);
1435         CLKCTRL(am33xx_timer1_hwmod, AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET);
1436         CLKCTRL(am33xx_i2c1_hwmod, AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET);
1437         CLKCTRL(am33xx_wd_timer1_hwmod, AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET);
1438         CLKCTRL(am33xx_rtc_hwmod, AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET);
1439         CLKCTRL(am33xx_mmc2_hwmod, AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET);
1440         CLKCTRL(am33xx_gpmc_hwmod, AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET);
1441         CLKCTRL(am33xx_l4_ls_hwmod, AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET);
1442         CLKCTRL(am33xx_l4_wkup_hwmod, AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET);
1443         CLKCTRL(am33xx_l3_main_hwmod, AM43XX_CM_PER_L3_CLKCTRL_OFFSET);
1444         CLKCTRL(am33xx_tpcc_hwmod, AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET);
1445         CLKCTRL(am33xx_tptc0_hwmod, AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET);
1446         CLKCTRL(am33xx_tptc1_hwmod, AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET);
1447         CLKCTRL(am33xx_tptc2_hwmod, AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET);
1448         CLKCTRL(am33xx_gfx_hwmod, AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET);
1449         CLKCTRL(am33xx_cpgmac0_hwmod, AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET);
1450         CLKCTRL(am33xx_pruss_hwmod, AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET);
1451         CLKCTRL(am33xx_mpu_hwmod , AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET);
1452         CLKCTRL(am33xx_l3_instr_hwmod , AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET);
1453         CLKCTRL(am33xx_ocmcram_hwmod , AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET);
1454         CLKCTRL(am33xx_sha0_hwmod , AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET);
1455         CLKCTRL(am33xx_aes0_hwmod , AM43XX_CM_PER_AES0_CLKCTRL_OFFSET);
1456 }
1457
1458 static void omap_hwmod_am43xx_rst(void)
1459 {
1460         RSTCTRL(am33xx_pruss_hwmod, AM43XX_RM_PER_RSTCTRL_OFFSET);
1461         RSTCTRL(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTCTRL_OFFSET);
1462         RSTST(am33xx_gfx_hwmod, AM43XX_RM_GFX_RSTST_OFFSET);
1463 }
1464
1465 void omap_hwmod_am43xx_reg(void)
1466 {
1467         omap_hwmod_am43xx_clkctrl();
1468         omap_hwmod_am43xx_rst();
1469 }