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Merge tag 'stable/for-linus-3.8-rc0-tag' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_33xx_data.c
1 /*
2 * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
3 *
4 * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #include <linux/i2c-omap.h>
18
19 #include "omap_hwmod.h"
20 #include <linux/platform_data/gpio-omap.h>
21 #include <linux/platform_data/spi-omap2-mcspi.h>
22
23 #include "omap_hwmod_common_data.h"
24
25 #include "control.h"
26 #include "cm33xx.h"
27 #include "prm33xx.h"
28 #include "prm-regbits-33xx.h"
29 #include "i2c.h"
30 #include "mmc.h"
31
32 /*
33 * IP blocks
34 */
35
36 /*
37 * 'emif_fw' class
38 * instance(s): emif_fw
39 */
40 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
41 .name = "emif_fw",
42 };
43
44 /* emif_fw */
45 static struct omap_hwmod am33xx_emif_fw_hwmod = {
46 .name = "emif_fw",
47 .class = &am33xx_emif_fw_hwmod_class,
48 .clkdm_name = "l4fw_clkdm",
49 .main_clk = "l4fw_gclk",
50 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
51 .prcm = {
52 .omap4 = {
53 .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
54 .modulemode = MODULEMODE_SWCTRL,
55 },
56 },
57 };
58
59 /*
60 * 'emif' class
61 * instance(s): emif
62 */
63 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
64 .rev_offs = 0x0000,
65 };
66
67 static struct omap_hwmod_class am33xx_emif_hwmod_class = {
68 .name = "emif",
69 .sysc = &am33xx_emif_sysc,
70 };
71
72 static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
73 { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
74 { .irq = -1 },
75 };
76
77 /* emif */
78 static struct omap_hwmod am33xx_emif_hwmod = {
79 .name = "emif",
80 .class = &am33xx_emif_hwmod_class,
81 .clkdm_name = "l3_clkdm",
82 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
83 .mpu_irqs = am33xx_emif_irqs,
84 .main_clk = "dpll_ddr_m2_div2_ck",
85 .prcm = {
86 .omap4 = {
87 .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
88 .modulemode = MODULEMODE_SWCTRL,
89 },
90 },
91 };
92
93 /*
94 * 'l3' class
95 * instance(s): l3_main, l3_s, l3_instr
96 */
97 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
98 .name = "l3",
99 };
100
101 /* l3_main (l3_fast) */
102 static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
103 { .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
104 { .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
105 { .irq = -1 },
106 };
107
108 static struct omap_hwmod am33xx_l3_main_hwmod = {
109 .name = "l3_main",
110 .class = &am33xx_l3_hwmod_class,
111 .clkdm_name = "l3_clkdm",
112 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
113 .mpu_irqs = am33xx_l3_main_irqs,
114 .main_clk = "l3_gclk",
115 .prcm = {
116 .omap4 = {
117 .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
118 .modulemode = MODULEMODE_SWCTRL,
119 },
120 },
121 };
122
123 /* l3_s */
124 static struct omap_hwmod am33xx_l3_s_hwmod = {
125 .name = "l3_s",
126 .class = &am33xx_l3_hwmod_class,
127 .clkdm_name = "l3s_clkdm",
128 };
129
130 /* l3_instr */
131 static struct omap_hwmod am33xx_l3_instr_hwmod = {
132 .name = "l3_instr",
133 .class = &am33xx_l3_hwmod_class,
134 .clkdm_name = "l3_clkdm",
135 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
136 .main_clk = "l3_gclk",
137 .prcm = {
138 .omap4 = {
139 .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
140 .modulemode = MODULEMODE_SWCTRL,
141 },
142 },
143 };
144
145 /*
146 * 'l4' class
147 * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
148 */
149 static struct omap_hwmod_class am33xx_l4_hwmod_class = {
150 .name = "l4",
151 };
152
153 /* l4_ls */
154 static struct omap_hwmod am33xx_l4_ls_hwmod = {
155 .name = "l4_ls",
156 .class = &am33xx_l4_hwmod_class,
157 .clkdm_name = "l4ls_clkdm",
158 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
159 .main_clk = "l4ls_gclk",
160 .prcm = {
161 .omap4 = {
162 .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
163 .modulemode = MODULEMODE_SWCTRL,
164 },
165 },
166 };
167
168 /* l4_hs */
169 static struct omap_hwmod am33xx_l4_hs_hwmod = {
170 .name = "l4_hs",
171 .class = &am33xx_l4_hwmod_class,
172 .clkdm_name = "l4hs_clkdm",
173 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
174 .main_clk = "l4hs_gclk",
175 .prcm = {
176 .omap4 = {
177 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
178 .modulemode = MODULEMODE_SWCTRL,
179 },
180 },
181 };
182
183
184 /* l4_wkup */
185 static struct omap_hwmod am33xx_l4_wkup_hwmod = {
186 .name = "l4_wkup",
187 .class = &am33xx_l4_hwmod_class,
188 .clkdm_name = "l4_wkup_clkdm",
189 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
190 .prcm = {
191 .omap4 = {
192 .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
193 .modulemode = MODULEMODE_SWCTRL,
194 },
195 },
196 };
197
198 /* l4_fw */
199 static struct omap_hwmod am33xx_l4_fw_hwmod = {
200 .name = "l4_fw",
201 .class = &am33xx_l4_hwmod_class,
202 .clkdm_name = "l4fw_clkdm",
203 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
204 .prcm = {
205 .omap4 = {
206 .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
207 .modulemode = MODULEMODE_SWCTRL,
208 },
209 },
210 };
211
212 /*
213 * 'mpu' class
214 */
215 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
216 .name = "mpu",
217 };
218
219 /* mpu */
220 static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
221 { .name = "emuint", .irq = 0 + OMAP_INTC_START, },
222 { .name = "commtx", .irq = 1 + OMAP_INTC_START, },
223 { .name = "commrx", .irq = 2 + OMAP_INTC_START, },
224 { .name = "bench", .irq = 3 + OMAP_INTC_START, },
225 { .irq = -1 },
226 };
227
228 static struct omap_hwmod am33xx_mpu_hwmod = {
229 .name = "mpu",
230 .class = &am33xx_mpu_hwmod_class,
231 .clkdm_name = "mpu_clkdm",
232 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
233 .mpu_irqs = am33xx_mpu_irqs,
234 .main_clk = "dpll_mpu_m2_ck",
235 .prcm = {
236 .omap4 = {
237 .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
238 .modulemode = MODULEMODE_SWCTRL,
239 },
240 },
241 };
242
243 /*
244 * 'wakeup m3' class
245 * Wakeup controller sub-system under wakeup domain
246 */
247 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
248 .name = "wkup_m3",
249 };
250
251 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
252 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
253 };
254
255 static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
256 { .name = "txev", .irq = 78 + OMAP_INTC_START, },
257 { .irq = -1 },
258 };
259
260 /* wkup_m3 */
261 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
262 .name = "wkup_m3",
263 .class = &am33xx_wkup_m3_hwmod_class,
264 .clkdm_name = "l4_wkup_aon_clkdm",
265 .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */
266 .mpu_irqs = am33xx_wkup_m3_irqs,
267 .main_clk = "dpll_core_m4_div2_ck",
268 .prcm = {
269 .omap4 = {
270 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
271 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
272 .modulemode = MODULEMODE_SWCTRL,
273 },
274 },
275 .rst_lines = am33xx_wkup_m3_resets,
276 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
277 };
278
279 /*
280 * 'pru-icss' class
281 * Programmable Real-Time Unit and Industrial Communication Subsystem
282 */
283 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
284 .name = "pruss",
285 };
286
287 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
288 { .name = "pruss", .rst_shift = 1 },
289 };
290
291 static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
292 { .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
293 { .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
294 { .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
295 { .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
296 { .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
297 { .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
298 { .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
299 { .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
300 { .irq = -1 },
301 };
302
303 /* pru-icss */
304 /* Pseudo hwmod for reset control purpose only */
305 static struct omap_hwmod am33xx_pruss_hwmod = {
306 .name = "pruss",
307 .class = &am33xx_pruss_hwmod_class,
308 .clkdm_name = "pruss_ocp_clkdm",
309 .mpu_irqs = am33xx_pruss_irqs,
310 .main_clk = "pruss_ocp_gclk",
311 .prcm = {
312 .omap4 = {
313 .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
314 .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET,
315 .modulemode = MODULEMODE_SWCTRL,
316 },
317 },
318 .rst_lines = am33xx_pruss_resets,
319 .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
320 };
321
322 /* gfx */
323 /* Pseudo hwmod for reset control purpose only */
324 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
325 .name = "gfx",
326 };
327
328 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
329 { .name = "gfx", .rst_shift = 0 },
330 };
331
332 static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
333 { .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
334 { .irq = -1 },
335 };
336
337 static struct omap_hwmod am33xx_gfx_hwmod = {
338 .name = "gfx",
339 .class = &am33xx_gfx_hwmod_class,
340 .clkdm_name = "gfx_l3_clkdm",
341 .mpu_irqs = am33xx_gfx_irqs,
342 .main_clk = "gfx_fck_div_ck",
343 .prcm = {
344 .omap4 = {
345 .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
346 .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
347 .modulemode = MODULEMODE_SWCTRL,
348 },
349 },
350 .rst_lines = am33xx_gfx_resets,
351 .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
352 };
353
354 /*
355 * 'prcm' class
356 * power and reset manager (whole prcm infrastructure)
357 */
358 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
359 .name = "prcm",
360 };
361
362 /* prcm */
363 static struct omap_hwmod am33xx_prcm_hwmod = {
364 .name = "prcm",
365 .class = &am33xx_prcm_hwmod_class,
366 .clkdm_name = "l4_wkup_clkdm",
367 };
368
369 /*
370 * 'adc/tsc' class
371 * TouchScreen Controller (Anolog-To-Digital Converter)
372 */
373 static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
374 .rev_offs = 0x00,
375 .sysc_offs = 0x10,
376 .sysc_flags = SYSC_HAS_SIDLEMODE,
377 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
378 SIDLE_SMART_WKUP),
379 .sysc_fields = &omap_hwmod_sysc_type2,
380 };
381
382 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
383 .name = "adc_tsc",
384 .sysc = &am33xx_adc_tsc_sysc,
385 };
386
387 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
388 { .irq = 16 + OMAP_INTC_START, },
389 { .irq = -1 },
390 };
391
392 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
393 .name = "adc_tsc",
394 .class = &am33xx_adc_tsc_hwmod_class,
395 .clkdm_name = "l4_wkup_clkdm",
396 .mpu_irqs = am33xx_adc_tsc_irqs,
397 .main_clk = "adc_tsc_fck",
398 .prcm = {
399 .omap4 = {
400 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
401 .modulemode = MODULEMODE_SWCTRL,
402 },
403 },
404 };
405
406 /*
407 * Modules omap_hwmod structures
408 *
409 * The following IPs are excluded for the moment because:
410 * - They do not need an explicit SW control using omap_hwmod API.
411 * - They still need to be validated with the driver
412 * properly adapted to omap_hwmod / omap_device
413 *
414 * - cEFUSE (doesn't fall under any ocp_if)
415 * - clkdiv32k
416 * - debugss
417 * - ocmc ram
418 * - ocp watch point
419 * - aes0
420 * - sha0
421 */
422 #if 0
423 /*
424 * 'cefuse' class
425 */
426 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
427 .name = "cefuse",
428 };
429
430 static struct omap_hwmod am33xx_cefuse_hwmod = {
431 .name = "cefuse",
432 .class = &am33xx_cefuse_hwmod_class,
433 .clkdm_name = "l4_cefuse_clkdm",
434 .main_clk = "cefuse_fck",
435 .prcm = {
436 .omap4 = {
437 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
438 .modulemode = MODULEMODE_SWCTRL,
439 },
440 },
441 };
442
443 /*
444 * 'clkdiv32k' class
445 */
446 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
447 .name = "clkdiv32k",
448 };
449
450 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
451 .name = "clkdiv32k",
452 .class = &am33xx_clkdiv32k_hwmod_class,
453 .clkdm_name = "clk_24mhz_clkdm",
454 .main_clk = "clkdiv32k_ick",
455 .prcm = {
456 .omap4 = {
457 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
458 .modulemode = MODULEMODE_SWCTRL,
459 },
460 },
461 };
462
463 /*
464 * 'debugss' class
465 * debug sub system
466 */
467 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
468 .name = "debugss",
469 };
470
471 static struct omap_hwmod am33xx_debugss_hwmod = {
472 .name = "debugss",
473 .class = &am33xx_debugss_hwmod_class,
474 .clkdm_name = "l3_aon_clkdm",
475 .main_clk = "debugss_ick",
476 .prcm = {
477 .omap4 = {
478 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
479 .modulemode = MODULEMODE_SWCTRL,
480 },
481 },
482 };
483
484 /* ocmcram */
485 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
486 .name = "ocmcram",
487 };
488
489 static struct omap_hwmod am33xx_ocmcram_hwmod = {
490 .name = "ocmcram",
491 .class = &am33xx_ocmcram_hwmod_class,
492 .clkdm_name = "l3_clkdm",
493 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
494 .main_clk = "l3_gclk",
495 .prcm = {
496 .omap4 = {
497 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
498 .modulemode = MODULEMODE_SWCTRL,
499 },
500 },
501 };
502
503 /* ocpwp */
504 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
505 .name = "ocpwp",
506 };
507
508 static struct omap_hwmod am33xx_ocpwp_hwmod = {
509 .name = "ocpwp",
510 .class = &am33xx_ocpwp_hwmod_class,
511 .clkdm_name = "l4ls_clkdm",
512 .main_clk = "l4ls_gclk",
513 .prcm = {
514 .omap4 = {
515 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
516 .modulemode = MODULEMODE_SWCTRL,
517 },
518 },
519 };
520
521 /*
522 * 'aes' class
523 */
524 static struct omap_hwmod_class am33xx_aes_hwmod_class = {
525 .name = "aes",
526 };
527
528 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
529 { .irq = 102 + OMAP_INTC_START, },
530 { .irq = -1 },
531 };
532
533 static struct omap_hwmod am33xx_aes0_hwmod = {
534 .name = "aes0",
535 .class = &am33xx_aes_hwmod_class,
536 .clkdm_name = "l3_clkdm",
537 .mpu_irqs = am33xx_aes0_irqs,
538 .main_clk = "l3_gclk",
539 .prcm = {
540 .omap4 = {
541 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
542 .modulemode = MODULEMODE_SWCTRL,
543 },
544 },
545 };
546
547 /* sha0 */
548 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
549 .name = "sha0",
550 };
551
552 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
553 { .irq = 108 + OMAP_INTC_START, },
554 { .irq = -1 },
555 };
556
557 static struct omap_hwmod am33xx_sha0_hwmod = {
558 .name = "sha0",
559 .class = &am33xx_sha0_hwmod_class,
560 .clkdm_name = "l3_clkdm",
561 .mpu_irqs = am33xx_sha0_irqs,
562 .main_clk = "l3_gclk",
563 .prcm = {
564 .omap4 = {
565 .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
566 .modulemode = MODULEMODE_SWCTRL,
567 },
568 },
569 };
570
571 #endif
572
573 /* 'smartreflex' class */
574 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
575 .name = "smartreflex",
576 };
577
578 /* smartreflex0 */
579 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
580 { .irq = 120 + OMAP_INTC_START, },
581 { .irq = -1 },
582 };
583
584 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
585 .name = "smartreflex0",
586 .class = &am33xx_smartreflex_hwmod_class,
587 .clkdm_name = "l4_wkup_clkdm",
588 .mpu_irqs = am33xx_smartreflex0_irqs,
589 .main_clk = "smartreflex0_fck",
590 .prcm = {
591 .omap4 = {
592 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
593 .modulemode = MODULEMODE_SWCTRL,
594 },
595 },
596 };
597
598 /* smartreflex1 */
599 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
600 { .irq = 121 + OMAP_INTC_START, },
601 { .irq = -1 },
602 };
603
604 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
605 .name = "smartreflex1",
606 .class = &am33xx_smartreflex_hwmod_class,
607 .clkdm_name = "l4_wkup_clkdm",
608 .mpu_irqs = am33xx_smartreflex1_irqs,
609 .main_clk = "smartreflex1_fck",
610 .prcm = {
611 .omap4 = {
612 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
613 .modulemode = MODULEMODE_SWCTRL,
614 },
615 },
616 };
617
618 /*
619 * 'control' module class
620 */
621 static struct omap_hwmod_class am33xx_control_hwmod_class = {
622 .name = "control",
623 };
624
625 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
626 { .irq = 8 + OMAP_INTC_START, },
627 { .irq = -1 },
628 };
629
630 static struct omap_hwmod am33xx_control_hwmod = {
631 .name = "control",
632 .class = &am33xx_control_hwmod_class,
633 .clkdm_name = "l4_wkup_clkdm",
634 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
635 .mpu_irqs = am33xx_control_irqs,
636 .main_clk = "dpll_core_m4_div2_ck",
637 .prcm = {
638 .omap4 = {
639 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
640 .modulemode = MODULEMODE_SWCTRL,
641 },
642 },
643 };
644
645 /*
646 * 'cpgmac' class
647 * cpsw/cpgmac sub system
648 */
649 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
650 .rev_offs = 0x0,
651 .sysc_offs = 0x8,
652 .syss_offs = 0x4,
653 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
654 SYSS_HAS_RESET_STATUS),
655 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
656 MSTANDBY_NO),
657 .sysc_fields = &omap_hwmod_sysc_type3,
658 };
659
660 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
661 .name = "cpgmac0",
662 .sysc = &am33xx_cpgmac_sysc,
663 };
664
665 static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
666 { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
667 { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
668 { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
669 { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
670 { .irq = -1 },
671 };
672
673 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
674 .name = "cpgmac0",
675 .class = &am33xx_cpgmac0_hwmod_class,
676 .clkdm_name = "cpsw_125mhz_clkdm",
677 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
678 .mpu_irqs = am33xx_cpgmac0_irqs,
679 .main_clk = "cpsw_125mhz_gclk",
680 .prcm = {
681 .omap4 = {
682 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
683 .modulemode = MODULEMODE_SWCTRL,
684 },
685 },
686 };
687
688 /*
689 * mdio class
690 */
691 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
692 .name = "davinci_mdio",
693 };
694
695 static struct omap_hwmod am33xx_mdio_hwmod = {
696 .name = "davinci_mdio",
697 .class = &am33xx_mdio_hwmod_class,
698 .clkdm_name = "cpsw_125mhz_clkdm",
699 .main_clk = "cpsw_125mhz_gclk",
700 };
701
702 /*
703 * dcan class
704 */
705 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
706 .name = "d_can",
707 };
708
709 /* dcan0 */
710 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
711 { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
712 { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
713 { .irq = -1 },
714 };
715
716 static struct omap_hwmod am33xx_dcan0_hwmod = {
717 .name = "d_can0",
718 .class = &am33xx_dcan_hwmod_class,
719 .clkdm_name = "l4ls_clkdm",
720 .mpu_irqs = am33xx_dcan0_irqs,
721 .main_clk = "dcan0_fck",
722 .prcm = {
723 .omap4 = {
724 .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
725 .modulemode = MODULEMODE_SWCTRL,
726 },
727 },
728 };
729
730 /* dcan1 */
731 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
732 { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
733 { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
734 { .irq = -1 },
735 };
736 static struct omap_hwmod am33xx_dcan1_hwmod = {
737 .name = "d_can1",
738 .class = &am33xx_dcan_hwmod_class,
739 .clkdm_name = "l4ls_clkdm",
740 .mpu_irqs = am33xx_dcan1_irqs,
741 .main_clk = "dcan1_fck",
742 .prcm = {
743 .omap4 = {
744 .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
745 .modulemode = MODULEMODE_SWCTRL,
746 },
747 },
748 };
749
750 /* elm */
751 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
752 .rev_offs = 0x0000,
753 .sysc_offs = 0x0010,
754 .syss_offs = 0x0014,
755 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
756 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
757 SYSS_HAS_RESET_STATUS),
758 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
759 .sysc_fields = &omap_hwmod_sysc_type1,
760 };
761
762 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
763 .name = "elm",
764 .sysc = &am33xx_elm_sysc,
765 };
766
767 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
768 { .irq = 4 + OMAP_INTC_START, },
769 { .irq = -1 },
770 };
771
772 static struct omap_hwmod am33xx_elm_hwmod = {
773 .name = "elm",
774 .class = &am33xx_elm_hwmod_class,
775 .clkdm_name = "l4ls_clkdm",
776 .mpu_irqs = am33xx_elm_irqs,
777 .main_clk = "l4ls_gclk",
778 .prcm = {
779 .omap4 = {
780 .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
781 .modulemode = MODULEMODE_SWCTRL,
782 },
783 },
784 };
785
786 /*
787 * 'epwmss' class: ecap0,1,2, ehrpwm0,1,2
788 */
789 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
790 .rev_offs = 0x0,
791 .sysc_offs = 0x4,
792 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
793 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
794 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
795 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
796 .sysc_fields = &omap_hwmod_sysc_type2,
797 };
798
799 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
800 .name = "epwmss",
801 .sysc = &am33xx_epwmss_sysc,
802 };
803
804 /* ehrpwm0 */
805 static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
806 { .name = "int", .irq = 86 + OMAP_INTC_START, },
807 { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
808 { .irq = -1 },
809 };
810
811 static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
812 .name = "ehrpwm0",
813 .class = &am33xx_epwmss_hwmod_class,
814 .clkdm_name = "l4ls_clkdm",
815 .mpu_irqs = am33xx_ehrpwm0_irqs,
816 .main_clk = "l4ls_gclk",
817 .prcm = {
818 .omap4 = {
819 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
820 .modulemode = MODULEMODE_SWCTRL,
821 },
822 },
823 };
824
825 /* ehrpwm1 */
826 static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
827 { .name = "int", .irq = 87 + OMAP_INTC_START, },
828 { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
829 { .irq = -1 },
830 };
831
832 static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
833 .name = "ehrpwm1",
834 .class = &am33xx_epwmss_hwmod_class,
835 .clkdm_name = "l4ls_clkdm",
836 .mpu_irqs = am33xx_ehrpwm1_irqs,
837 .main_clk = "l4ls_gclk",
838 .prcm = {
839 .omap4 = {
840 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
841 .modulemode = MODULEMODE_SWCTRL,
842 },
843 },
844 };
845
846 /* ehrpwm2 */
847 static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
848 { .name = "int", .irq = 39 + OMAP_INTC_START, },
849 { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
850 { .irq = -1 },
851 };
852
853 static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
854 .name = "ehrpwm2",
855 .class = &am33xx_epwmss_hwmod_class,
856 .clkdm_name = "l4ls_clkdm",
857 .mpu_irqs = am33xx_ehrpwm2_irqs,
858 .main_clk = "l4ls_gclk",
859 .prcm = {
860 .omap4 = {
861 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
862 .modulemode = MODULEMODE_SWCTRL,
863 },
864 },
865 };
866
867 /* ecap0 */
868 static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
869 { .irq = 31 + OMAP_INTC_START, },
870 { .irq = -1 },
871 };
872
873 static struct omap_hwmod am33xx_ecap0_hwmod = {
874 .name = "ecap0",
875 .class = &am33xx_epwmss_hwmod_class,
876 .clkdm_name = "l4ls_clkdm",
877 .mpu_irqs = am33xx_ecap0_irqs,
878 .main_clk = "l4ls_gclk",
879 .prcm = {
880 .omap4 = {
881 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
882 .modulemode = MODULEMODE_SWCTRL,
883 },
884 },
885 };
886
887 /* ecap1 */
888 static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
889 { .irq = 47 + OMAP_INTC_START, },
890 { .irq = -1 },
891 };
892
893 static struct omap_hwmod am33xx_ecap1_hwmod = {
894 .name = "ecap1",
895 .class = &am33xx_epwmss_hwmod_class,
896 .clkdm_name = "l4ls_clkdm",
897 .mpu_irqs = am33xx_ecap1_irqs,
898 .main_clk = "l4ls_gclk",
899 .prcm = {
900 .omap4 = {
901 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
902 .modulemode = MODULEMODE_SWCTRL,
903 },
904 },
905 };
906
907 /* ecap2 */
908 static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
909 { .irq = 61 + OMAP_INTC_START, },
910 { .irq = -1 },
911 };
912
913 static struct omap_hwmod am33xx_ecap2_hwmod = {
914 .name = "ecap2",
915 .mpu_irqs = am33xx_ecap2_irqs,
916 .class = &am33xx_epwmss_hwmod_class,
917 .clkdm_name = "l4ls_clkdm",
918 .main_clk = "l4ls_gclk",
919 .prcm = {
920 .omap4 = {
921 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
922 .modulemode = MODULEMODE_SWCTRL,
923 },
924 },
925 };
926
927 /*
928 * 'gpio' class: for gpio 0,1,2,3
929 */
930 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
931 .rev_offs = 0x0000,
932 .sysc_offs = 0x0010,
933 .syss_offs = 0x0114,
934 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
935 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
936 SYSS_HAS_RESET_STATUS),
937 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
938 SIDLE_SMART_WKUP),
939 .sysc_fields = &omap_hwmod_sysc_type1,
940 };
941
942 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
943 .name = "gpio",
944 .sysc = &am33xx_gpio_sysc,
945 .rev = 2,
946 };
947
948 static struct omap_gpio_dev_attr gpio_dev_attr = {
949 .bank_width = 32,
950 .dbck_flag = true,
951 };
952
953 /* gpio0 */
954 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
955 { .role = "dbclk", .clk = "gpio0_dbclk" },
956 };
957
958 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
959 { .irq = 96 + OMAP_INTC_START, },
960 { .irq = -1 },
961 };
962
963 static struct omap_hwmod am33xx_gpio0_hwmod = {
964 .name = "gpio1",
965 .class = &am33xx_gpio_hwmod_class,
966 .clkdm_name = "l4_wkup_clkdm",
967 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
968 .mpu_irqs = am33xx_gpio0_irqs,
969 .main_clk = "dpll_core_m4_div2_ck",
970 .prcm = {
971 .omap4 = {
972 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
973 .modulemode = MODULEMODE_SWCTRL,
974 },
975 },
976 .opt_clks = gpio0_opt_clks,
977 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
978 .dev_attr = &gpio_dev_attr,
979 };
980
981 /* gpio1 */
982 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
983 { .irq = 98 + OMAP_INTC_START, },
984 { .irq = -1 },
985 };
986
987 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
988 { .role = "dbclk", .clk = "gpio1_dbclk" },
989 };
990
991 static struct omap_hwmod am33xx_gpio1_hwmod = {
992 .name = "gpio2",
993 .class = &am33xx_gpio_hwmod_class,
994 .clkdm_name = "l4ls_clkdm",
995 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
996 .mpu_irqs = am33xx_gpio1_irqs,
997 .main_clk = "l4ls_gclk",
998 .prcm = {
999 .omap4 = {
1000 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
1001 .modulemode = MODULEMODE_SWCTRL,
1002 },
1003 },
1004 .opt_clks = gpio1_opt_clks,
1005 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1006 .dev_attr = &gpio_dev_attr,
1007 };
1008
1009 /* gpio2 */
1010 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
1011 { .irq = 32 + OMAP_INTC_START, },
1012 { .irq = -1 },
1013 };
1014
1015 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1016 { .role = "dbclk", .clk = "gpio2_dbclk" },
1017 };
1018
1019 static struct omap_hwmod am33xx_gpio2_hwmod = {
1020 .name = "gpio3",
1021 .class = &am33xx_gpio_hwmod_class,
1022 .clkdm_name = "l4ls_clkdm",
1023 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1024 .mpu_irqs = am33xx_gpio2_irqs,
1025 .main_clk = "l4ls_gclk",
1026 .prcm = {
1027 .omap4 = {
1028 .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
1029 .modulemode = MODULEMODE_SWCTRL,
1030 },
1031 },
1032 .opt_clks = gpio2_opt_clks,
1033 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1034 .dev_attr = &gpio_dev_attr,
1035 };
1036
1037 /* gpio3 */
1038 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
1039 { .irq = 62 + OMAP_INTC_START, },
1040 { .irq = -1 },
1041 };
1042
1043 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1044 { .role = "dbclk", .clk = "gpio3_dbclk" },
1045 };
1046
1047 static struct omap_hwmod am33xx_gpio3_hwmod = {
1048 .name = "gpio4",
1049 .class = &am33xx_gpio_hwmod_class,
1050 .clkdm_name = "l4ls_clkdm",
1051 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1052 .mpu_irqs = am33xx_gpio3_irqs,
1053 .main_clk = "l4ls_gclk",
1054 .prcm = {
1055 .omap4 = {
1056 .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
1057 .modulemode = MODULEMODE_SWCTRL,
1058 },
1059 },
1060 .opt_clks = gpio3_opt_clks,
1061 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1062 .dev_attr = &gpio_dev_attr,
1063 };
1064
1065 /* gpmc */
1066 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
1067 .rev_offs = 0x0,
1068 .sysc_offs = 0x10,
1069 .syss_offs = 0x14,
1070 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1071 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1072 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1073 .sysc_fields = &omap_hwmod_sysc_type1,
1074 };
1075
1076 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
1077 .name = "gpmc",
1078 .sysc = &gpmc_sysc,
1079 };
1080
1081 static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
1082 { .irq = 100 + OMAP_INTC_START, },
1083 { .irq = -1 },
1084 };
1085
1086 static struct omap_hwmod am33xx_gpmc_hwmod = {
1087 .name = "gpmc",
1088 .class = &am33xx_gpmc_hwmod_class,
1089 .clkdm_name = "l3s_clkdm",
1090 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1091 .mpu_irqs = am33xx_gpmc_irqs,
1092 .main_clk = "l3s_gclk",
1093 .prcm = {
1094 .omap4 = {
1095 .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
1096 .modulemode = MODULEMODE_SWCTRL,
1097 },
1098 },
1099 };
1100
1101 /* 'i2c' class */
1102 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
1103 .sysc_offs = 0x0010,
1104 .syss_offs = 0x0090,
1105 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1106 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1107 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1108 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1109 SIDLE_SMART_WKUP),
1110 .sysc_fields = &omap_hwmod_sysc_type1,
1111 };
1112
1113 static struct omap_hwmod_class i2c_class = {
1114 .name = "i2c",
1115 .sysc = &am33xx_i2c_sysc,
1116 .rev = OMAP_I2C_IP_VERSION_2,
1117 .reset = &omap_i2c_reset,
1118 };
1119
1120 static struct omap_i2c_dev_attr i2c_dev_attr = {
1121 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE |
1122 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE,
1123 };
1124
1125 /* i2c1 */
1126 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1127 { .irq = 70 + OMAP_INTC_START, },
1128 { .irq = -1 },
1129 };
1130
1131 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
1132 { .name = "tx", .dma_req = 0, },
1133 { .name = "rx", .dma_req = 0, },
1134 { .dma_req = -1 }
1135 };
1136
1137 static struct omap_hwmod am33xx_i2c1_hwmod = {
1138 .name = "i2c1",
1139 .class = &i2c_class,
1140 .clkdm_name = "l4_wkup_clkdm",
1141 .mpu_irqs = i2c1_mpu_irqs,
1142 .sdma_reqs = i2c1_edma_reqs,
1143 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1144 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1145 .prcm = {
1146 .omap4 = {
1147 .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
1148 .modulemode = MODULEMODE_SWCTRL,
1149 },
1150 },
1151 .dev_attr = &i2c_dev_attr,
1152 };
1153
1154 /* i2c1 */
1155 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1156 { .irq = 71 + OMAP_INTC_START, },
1157 { .irq = -1 },
1158 };
1159
1160 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
1161 { .name = "tx", .dma_req = 0, },
1162 { .name = "rx", .dma_req = 0, },
1163 { .dma_req = -1 }
1164 };
1165
1166 static struct omap_hwmod am33xx_i2c2_hwmod = {
1167 .name = "i2c2",
1168 .class = &i2c_class,
1169 .clkdm_name = "l4ls_clkdm",
1170 .mpu_irqs = i2c2_mpu_irqs,
1171 .sdma_reqs = i2c2_edma_reqs,
1172 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1173 .main_clk = "dpll_per_m2_div4_ck",
1174 .prcm = {
1175 .omap4 = {
1176 .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
1177 .modulemode = MODULEMODE_SWCTRL,
1178 },
1179 },
1180 .dev_attr = &i2c_dev_attr,
1181 };
1182
1183 /* i2c3 */
1184 static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
1185 { .name = "tx", .dma_req = 0, },
1186 { .name = "rx", .dma_req = 0, },
1187 { .dma_req = -1 }
1188 };
1189
1190 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1191 { .irq = 30 + OMAP_INTC_START, },
1192 { .irq = -1 },
1193 };
1194
1195 static struct omap_hwmod am33xx_i2c3_hwmod = {
1196 .name = "i2c3",
1197 .class = &i2c_class,
1198 .clkdm_name = "l4ls_clkdm",
1199 .mpu_irqs = i2c3_mpu_irqs,
1200 .sdma_reqs = i2c3_edma_reqs,
1201 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1202 .main_clk = "dpll_per_m2_div4_ck",
1203 .prcm = {
1204 .omap4 = {
1205 .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
1206 .modulemode = MODULEMODE_SWCTRL,
1207 },
1208 },
1209 .dev_attr = &i2c_dev_attr,
1210 };
1211
1212
1213 /* lcdc */
1214 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
1215 .rev_offs = 0x0,
1216 .sysc_offs = 0x54,
1217 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
1218 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1219 .sysc_fields = &omap_hwmod_sysc_type2,
1220 };
1221
1222 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1223 .name = "lcdc",
1224 .sysc = &lcdc_sysc,
1225 };
1226
1227 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1228 { .irq = 36 + OMAP_INTC_START, },
1229 { .irq = -1 },
1230 };
1231
1232 static struct omap_hwmod am33xx_lcdc_hwmod = {
1233 .name = "lcdc",
1234 .class = &am33xx_lcdc_hwmod_class,
1235 .clkdm_name = "lcdc_clkdm",
1236 .mpu_irqs = am33xx_lcdc_irqs,
1237 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1238 .main_clk = "lcd_gclk",
1239 .prcm = {
1240 .omap4 = {
1241 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1242 .modulemode = MODULEMODE_SWCTRL,
1243 },
1244 },
1245 };
1246
1247 /*
1248 * 'mailbox' class
1249 * mailbox module allowing communication between the on-chip processors using a
1250 * queued mailbox-interrupt mechanism.
1251 */
1252 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1253 .rev_offs = 0x0000,
1254 .sysc_offs = 0x0010,
1255 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1256 SYSC_HAS_SOFTRESET),
1257 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1258 .sysc_fields = &omap_hwmod_sysc_type2,
1259 };
1260
1261 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1262 .name = "mailbox",
1263 .sysc = &am33xx_mailbox_sysc,
1264 };
1265
1266 static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1267 { .irq = 77 + OMAP_INTC_START, },
1268 { .irq = -1 },
1269 };
1270
1271 static struct omap_hwmod am33xx_mailbox_hwmod = {
1272 .name = "mailbox",
1273 .class = &am33xx_mailbox_hwmod_class,
1274 .clkdm_name = "l4ls_clkdm",
1275 .mpu_irqs = am33xx_mailbox_irqs,
1276 .main_clk = "l4ls_gclk",
1277 .prcm = {
1278 .omap4 = {
1279 .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1280 .modulemode = MODULEMODE_SWCTRL,
1281 },
1282 },
1283 };
1284
1285 /*
1286 * 'mcasp' class
1287 */
1288 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
1289 .rev_offs = 0x0,
1290 .sysc_offs = 0x4,
1291 .sysc_flags = SYSC_HAS_SIDLEMODE,
1292 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1293 .sysc_fields = &omap_hwmod_sysc_type3,
1294 };
1295
1296 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1297 .name = "mcasp",
1298 .sysc = &am33xx_mcasp_sysc,
1299 };
1300
1301 /* mcasp0 */
1302 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1303 { .name = "ax", .irq = 80 + OMAP_INTC_START, },
1304 { .name = "ar", .irq = 81 + OMAP_INTC_START, },
1305 { .irq = -1 },
1306 };
1307
1308 static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
1309 { .name = "tx", .dma_req = 8, },
1310 { .name = "rx", .dma_req = 9, },
1311 { .dma_req = -1 }
1312 };
1313
1314 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1315 .name = "mcasp0",
1316 .class = &am33xx_mcasp_hwmod_class,
1317 .clkdm_name = "l3s_clkdm",
1318 .mpu_irqs = am33xx_mcasp0_irqs,
1319 .sdma_reqs = am33xx_mcasp0_edma_reqs,
1320 .main_clk = "mcasp0_fck",
1321 .prcm = {
1322 .omap4 = {
1323 .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1324 .modulemode = MODULEMODE_SWCTRL,
1325 },
1326 },
1327 };
1328
1329 /* mcasp1 */
1330 static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
1331 { .name = "ax", .irq = 82 + OMAP_INTC_START, },
1332 { .name = "ar", .irq = 83 + OMAP_INTC_START, },
1333 { .irq = -1 },
1334 };
1335
1336 static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
1337 { .name = "tx", .dma_req = 10, },
1338 { .name = "rx", .dma_req = 11, },
1339 { .dma_req = -1 }
1340 };
1341
1342 static struct omap_hwmod am33xx_mcasp1_hwmod = {
1343 .name = "mcasp1",
1344 .class = &am33xx_mcasp_hwmod_class,
1345 .clkdm_name = "l3s_clkdm",
1346 .mpu_irqs = am33xx_mcasp1_irqs,
1347 .sdma_reqs = am33xx_mcasp1_edma_reqs,
1348 .main_clk = "mcasp1_fck",
1349 .prcm = {
1350 .omap4 = {
1351 .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
1352 .modulemode = MODULEMODE_SWCTRL,
1353 },
1354 },
1355 };
1356
1357 /* 'mmc' class */
1358 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1359 .rev_offs = 0x1fc,
1360 .sysc_offs = 0x10,
1361 .syss_offs = 0x14,
1362 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1363 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1364 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1365 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1366 .sysc_fields = &omap_hwmod_sysc_type1,
1367 };
1368
1369 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1370 .name = "mmc",
1371 .sysc = &am33xx_mmc_sysc,
1372 };
1373
1374 /* mmc0 */
1375 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1376 { .irq = 64 + OMAP_INTC_START, },
1377 { .irq = -1 },
1378 };
1379
1380 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1381 { .name = "tx", .dma_req = 24, },
1382 { .name = "rx", .dma_req = 25, },
1383 { .dma_req = -1 }
1384 };
1385
1386 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1387 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1388 };
1389
1390 static struct omap_hwmod am33xx_mmc0_hwmod = {
1391 .name = "mmc1",
1392 .class = &am33xx_mmc_hwmod_class,
1393 .clkdm_name = "l4ls_clkdm",
1394 .mpu_irqs = am33xx_mmc0_irqs,
1395 .sdma_reqs = am33xx_mmc0_edma_reqs,
1396 .main_clk = "mmc_clk",
1397 .prcm = {
1398 .omap4 = {
1399 .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1400 .modulemode = MODULEMODE_SWCTRL,
1401 },
1402 },
1403 .dev_attr = &am33xx_mmc0_dev_attr,
1404 };
1405
1406 /* mmc1 */
1407 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1408 { .irq = 28 + OMAP_INTC_START, },
1409 { .irq = -1 },
1410 };
1411
1412 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1413 { .name = "tx", .dma_req = 2, },
1414 { .name = "rx", .dma_req = 3, },
1415 { .dma_req = -1 }
1416 };
1417
1418 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1419 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1420 };
1421
1422 static struct omap_hwmod am33xx_mmc1_hwmod = {
1423 .name = "mmc2",
1424 .class = &am33xx_mmc_hwmod_class,
1425 .clkdm_name = "l4ls_clkdm",
1426 .mpu_irqs = am33xx_mmc1_irqs,
1427 .sdma_reqs = am33xx_mmc1_edma_reqs,
1428 .main_clk = "mmc_clk",
1429 .prcm = {
1430 .omap4 = {
1431 .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1432 .modulemode = MODULEMODE_SWCTRL,
1433 },
1434 },
1435 .dev_attr = &am33xx_mmc1_dev_attr,
1436 };
1437
1438 /* mmc2 */
1439 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1440 { .irq = 29 + OMAP_INTC_START, },
1441 { .irq = -1 },
1442 };
1443
1444 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1445 { .name = "tx", .dma_req = 64, },
1446 { .name = "rx", .dma_req = 65, },
1447 { .dma_req = -1 }
1448 };
1449
1450 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1451 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1452 };
1453 static struct omap_hwmod am33xx_mmc2_hwmod = {
1454 .name = "mmc3",
1455 .class = &am33xx_mmc_hwmod_class,
1456 .clkdm_name = "l3s_clkdm",
1457 .mpu_irqs = am33xx_mmc2_irqs,
1458 .sdma_reqs = am33xx_mmc2_edma_reqs,
1459 .main_clk = "mmc_clk",
1460 .prcm = {
1461 .omap4 = {
1462 .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1463 .modulemode = MODULEMODE_SWCTRL,
1464 },
1465 },
1466 .dev_attr = &am33xx_mmc2_dev_attr,
1467 };
1468
1469 /*
1470 * 'rtc' class
1471 * rtc subsystem
1472 */
1473 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
1474 .rev_offs = 0x0074,
1475 .sysc_offs = 0x0078,
1476 .sysc_flags = SYSC_HAS_SIDLEMODE,
1477 .idlemodes = (SIDLE_FORCE | SIDLE_NO |
1478 SIDLE_SMART | SIDLE_SMART_WKUP),
1479 .sysc_fields = &omap_hwmod_sysc_type3,
1480 };
1481
1482 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1483 .name = "rtc",
1484 .sysc = &am33xx_rtc_sysc,
1485 };
1486
1487 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1488 { .name = "rtcint", .irq = 75 + OMAP_INTC_START, },
1489 { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, },
1490 { .irq = -1 },
1491 };
1492
1493 static struct omap_hwmod am33xx_rtc_hwmod = {
1494 .name = "rtc",
1495 .class = &am33xx_rtc_hwmod_class,
1496 .clkdm_name = "l4_rtc_clkdm",
1497 .mpu_irqs = am33xx_rtc_irqs,
1498 .main_clk = "clk_32768_ck",
1499 .prcm = {
1500 .omap4 = {
1501 .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1502 .modulemode = MODULEMODE_SWCTRL,
1503 },
1504 },
1505 };
1506
1507 /* 'spi' class */
1508 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1509 .rev_offs = 0x0000,
1510 .sysc_offs = 0x0110,
1511 .syss_offs = 0x0114,
1512 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1513 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1514 SYSS_HAS_RESET_STATUS),
1515 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1516 .sysc_fields = &omap_hwmod_sysc_type1,
1517 };
1518
1519 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1520 .name = "mcspi",
1521 .sysc = &am33xx_mcspi_sysc,
1522 .rev = OMAP4_MCSPI_REV,
1523 };
1524
1525 /* spi0 */
1526 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1527 { .irq = 65 + OMAP_INTC_START, },
1528 { .irq = -1 },
1529 };
1530
1531 static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
1532 { .name = "rx0", .dma_req = 17 },
1533 { .name = "tx0", .dma_req = 16 },
1534 { .name = "rx1", .dma_req = 19 },
1535 { .name = "tx1", .dma_req = 18 },
1536 { .dma_req = -1 }
1537 };
1538
1539 static struct omap2_mcspi_dev_attr mcspi_attrib = {
1540 .num_chipselect = 2,
1541 };
1542 static struct omap_hwmod am33xx_spi0_hwmod = {
1543 .name = "spi0",
1544 .class = &am33xx_spi_hwmod_class,
1545 .clkdm_name = "l4ls_clkdm",
1546 .mpu_irqs = am33xx_spi0_irqs,
1547 .sdma_reqs = am33xx_mcspi0_edma_reqs,
1548 .main_clk = "dpll_per_m2_div4_ck",
1549 .prcm = {
1550 .omap4 = {
1551 .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1552 .modulemode = MODULEMODE_SWCTRL,
1553 },
1554 },
1555 .dev_attr = &mcspi_attrib,
1556 };
1557
1558 /* spi1 */
1559 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1560 { .irq = 125 + OMAP_INTC_START, },
1561 { .irq = -1 },
1562 };
1563
1564 static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
1565 { .name = "rx0", .dma_req = 43 },
1566 { .name = "tx0", .dma_req = 42 },
1567 { .name = "rx1", .dma_req = 45 },
1568 { .name = "tx1", .dma_req = 44 },
1569 { .dma_req = -1 }
1570 };
1571
1572 static struct omap_hwmod am33xx_spi1_hwmod = {
1573 .name = "spi1",
1574 .class = &am33xx_spi_hwmod_class,
1575 .clkdm_name = "l4ls_clkdm",
1576 .mpu_irqs = am33xx_spi1_irqs,
1577 .sdma_reqs = am33xx_mcspi1_edma_reqs,
1578 .main_clk = "dpll_per_m2_div4_ck",
1579 .prcm = {
1580 .omap4 = {
1581 .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1582 .modulemode = MODULEMODE_SWCTRL,
1583 },
1584 },
1585 .dev_attr = &mcspi_attrib,
1586 };
1587
1588 /*
1589 * 'spinlock' class
1590 * spinlock provides hardware assistance for synchronizing the
1591 * processes running on multiple processors
1592 */
1593 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1594 .name = "spinlock",
1595 };
1596
1597 static struct omap_hwmod am33xx_spinlock_hwmod = {
1598 .name = "spinlock",
1599 .class = &am33xx_spinlock_hwmod_class,
1600 .clkdm_name = "l4ls_clkdm",
1601 .main_clk = "l4ls_gclk",
1602 .prcm = {
1603 .omap4 = {
1604 .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1605 .modulemode = MODULEMODE_SWCTRL,
1606 },
1607 },
1608 };
1609
1610 /* 'timer 2-7' class */
1611 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1612 .rev_offs = 0x0000,
1613 .sysc_offs = 0x0010,
1614 .syss_offs = 0x0014,
1615 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1616 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1617 SIDLE_SMART_WKUP),
1618 .sysc_fields = &omap_hwmod_sysc_type2,
1619 };
1620
1621 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1622 .name = "timer",
1623 .sysc = &am33xx_timer_sysc,
1624 };
1625
1626 /* timer1 1ms */
1627 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1628 .rev_offs = 0x0000,
1629 .sysc_offs = 0x0010,
1630 .syss_offs = 0x0014,
1631 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1632 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1633 SYSS_HAS_RESET_STATUS),
1634 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1635 .sysc_fields = &omap_hwmod_sysc_type1,
1636 };
1637
1638 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1639 .name = "timer",
1640 .sysc = &am33xx_timer1ms_sysc,
1641 };
1642
1643 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
1644 { .irq = 67 + OMAP_INTC_START, },
1645 { .irq = -1 },
1646 };
1647
1648 static struct omap_hwmod am33xx_timer1_hwmod = {
1649 .name = "timer1",
1650 .class = &am33xx_timer1ms_hwmod_class,
1651 .clkdm_name = "l4_wkup_clkdm",
1652 .mpu_irqs = am33xx_timer1_irqs,
1653 .main_clk = "timer1_fck",
1654 .prcm = {
1655 .omap4 = {
1656 .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1657 .modulemode = MODULEMODE_SWCTRL,
1658 },
1659 },
1660 };
1661
1662 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
1663 { .irq = 68 + OMAP_INTC_START, },
1664 { .irq = -1 },
1665 };
1666
1667 static struct omap_hwmod am33xx_timer2_hwmod = {
1668 .name = "timer2",
1669 .class = &am33xx_timer_hwmod_class,
1670 .clkdm_name = "l4ls_clkdm",
1671 .mpu_irqs = am33xx_timer2_irqs,
1672 .main_clk = "timer2_fck",
1673 .prcm = {
1674 .omap4 = {
1675 .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1676 .modulemode = MODULEMODE_SWCTRL,
1677 },
1678 },
1679 };
1680
1681 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
1682 { .irq = 69 + OMAP_INTC_START, },
1683 { .irq = -1 },
1684 };
1685
1686 static struct omap_hwmod am33xx_timer3_hwmod = {
1687 .name = "timer3",
1688 .class = &am33xx_timer_hwmod_class,
1689 .clkdm_name = "l4ls_clkdm",
1690 .mpu_irqs = am33xx_timer3_irqs,
1691 .main_clk = "timer3_fck",
1692 .prcm = {
1693 .omap4 = {
1694 .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
1695 .modulemode = MODULEMODE_SWCTRL,
1696 },
1697 },
1698 };
1699
1700 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
1701 { .irq = 92 + OMAP_INTC_START, },
1702 { .irq = -1 },
1703 };
1704
1705 static struct omap_hwmod am33xx_timer4_hwmod = {
1706 .name = "timer4",
1707 .class = &am33xx_timer_hwmod_class,
1708 .clkdm_name = "l4ls_clkdm",
1709 .mpu_irqs = am33xx_timer4_irqs,
1710 .main_clk = "timer4_fck",
1711 .prcm = {
1712 .omap4 = {
1713 .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
1714 .modulemode = MODULEMODE_SWCTRL,
1715 },
1716 },
1717 };
1718
1719 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
1720 { .irq = 93 + OMAP_INTC_START, },
1721 { .irq = -1 },
1722 };
1723
1724 static struct omap_hwmod am33xx_timer5_hwmod = {
1725 .name = "timer5",
1726 .class = &am33xx_timer_hwmod_class,
1727 .clkdm_name = "l4ls_clkdm",
1728 .mpu_irqs = am33xx_timer5_irqs,
1729 .main_clk = "timer5_fck",
1730 .prcm = {
1731 .omap4 = {
1732 .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
1733 .modulemode = MODULEMODE_SWCTRL,
1734 },
1735 },
1736 };
1737
1738 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
1739 { .irq = 94 + OMAP_INTC_START, },
1740 { .irq = -1 },
1741 };
1742
1743 static struct omap_hwmod am33xx_timer6_hwmod = {
1744 .name = "timer6",
1745 .class = &am33xx_timer_hwmod_class,
1746 .clkdm_name = "l4ls_clkdm",
1747 .mpu_irqs = am33xx_timer6_irqs,
1748 .main_clk = "timer6_fck",
1749 .prcm = {
1750 .omap4 = {
1751 .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
1752 .modulemode = MODULEMODE_SWCTRL,
1753 },
1754 },
1755 };
1756
1757 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
1758 { .irq = 95 + OMAP_INTC_START, },
1759 { .irq = -1 },
1760 };
1761
1762 static struct omap_hwmod am33xx_timer7_hwmod = {
1763 .name = "timer7",
1764 .class = &am33xx_timer_hwmod_class,
1765 .clkdm_name = "l4ls_clkdm",
1766 .mpu_irqs = am33xx_timer7_irqs,
1767 .main_clk = "timer7_fck",
1768 .prcm = {
1769 .omap4 = {
1770 .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
1771 .modulemode = MODULEMODE_SWCTRL,
1772 },
1773 },
1774 };
1775
1776 /* tpcc */
1777 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1778 .name = "tpcc",
1779 };
1780
1781 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
1782 { .name = "edma0", .irq = 12 + OMAP_INTC_START, },
1783 { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, },
1784 { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, },
1785 { .irq = -1 },
1786 };
1787
1788 static struct omap_hwmod am33xx_tpcc_hwmod = {
1789 .name = "tpcc",
1790 .class = &am33xx_tpcc_hwmod_class,
1791 .clkdm_name = "l3_clkdm",
1792 .mpu_irqs = am33xx_tpcc_irqs,
1793 .main_clk = "l3_gclk",
1794 .prcm = {
1795 .omap4 = {
1796 .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
1797 .modulemode = MODULEMODE_SWCTRL,
1798 },
1799 },
1800 };
1801
1802 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1803 .rev_offs = 0x0,
1804 .sysc_offs = 0x10,
1805 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1806 SYSC_HAS_MIDLEMODE),
1807 .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1808 .sysc_fields = &omap_hwmod_sysc_type2,
1809 };
1810
1811 /* 'tptc' class */
1812 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1813 .name = "tptc",
1814 .sysc = &am33xx_tptc_sysc,
1815 };
1816
1817 /* tptc0 */
1818 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
1819 { .irq = 112 + OMAP_INTC_START, },
1820 { .irq = -1 },
1821 };
1822
1823 static struct omap_hwmod am33xx_tptc0_hwmod = {
1824 .name = "tptc0",
1825 .class = &am33xx_tptc_hwmod_class,
1826 .clkdm_name = "l3_clkdm",
1827 .mpu_irqs = am33xx_tptc0_irqs,
1828 .main_clk = "l3_gclk",
1829 .prcm = {
1830 .omap4 = {
1831 .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
1832 .modulemode = MODULEMODE_SWCTRL,
1833 },
1834 },
1835 };
1836
1837 /* tptc1 */
1838 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
1839 { .irq = 113 + OMAP_INTC_START, },
1840 { .irq = -1 },
1841 };
1842
1843 static struct omap_hwmod am33xx_tptc1_hwmod = {
1844 .name = "tptc1",
1845 .class = &am33xx_tptc_hwmod_class,
1846 .clkdm_name = "l3_clkdm",
1847 .mpu_irqs = am33xx_tptc1_irqs,
1848 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1849 .main_clk = "l3_gclk",
1850 .prcm = {
1851 .omap4 = {
1852 .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
1853 .modulemode = MODULEMODE_SWCTRL,
1854 },
1855 },
1856 };
1857
1858 /* tptc2 */
1859 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
1860 { .irq = 114 + OMAP_INTC_START, },
1861 { .irq = -1 },
1862 };
1863
1864 static struct omap_hwmod am33xx_tptc2_hwmod = {
1865 .name = "tptc2",
1866 .class = &am33xx_tptc_hwmod_class,
1867 .clkdm_name = "l3_clkdm",
1868 .mpu_irqs = am33xx_tptc2_irqs,
1869 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1870 .main_clk = "l3_gclk",
1871 .prcm = {
1872 .omap4 = {
1873 .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
1874 .modulemode = MODULEMODE_SWCTRL,
1875 },
1876 },
1877 };
1878
1879 /* 'uart' class */
1880 static struct omap_hwmod_class_sysconfig uart_sysc = {
1881 .rev_offs = 0x50,
1882 .sysc_offs = 0x54,
1883 .syss_offs = 0x58,
1884 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1885 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1886 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1887 SIDLE_SMART_WKUP),
1888 .sysc_fields = &omap_hwmod_sysc_type1,
1889 };
1890
1891 static struct omap_hwmod_class uart_class = {
1892 .name = "uart",
1893 .sysc = &uart_sysc,
1894 };
1895
1896 /* uart1 */
1897 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
1898 { .name = "tx", .dma_req = 26, },
1899 { .name = "rx", .dma_req = 27, },
1900 { .dma_req = -1 }
1901 };
1902
1903 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
1904 { .irq = 72 + OMAP_INTC_START, },
1905 { .irq = -1 },
1906 };
1907
1908 static struct omap_hwmod am33xx_uart1_hwmod = {
1909 .name = "uart1",
1910 .class = &uart_class,
1911 .clkdm_name = "l4_wkup_clkdm",
1912 .mpu_irqs = am33xx_uart1_irqs,
1913 .sdma_reqs = uart1_edma_reqs,
1914 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1915 .prcm = {
1916 .omap4 = {
1917 .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
1918 .modulemode = MODULEMODE_SWCTRL,
1919 },
1920 },
1921 };
1922
1923 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
1924 { .irq = 73 + OMAP_INTC_START, },
1925 { .irq = -1 },
1926 };
1927
1928 static struct omap_hwmod am33xx_uart2_hwmod = {
1929 .name = "uart2",
1930 .class = &uart_class,
1931 .clkdm_name = "l4ls_clkdm",
1932 .mpu_irqs = am33xx_uart2_irqs,
1933 .sdma_reqs = uart1_edma_reqs,
1934 .main_clk = "dpll_per_m2_div4_ck",
1935 .prcm = {
1936 .omap4 = {
1937 .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
1938 .modulemode = MODULEMODE_SWCTRL,
1939 },
1940 },
1941 };
1942
1943 /* uart3 */
1944 static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
1945 { .name = "tx", .dma_req = 30, },
1946 { .name = "rx", .dma_req = 31, },
1947 { .dma_req = -1 }
1948 };
1949
1950 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
1951 { .irq = 74 + OMAP_INTC_START, },
1952 { .irq = -1 },
1953 };
1954
1955 static struct omap_hwmod am33xx_uart3_hwmod = {
1956 .name = "uart3",
1957 .class = &uart_class,
1958 .clkdm_name = "l4ls_clkdm",
1959 .mpu_irqs = am33xx_uart3_irqs,
1960 .sdma_reqs = uart3_edma_reqs,
1961 .main_clk = "dpll_per_m2_div4_ck",
1962 .prcm = {
1963 .omap4 = {
1964 .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
1965 .modulemode = MODULEMODE_SWCTRL,
1966 },
1967 },
1968 };
1969
1970 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
1971 { .irq = 44 + OMAP_INTC_START, },
1972 { .irq = -1 },
1973 };
1974
1975 static struct omap_hwmod am33xx_uart4_hwmod = {
1976 .name = "uart4",
1977 .class = &uart_class,
1978 .clkdm_name = "l4ls_clkdm",
1979 .mpu_irqs = am33xx_uart4_irqs,
1980 .sdma_reqs = uart1_edma_reqs,
1981 .main_clk = "dpll_per_m2_div4_ck",
1982 .prcm = {
1983 .omap4 = {
1984 .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
1985 .modulemode = MODULEMODE_SWCTRL,
1986 },
1987 },
1988 };
1989
1990 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
1991 { .irq = 45 + OMAP_INTC_START, },
1992 { .irq = -1 },
1993 };
1994
1995 static struct omap_hwmod am33xx_uart5_hwmod = {
1996 .name = "uart5",
1997 .class = &uart_class,
1998 .clkdm_name = "l4ls_clkdm",
1999 .mpu_irqs = am33xx_uart5_irqs,
2000 .sdma_reqs = uart1_edma_reqs,
2001 .main_clk = "dpll_per_m2_div4_ck",
2002 .prcm = {
2003 .omap4 = {
2004 .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2005 .modulemode = MODULEMODE_SWCTRL,
2006 },
2007 },
2008 };
2009
2010 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2011 { .irq = 46 + OMAP_INTC_START, },
2012 { .irq = -1 },
2013 };
2014
2015 static struct omap_hwmod am33xx_uart6_hwmod = {
2016 .name = "uart6",
2017 .class = &uart_class,
2018 .clkdm_name = "l4ls_clkdm",
2019 .mpu_irqs = am33xx_uart6_irqs,
2020 .sdma_reqs = uart1_edma_reqs,
2021 .main_clk = "dpll_per_m2_div4_ck",
2022 .prcm = {
2023 .omap4 = {
2024 .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2025 .modulemode = MODULEMODE_SWCTRL,
2026 },
2027 },
2028 };
2029
2030 /* 'wd_timer' class */
2031 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2032 .name = "wd_timer",
2033 };
2034
2035 /*
2036 * XXX: device.c file uses hardcoded name for watchdog timer
2037 * driver "wd_timer2, so we are also using same name as of now...
2038 */
2039 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2040 .name = "wd_timer2",
2041 .class = &am33xx_wd_timer_hwmod_class,
2042 .clkdm_name = "l4_wkup_clkdm",
2043 .main_clk = "wdt1_fck",
2044 .prcm = {
2045 .omap4 = {
2046 .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2047 .modulemode = MODULEMODE_SWCTRL,
2048 },
2049 },
2050 };
2051
2052 /*
2053 * 'usb_otg' class
2054 * high-speed on-the-go universal serial bus (usb_otg) controller
2055 */
2056 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2057 .rev_offs = 0x0,
2058 .sysc_offs = 0x10,
2059 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
2060 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2061 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2062 .sysc_fields = &omap_hwmod_sysc_type2,
2063 };
2064
2065 static struct omap_hwmod_class am33xx_usbotg_class = {
2066 .name = "usbotg",
2067 .sysc = &am33xx_usbhsotg_sysc,
2068 };
2069
2070 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2071 { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
2072 { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
2073 { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
2074 { .irq = -1 + OMAP_INTC_START, },
2075 };
2076
2077 static struct omap_hwmod am33xx_usbss_hwmod = {
2078 .name = "usb_otg_hs",
2079 .class = &am33xx_usbotg_class,
2080 .clkdm_name = "l3s_clkdm",
2081 .mpu_irqs = am33xx_usbss_mpu_irqs,
2082 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2083 .main_clk = "usbotg_fck",
2084 .prcm = {
2085 .omap4 = {
2086 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
2087 .modulemode = MODULEMODE_SWCTRL,
2088 },
2089 },
2090 };
2091
2092
2093 /*
2094 * Interfaces
2095 */
2096
2097 /* l4 fw -> emif fw */
2098 static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
2099 .master = &am33xx_l4_fw_hwmod,
2100 .slave = &am33xx_emif_fw_hwmod,
2101 .clk = "l4fw_gclk",
2102 .user = OCP_USER_MPU,
2103 };
2104
2105 static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
2106 {
2107 .pa_start = 0x4c000000,
2108 .pa_end = 0x4c000fff,
2109 .flags = ADDR_TYPE_RT
2110 },
2111 { }
2112 };
2113 /* l3 main -> emif */
2114 static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
2115 .master = &am33xx_l3_main_hwmod,
2116 .slave = &am33xx_emif_hwmod,
2117 .clk = "dpll_core_m4_ck",
2118 .addr = am33xx_emif_addrs,
2119 .user = OCP_USER_MPU | OCP_USER_SDMA,
2120 };
2121
2122 /* mpu -> l3 main */
2123 static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
2124 .master = &am33xx_mpu_hwmod,
2125 .slave = &am33xx_l3_main_hwmod,
2126 .clk = "dpll_mpu_m2_ck",
2127 .user = OCP_USER_MPU,
2128 };
2129
2130 /* l3 main -> l4 hs */
2131 static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
2132 .master = &am33xx_l3_main_hwmod,
2133 .slave = &am33xx_l4_hs_hwmod,
2134 .clk = "l3s_gclk",
2135 .user = OCP_USER_MPU | OCP_USER_SDMA,
2136 };
2137
2138 /* l3 main -> l3 s */
2139 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
2140 .master = &am33xx_l3_main_hwmod,
2141 .slave = &am33xx_l3_s_hwmod,
2142 .clk = "l3s_gclk",
2143 .user = OCP_USER_MPU | OCP_USER_SDMA,
2144 };
2145
2146 /* l3 s -> l4 per/ls */
2147 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
2148 .master = &am33xx_l3_s_hwmod,
2149 .slave = &am33xx_l4_ls_hwmod,
2150 .clk = "l3s_gclk",
2151 .user = OCP_USER_MPU | OCP_USER_SDMA,
2152 };
2153
2154 /* l3 s -> l4 wkup */
2155 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
2156 .master = &am33xx_l3_s_hwmod,
2157 .slave = &am33xx_l4_wkup_hwmod,
2158 .clk = "l3s_gclk",
2159 .user = OCP_USER_MPU | OCP_USER_SDMA,
2160 };
2161
2162 /* l3 s -> l4 fw */
2163 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
2164 .master = &am33xx_l3_s_hwmod,
2165 .slave = &am33xx_l4_fw_hwmod,
2166 .clk = "l3s_gclk",
2167 .user = OCP_USER_MPU | OCP_USER_SDMA,
2168 };
2169
2170 /* l3 main -> l3 instr */
2171 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
2172 .master = &am33xx_l3_main_hwmod,
2173 .slave = &am33xx_l3_instr_hwmod,
2174 .clk = "l3s_gclk",
2175 .user = OCP_USER_MPU | OCP_USER_SDMA,
2176 };
2177
2178 /* mpu -> prcm */
2179 static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
2180 .master = &am33xx_mpu_hwmod,
2181 .slave = &am33xx_prcm_hwmod,
2182 .clk = "dpll_mpu_m2_ck",
2183 .user = OCP_USER_MPU | OCP_USER_SDMA,
2184 };
2185
2186 /* l3 s -> l3 main*/
2187 static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
2188 .master = &am33xx_l3_s_hwmod,
2189 .slave = &am33xx_l3_main_hwmod,
2190 .clk = "l3s_gclk",
2191 .user = OCP_USER_MPU | OCP_USER_SDMA,
2192 };
2193
2194 /* pru-icss -> l3 main */
2195 static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
2196 .master = &am33xx_pruss_hwmod,
2197 .slave = &am33xx_l3_main_hwmod,
2198 .clk = "l3_gclk",
2199 .user = OCP_USER_MPU | OCP_USER_SDMA,
2200 };
2201
2202 /* wkup m3 -> l4 wkup */
2203 static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
2204 .master = &am33xx_wkup_m3_hwmod,
2205 .slave = &am33xx_l4_wkup_hwmod,
2206 .clk = "dpll_core_m4_div2_ck",
2207 .user = OCP_USER_MPU | OCP_USER_SDMA,
2208 };
2209
2210 /* gfx -> l3 main */
2211 static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
2212 .master = &am33xx_gfx_hwmod,
2213 .slave = &am33xx_l3_main_hwmod,
2214 .clk = "dpll_core_m4_ck",
2215 .user = OCP_USER_MPU | OCP_USER_SDMA,
2216 };
2217
2218 /* l4 wkup -> wkup m3 */
2219 static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
2220 {
2221 .name = "umem",
2222 .pa_start = 0x44d00000,
2223 .pa_end = 0x44d00000 + SZ_16K - 1,
2224 .flags = ADDR_TYPE_RT
2225 },
2226 {
2227 .name = "dmem",
2228 .pa_start = 0x44d80000,
2229 .pa_end = 0x44d80000 + SZ_8K - 1,
2230 .flags = ADDR_TYPE_RT
2231 },
2232 { }
2233 };
2234
2235 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
2236 .master = &am33xx_l4_wkup_hwmod,
2237 .slave = &am33xx_wkup_m3_hwmod,
2238 .clk = "dpll_core_m4_div2_ck",
2239 .addr = am33xx_wkup_m3_addrs,
2240 .user = OCP_USER_MPU | OCP_USER_SDMA,
2241 };
2242
2243 /* l4 hs -> pru-icss */
2244 static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
2245 {
2246 .pa_start = 0x4a300000,
2247 .pa_end = 0x4a300000 + SZ_512K - 1,
2248 .flags = ADDR_TYPE_RT
2249 },
2250 { }
2251 };
2252
2253 static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
2254 .master = &am33xx_l4_hs_hwmod,
2255 .slave = &am33xx_pruss_hwmod,
2256 .clk = "dpll_core_m4_ck",
2257 .addr = am33xx_pruss_addrs,
2258 .user = OCP_USER_MPU | OCP_USER_SDMA,
2259 };
2260
2261 /* l3 main -> gfx */
2262 static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
2263 {
2264 .pa_start = 0x56000000,
2265 .pa_end = 0x56000000 + SZ_16M - 1,
2266 .flags = ADDR_TYPE_RT
2267 },
2268 { }
2269 };
2270
2271 static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
2272 .master = &am33xx_l3_main_hwmod,
2273 .slave = &am33xx_gfx_hwmod,
2274 .clk = "dpll_core_m4_ck",
2275 .addr = am33xx_gfx_addrs,
2276 .user = OCP_USER_MPU | OCP_USER_SDMA,
2277 };
2278
2279 /* l4 wkup -> smartreflex0 */
2280 static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
2281 {
2282 .pa_start = 0x44e37000,
2283 .pa_end = 0x44e37000 + SZ_4K - 1,
2284 .flags = ADDR_TYPE_RT
2285 },
2286 { }
2287 };
2288
2289 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
2290 .master = &am33xx_l4_wkup_hwmod,
2291 .slave = &am33xx_smartreflex0_hwmod,
2292 .clk = "dpll_core_m4_div2_ck",
2293 .addr = am33xx_smartreflex0_addrs,
2294 .user = OCP_USER_MPU,
2295 };
2296
2297 /* l4 wkup -> smartreflex1 */
2298 static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
2299 {
2300 .pa_start = 0x44e39000,
2301 .pa_end = 0x44e39000 + SZ_4K - 1,
2302 .flags = ADDR_TYPE_RT
2303 },
2304 { }
2305 };
2306
2307 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
2308 .master = &am33xx_l4_wkup_hwmod,
2309 .slave = &am33xx_smartreflex1_hwmod,
2310 .clk = "dpll_core_m4_div2_ck",
2311 .addr = am33xx_smartreflex1_addrs,
2312 .user = OCP_USER_MPU,
2313 };
2314
2315 /* l4 wkup -> control */
2316 static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
2317 {
2318 .pa_start = 0x44e10000,
2319 .pa_end = 0x44e10000 + SZ_8K - 1,
2320 .flags = ADDR_TYPE_RT
2321 },
2322 { }
2323 };
2324
2325 static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
2326 .master = &am33xx_l4_wkup_hwmod,
2327 .slave = &am33xx_control_hwmod,
2328 .clk = "dpll_core_m4_div2_ck",
2329 .addr = am33xx_control_addrs,
2330 .user = OCP_USER_MPU,
2331 };
2332
2333 /* l4 wkup -> rtc */
2334 static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
2335 {
2336 .pa_start = 0x44e3e000,
2337 .pa_end = 0x44e3e000 + SZ_4K - 1,
2338 .flags = ADDR_TYPE_RT
2339 },
2340 { }
2341 };
2342
2343 static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
2344 .master = &am33xx_l4_wkup_hwmod,
2345 .slave = &am33xx_rtc_hwmod,
2346 .clk = "clkdiv32k_ick",
2347 .addr = am33xx_rtc_addrs,
2348 .user = OCP_USER_MPU,
2349 };
2350
2351 /* l4 per/ls -> DCAN0 */
2352 static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
2353 {
2354 .pa_start = 0x481CC000,
2355 .pa_end = 0x481CC000 + SZ_4K - 1,
2356 .flags = ADDR_TYPE_RT
2357 },
2358 { }
2359 };
2360
2361 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
2362 .master = &am33xx_l4_ls_hwmod,
2363 .slave = &am33xx_dcan0_hwmod,
2364 .clk = "l4ls_gclk",
2365 .addr = am33xx_dcan0_addrs,
2366 .user = OCP_USER_MPU | OCP_USER_SDMA,
2367 };
2368
2369 /* l4 per/ls -> DCAN1 */
2370 static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
2371 {
2372 .pa_start = 0x481D0000,
2373 .pa_end = 0x481D0000 + SZ_4K - 1,
2374 .flags = ADDR_TYPE_RT
2375 },
2376 { }
2377 };
2378
2379 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
2380 .master = &am33xx_l4_ls_hwmod,
2381 .slave = &am33xx_dcan1_hwmod,
2382 .clk = "l4ls_gclk",
2383 .addr = am33xx_dcan1_addrs,
2384 .user = OCP_USER_MPU | OCP_USER_SDMA,
2385 };
2386
2387 /* l4 per/ls -> GPIO2 */
2388 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
2389 {
2390 .pa_start = 0x4804C000,
2391 .pa_end = 0x4804C000 + SZ_4K - 1,
2392 .flags = ADDR_TYPE_RT,
2393 },
2394 { }
2395 };
2396
2397 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
2398 .master = &am33xx_l4_ls_hwmod,
2399 .slave = &am33xx_gpio1_hwmod,
2400 .clk = "l4ls_gclk",
2401 .addr = am33xx_gpio1_addrs,
2402 .user = OCP_USER_MPU | OCP_USER_SDMA,
2403 };
2404
2405 /* l4 per/ls -> gpio3 */
2406 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
2407 {
2408 .pa_start = 0x481AC000,
2409 .pa_end = 0x481AC000 + SZ_4K - 1,
2410 .flags = ADDR_TYPE_RT,
2411 },
2412 { }
2413 };
2414
2415 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
2416 .master = &am33xx_l4_ls_hwmod,
2417 .slave = &am33xx_gpio2_hwmod,
2418 .clk = "l4ls_gclk",
2419 .addr = am33xx_gpio2_addrs,
2420 .user = OCP_USER_MPU | OCP_USER_SDMA,
2421 };
2422
2423 /* l4 per/ls -> gpio4 */
2424 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
2425 {
2426 .pa_start = 0x481AE000,
2427 .pa_end = 0x481AE000 + SZ_4K - 1,
2428 .flags = ADDR_TYPE_RT,
2429 },
2430 { }
2431 };
2432
2433 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
2434 .master = &am33xx_l4_ls_hwmod,
2435 .slave = &am33xx_gpio3_hwmod,
2436 .clk = "l4ls_gclk",
2437 .addr = am33xx_gpio3_addrs,
2438 .user = OCP_USER_MPU | OCP_USER_SDMA,
2439 };
2440
2441 /* L4 WKUP -> I2C1 */
2442 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
2443 {
2444 .pa_start = 0x44E0B000,
2445 .pa_end = 0x44E0B000 + SZ_4K - 1,
2446 .flags = ADDR_TYPE_RT,
2447 },
2448 { }
2449 };
2450
2451 static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
2452 .master = &am33xx_l4_wkup_hwmod,
2453 .slave = &am33xx_i2c1_hwmod,
2454 .clk = "dpll_core_m4_div2_ck",
2455 .addr = am33xx_i2c1_addr_space,
2456 .user = OCP_USER_MPU,
2457 };
2458
2459 /* L4 WKUP -> GPIO1 */
2460 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
2461 {
2462 .pa_start = 0x44E07000,
2463 .pa_end = 0x44E07000 + SZ_4K - 1,
2464 .flags = ADDR_TYPE_RT,
2465 },
2466 { }
2467 };
2468
2469 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
2470 .master = &am33xx_l4_wkup_hwmod,
2471 .slave = &am33xx_gpio0_hwmod,
2472 .clk = "dpll_core_m4_div2_ck",
2473 .addr = am33xx_gpio0_addrs,
2474 .user = OCP_USER_MPU | OCP_USER_SDMA,
2475 };
2476
2477 /* L4 WKUP -> ADC_TSC */
2478 static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
2479 {
2480 .pa_start = 0x44E0D000,
2481 .pa_end = 0x44E0D000 + SZ_8K - 1,
2482 .flags = ADDR_TYPE_RT
2483 },
2484 { }
2485 };
2486
2487 static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
2488 .master = &am33xx_l4_wkup_hwmod,
2489 .slave = &am33xx_adc_tsc_hwmod,
2490 .clk = "dpll_core_m4_div2_ck",
2491 .addr = am33xx_adc_tsc_addrs,
2492 .user = OCP_USER_MPU,
2493 };
2494
2495 static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
2496 /* cpsw ss */
2497 {
2498 .pa_start = 0x4a100000,
2499 .pa_end = 0x4a100000 + SZ_2K - 1,
2500 .flags = ADDR_TYPE_RT,
2501 },
2502 /* cpsw wr */
2503 {
2504 .pa_start = 0x4a101200,
2505 .pa_end = 0x4a101200 + SZ_256 - 1,
2506 .flags = ADDR_TYPE_RT,
2507 },
2508 { }
2509 };
2510
2511 static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
2512 .master = &am33xx_l4_hs_hwmod,
2513 .slave = &am33xx_cpgmac0_hwmod,
2514 .clk = "cpsw_125mhz_gclk",
2515 .addr = am33xx_cpgmac0_addr_space,
2516 .user = OCP_USER_MPU,
2517 };
2518
2519 struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
2520 {
2521 .pa_start = 0x4A101000,
2522 .pa_end = 0x4A101000 + SZ_256 - 1,
2523 },
2524 { }
2525 };
2526
2527 struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
2528 .master = &am33xx_cpgmac0_hwmod,
2529 .slave = &am33xx_mdio_hwmod,
2530 .addr = am33xx_mdio_addr_space,
2531 .user = OCP_USER_MPU,
2532 };
2533
2534 static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
2535 {
2536 .pa_start = 0x48080000,
2537 .pa_end = 0x48080000 + SZ_8K - 1,
2538 .flags = ADDR_TYPE_RT
2539 },
2540 { }
2541 };
2542
2543 static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
2544 .master = &am33xx_l4_ls_hwmod,
2545 .slave = &am33xx_elm_hwmod,
2546 .clk = "l4ls_gclk",
2547 .addr = am33xx_elm_addr_space,
2548 .user = OCP_USER_MPU,
2549 };
2550
2551 /*
2552 * Splitting the resources to handle access of PWMSS config space
2553 * and module specific part independently
2554 */
2555 static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
2556 {
2557 .pa_start = 0x48300000,
2558 .pa_end = 0x48300000 + SZ_16 - 1,
2559 .flags = ADDR_TYPE_RT
2560 },
2561 {
2562 .pa_start = 0x48300200,
2563 .pa_end = 0x48300200 + SZ_256 - 1,
2564 .flags = ADDR_TYPE_RT
2565 },
2566 { }
2567 };
2568
2569 static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = {
2570 .master = &am33xx_l4_ls_hwmod,
2571 .slave = &am33xx_ehrpwm0_hwmod,
2572 .clk = "l4ls_gclk",
2573 .addr = am33xx_ehrpwm0_addr_space,
2574 .user = OCP_USER_MPU,
2575 };
2576
2577 /*
2578 * Splitting the resources to handle access of PWMSS config space
2579 * and module specific part independently
2580 */
2581 static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
2582 {
2583 .pa_start = 0x48302000,
2584 .pa_end = 0x48302000 + SZ_16 - 1,
2585 .flags = ADDR_TYPE_RT
2586 },
2587 {
2588 .pa_start = 0x48302200,
2589 .pa_end = 0x48302200 + SZ_256 - 1,
2590 .flags = ADDR_TYPE_RT
2591 },
2592 { }
2593 };
2594
2595 static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = {
2596 .master = &am33xx_l4_ls_hwmod,
2597 .slave = &am33xx_ehrpwm1_hwmod,
2598 .clk = "l4ls_gclk",
2599 .addr = am33xx_ehrpwm1_addr_space,
2600 .user = OCP_USER_MPU,
2601 };
2602
2603 /*
2604 * Splitting the resources to handle access of PWMSS config space
2605 * and module specific part independently
2606 */
2607 static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
2608 {
2609 .pa_start = 0x48304000,
2610 .pa_end = 0x48304000 + SZ_16 - 1,
2611 .flags = ADDR_TYPE_RT
2612 },
2613 {
2614 .pa_start = 0x48304200,
2615 .pa_end = 0x48304200 + SZ_256 - 1,
2616 .flags = ADDR_TYPE_RT
2617 },
2618 { }
2619 };
2620
2621 static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = {
2622 .master = &am33xx_l4_ls_hwmod,
2623 .slave = &am33xx_ehrpwm2_hwmod,
2624 .clk = "l4ls_gclk",
2625 .addr = am33xx_ehrpwm2_addr_space,
2626 .user = OCP_USER_MPU,
2627 };
2628
2629 /*
2630 * Splitting the resources to handle access of PWMSS config space
2631 * and module specific part independently
2632 */
2633 static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
2634 {
2635 .pa_start = 0x48300000,
2636 .pa_end = 0x48300000 + SZ_16 - 1,
2637 .flags = ADDR_TYPE_RT
2638 },
2639 {
2640 .pa_start = 0x48300100,
2641 .pa_end = 0x48300100 + SZ_256 - 1,
2642 .flags = ADDR_TYPE_RT
2643 },
2644 { }
2645 };
2646
2647 static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = {
2648 .master = &am33xx_l4_ls_hwmod,
2649 .slave = &am33xx_ecap0_hwmod,
2650 .clk = "l4ls_gclk",
2651 .addr = am33xx_ecap0_addr_space,
2652 .user = OCP_USER_MPU,
2653 };
2654
2655 /*
2656 * Splitting the resources to handle access of PWMSS config space
2657 * and module specific part independently
2658 */
2659 static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
2660 {
2661 .pa_start = 0x48302000,
2662 .pa_end = 0x48302000 + SZ_16 - 1,
2663 .flags = ADDR_TYPE_RT
2664 },
2665 {
2666 .pa_start = 0x48302100,
2667 .pa_end = 0x48302100 + SZ_256 - 1,
2668 .flags = ADDR_TYPE_RT
2669 },
2670 { }
2671 };
2672
2673 static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = {
2674 .master = &am33xx_l4_ls_hwmod,
2675 .slave = &am33xx_ecap1_hwmod,
2676 .clk = "l4ls_gclk",
2677 .addr = am33xx_ecap1_addr_space,
2678 .user = OCP_USER_MPU,
2679 };
2680
2681 /*
2682 * Splitting the resources to handle access of PWMSS config space
2683 * and module specific part independently
2684 */
2685 static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
2686 {
2687 .pa_start = 0x48304000,
2688 .pa_end = 0x48304000 + SZ_16 - 1,
2689 .flags = ADDR_TYPE_RT
2690 },
2691 {
2692 .pa_start = 0x48304100,
2693 .pa_end = 0x48304100 + SZ_256 - 1,
2694 .flags = ADDR_TYPE_RT
2695 },
2696 { }
2697 };
2698
2699 static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = {
2700 .master = &am33xx_l4_ls_hwmod,
2701 .slave = &am33xx_ecap2_hwmod,
2702 .clk = "l4ls_gclk",
2703 .addr = am33xx_ecap2_addr_space,
2704 .user = OCP_USER_MPU,
2705 };
2706
2707 /* l3s cfg -> gpmc */
2708 static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
2709 {
2710 .pa_start = 0x50000000,
2711 .pa_end = 0x50000000 + SZ_8K - 1,
2712 .flags = ADDR_TYPE_RT,
2713 },
2714 { }
2715 };
2716
2717 static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
2718 .master = &am33xx_l3_s_hwmod,
2719 .slave = &am33xx_gpmc_hwmod,
2720 .clk = "l3s_gclk",
2721 .addr = am33xx_gpmc_addr_space,
2722 .user = OCP_USER_MPU,
2723 };
2724
2725 /* i2c2 */
2726 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
2727 {
2728 .pa_start = 0x4802A000,
2729 .pa_end = 0x4802A000 + SZ_4K - 1,
2730 .flags = ADDR_TYPE_RT,
2731 },
2732 { }
2733 };
2734
2735 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
2736 .master = &am33xx_l4_ls_hwmod,
2737 .slave = &am33xx_i2c2_hwmod,
2738 .clk = "l4ls_gclk",
2739 .addr = am33xx_i2c2_addr_space,
2740 .user = OCP_USER_MPU,
2741 };
2742
2743 static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
2744 {
2745 .pa_start = 0x4819C000,
2746 .pa_end = 0x4819C000 + SZ_4K - 1,
2747 .flags = ADDR_TYPE_RT
2748 },
2749 { }
2750 };
2751
2752 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
2753 .master = &am33xx_l4_ls_hwmod,
2754 .slave = &am33xx_i2c3_hwmod,
2755 .clk = "l4ls_gclk",
2756 .addr = am33xx_i2c3_addr_space,
2757 .user = OCP_USER_MPU,
2758 };
2759
2760 static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
2761 {
2762 .pa_start = 0x4830E000,
2763 .pa_end = 0x4830E000 + SZ_8K - 1,
2764 .flags = ADDR_TYPE_RT,
2765 },
2766 { }
2767 };
2768
2769 static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
2770 .master = &am33xx_l3_main_hwmod,
2771 .slave = &am33xx_lcdc_hwmod,
2772 .clk = "dpll_core_m4_ck",
2773 .addr = am33xx_lcdc_addr_space,
2774 .user = OCP_USER_MPU,
2775 };
2776
2777 static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
2778 {
2779 .pa_start = 0x480C8000,
2780 .pa_end = 0x480C8000 + (SZ_4K - 1),
2781 .flags = ADDR_TYPE_RT
2782 },
2783 { }
2784 };
2785
2786 /* l4 ls -> mailbox */
2787 static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
2788 .master = &am33xx_l4_ls_hwmod,
2789 .slave = &am33xx_mailbox_hwmod,
2790 .clk = "l4ls_gclk",
2791 .addr = am33xx_mailbox_addrs,
2792 .user = OCP_USER_MPU,
2793 };
2794
2795 /* l4 ls -> spinlock */
2796 static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
2797 {
2798 .pa_start = 0x480Ca000,
2799 .pa_end = 0x480Ca000 + SZ_4K - 1,
2800 .flags = ADDR_TYPE_RT
2801 },
2802 { }
2803 };
2804
2805 static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
2806 .master = &am33xx_l4_ls_hwmod,
2807 .slave = &am33xx_spinlock_hwmod,
2808 .clk = "l4ls_gclk",
2809 .addr = am33xx_spinlock_addrs,
2810 .user = OCP_USER_MPU,
2811 };
2812
2813 /* l4 ls -> mcasp0 */
2814 static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
2815 {
2816 .pa_start = 0x48038000,
2817 .pa_end = 0x48038000 + SZ_8K - 1,
2818 .flags = ADDR_TYPE_RT
2819 },
2820 { }
2821 };
2822
2823 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
2824 .master = &am33xx_l4_ls_hwmod,
2825 .slave = &am33xx_mcasp0_hwmod,
2826 .clk = "l4ls_gclk",
2827 .addr = am33xx_mcasp0_addr_space,
2828 .user = OCP_USER_MPU,
2829 };
2830
2831 /* l3 s -> mcasp0 data */
2832 static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
2833 {
2834 .pa_start = 0x46000000,
2835 .pa_end = 0x46000000 + SZ_4M - 1,
2836 .flags = ADDR_TYPE_RT
2837 },
2838 { }
2839 };
2840
2841 static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
2842 .master = &am33xx_l3_s_hwmod,
2843 .slave = &am33xx_mcasp0_hwmod,
2844 .clk = "l3s_gclk",
2845 .addr = am33xx_mcasp0_data_addr_space,
2846 .user = OCP_USER_SDMA,
2847 };
2848
2849 /* l4 ls -> mcasp1 */
2850 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
2851 {
2852 .pa_start = 0x4803C000,
2853 .pa_end = 0x4803C000 + SZ_8K - 1,
2854 .flags = ADDR_TYPE_RT
2855 },
2856 { }
2857 };
2858
2859 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
2860 .master = &am33xx_l4_ls_hwmod,
2861 .slave = &am33xx_mcasp1_hwmod,
2862 .clk = "l4ls_gclk",
2863 .addr = am33xx_mcasp1_addr_space,
2864 .user = OCP_USER_MPU,
2865 };
2866
2867 /* l3 s -> mcasp1 data */
2868 static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
2869 {
2870 .pa_start = 0x46400000,
2871 .pa_end = 0x46400000 + SZ_4M - 1,
2872 .flags = ADDR_TYPE_RT
2873 },
2874 { }
2875 };
2876
2877 static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
2878 .master = &am33xx_l3_s_hwmod,
2879 .slave = &am33xx_mcasp1_hwmod,
2880 .clk = "l3s_gclk",
2881 .addr = am33xx_mcasp1_data_addr_space,
2882 .user = OCP_USER_SDMA,
2883 };
2884
2885 /* l4 ls -> mmc0 */
2886 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
2887 {
2888 .pa_start = 0x48060100,
2889 .pa_end = 0x48060100 + SZ_4K - 1,
2890 .flags = ADDR_TYPE_RT,
2891 },
2892 { }
2893 };
2894
2895 static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
2896 .master = &am33xx_l4_ls_hwmod,
2897 .slave = &am33xx_mmc0_hwmod,
2898 .clk = "l4ls_gclk",
2899 .addr = am33xx_mmc0_addr_space,
2900 .user = OCP_USER_MPU,
2901 };
2902
2903 /* l4 ls -> mmc1 */
2904 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
2905 {
2906 .pa_start = 0x481d8100,
2907 .pa_end = 0x481d8100 + SZ_4K - 1,
2908 .flags = ADDR_TYPE_RT,
2909 },
2910 { }
2911 };
2912
2913 static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
2914 .master = &am33xx_l4_ls_hwmod,
2915 .slave = &am33xx_mmc1_hwmod,
2916 .clk = "l4ls_gclk",
2917 .addr = am33xx_mmc1_addr_space,
2918 .user = OCP_USER_MPU,
2919 };
2920
2921 /* l3 s -> mmc2 */
2922 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
2923 {
2924 .pa_start = 0x47810100,
2925 .pa_end = 0x47810100 + SZ_64K - 1,
2926 .flags = ADDR_TYPE_RT,
2927 },
2928 { }
2929 };
2930
2931 static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
2932 .master = &am33xx_l3_s_hwmod,
2933 .slave = &am33xx_mmc2_hwmod,
2934 .clk = "l3s_gclk",
2935 .addr = am33xx_mmc2_addr_space,
2936 .user = OCP_USER_MPU,
2937 };
2938
2939 /* l4 ls -> mcspi0 */
2940 static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
2941 {
2942 .pa_start = 0x48030000,
2943 .pa_end = 0x48030000 + SZ_1K - 1,
2944 .flags = ADDR_TYPE_RT,
2945 },
2946 { }
2947 };
2948
2949 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
2950 .master = &am33xx_l4_ls_hwmod,
2951 .slave = &am33xx_spi0_hwmod,
2952 .clk = "l4ls_gclk",
2953 .addr = am33xx_mcspi0_addr_space,
2954 .user = OCP_USER_MPU,
2955 };
2956
2957 /* l4 ls -> mcspi1 */
2958 static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
2959 {
2960 .pa_start = 0x481A0000,
2961 .pa_end = 0x481A0000 + SZ_1K - 1,
2962 .flags = ADDR_TYPE_RT,
2963 },
2964 { }
2965 };
2966
2967 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
2968 .master = &am33xx_l4_ls_hwmod,
2969 .slave = &am33xx_spi1_hwmod,
2970 .clk = "l4ls_gclk",
2971 .addr = am33xx_mcspi1_addr_space,
2972 .user = OCP_USER_MPU,
2973 };
2974
2975 /* l4 wkup -> timer1 */
2976 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
2977 {
2978 .pa_start = 0x44E31000,
2979 .pa_end = 0x44E31000 + SZ_1K - 1,
2980 .flags = ADDR_TYPE_RT
2981 },
2982 { }
2983 };
2984
2985 static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
2986 .master = &am33xx_l4_wkup_hwmod,
2987 .slave = &am33xx_timer1_hwmod,
2988 .clk = "dpll_core_m4_div2_ck",
2989 .addr = am33xx_timer1_addr_space,
2990 .user = OCP_USER_MPU,
2991 };
2992
2993 /* l4 per -> timer2 */
2994 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
2995 {
2996 .pa_start = 0x48040000,
2997 .pa_end = 0x48040000 + SZ_1K - 1,
2998 .flags = ADDR_TYPE_RT
2999 },
3000 { }
3001 };
3002
3003 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
3004 .master = &am33xx_l4_ls_hwmod,
3005 .slave = &am33xx_timer2_hwmod,
3006 .clk = "l4ls_gclk",
3007 .addr = am33xx_timer2_addr_space,
3008 .user = OCP_USER_MPU,
3009 };
3010
3011 /* l4 per -> timer3 */
3012 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
3013 {
3014 .pa_start = 0x48042000,
3015 .pa_end = 0x48042000 + SZ_1K - 1,
3016 .flags = ADDR_TYPE_RT
3017 },
3018 { }
3019 };
3020
3021 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
3022 .master = &am33xx_l4_ls_hwmod,
3023 .slave = &am33xx_timer3_hwmod,
3024 .clk = "l4ls_gclk",
3025 .addr = am33xx_timer3_addr_space,
3026 .user = OCP_USER_MPU,
3027 };
3028
3029 /* l4 per -> timer4 */
3030 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
3031 {
3032 .pa_start = 0x48044000,
3033 .pa_end = 0x48044000 + SZ_1K - 1,
3034 .flags = ADDR_TYPE_RT
3035 },
3036 { }
3037 };
3038
3039 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
3040 .master = &am33xx_l4_ls_hwmod,
3041 .slave = &am33xx_timer4_hwmod,
3042 .clk = "l4ls_gclk",
3043 .addr = am33xx_timer4_addr_space,
3044 .user = OCP_USER_MPU,
3045 };
3046
3047 /* l4 per -> timer5 */
3048 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
3049 {
3050 .pa_start = 0x48046000,
3051 .pa_end = 0x48046000 + SZ_1K - 1,
3052 .flags = ADDR_TYPE_RT
3053 },
3054 { }
3055 };
3056
3057 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
3058 .master = &am33xx_l4_ls_hwmod,
3059 .slave = &am33xx_timer5_hwmod,
3060 .clk = "l4ls_gclk",
3061 .addr = am33xx_timer5_addr_space,
3062 .user = OCP_USER_MPU,
3063 };
3064
3065 /* l4 per -> timer6 */
3066 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
3067 {
3068 .pa_start = 0x48048000,
3069 .pa_end = 0x48048000 + SZ_1K - 1,
3070 .flags = ADDR_TYPE_RT
3071 },
3072 { }
3073 };
3074
3075 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
3076 .master = &am33xx_l4_ls_hwmod,
3077 .slave = &am33xx_timer6_hwmod,
3078 .clk = "l4ls_gclk",
3079 .addr = am33xx_timer6_addr_space,
3080 .user = OCP_USER_MPU,
3081 };
3082
3083 /* l4 per -> timer7 */
3084 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
3085 {
3086 .pa_start = 0x4804A000,
3087 .pa_end = 0x4804A000 + SZ_1K - 1,
3088 .flags = ADDR_TYPE_RT
3089 },
3090 { }
3091 };
3092
3093 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
3094 .master = &am33xx_l4_ls_hwmod,
3095 .slave = &am33xx_timer7_hwmod,
3096 .clk = "l4ls_gclk",
3097 .addr = am33xx_timer7_addr_space,
3098 .user = OCP_USER_MPU,
3099 };
3100
3101 /* l3 main -> tpcc */
3102 static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
3103 {
3104 .pa_start = 0x49000000,
3105 .pa_end = 0x49000000 + SZ_32K - 1,
3106 .flags = ADDR_TYPE_RT
3107 },
3108 { }
3109 };
3110
3111 static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
3112 .master = &am33xx_l3_main_hwmod,
3113 .slave = &am33xx_tpcc_hwmod,
3114 .clk = "l3_gclk",
3115 .addr = am33xx_tpcc_addr_space,
3116 .user = OCP_USER_MPU,
3117 };
3118
3119 /* l3 main -> tpcc0 */
3120 static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
3121 {
3122 .pa_start = 0x49800000,
3123 .pa_end = 0x49800000 + SZ_8K - 1,
3124 .flags = ADDR_TYPE_RT,
3125 },
3126 { }
3127 };
3128
3129 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
3130 .master = &am33xx_l3_main_hwmod,
3131 .slave = &am33xx_tptc0_hwmod,
3132 .clk = "l3_gclk",
3133 .addr = am33xx_tptc0_addr_space,
3134 .user = OCP_USER_MPU,
3135 };
3136
3137 /* l3 main -> tpcc1 */
3138 static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
3139 {
3140 .pa_start = 0x49900000,
3141 .pa_end = 0x49900000 + SZ_8K - 1,
3142 .flags = ADDR_TYPE_RT,
3143 },
3144 { }
3145 };
3146
3147 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
3148 .master = &am33xx_l3_main_hwmod,
3149 .slave = &am33xx_tptc1_hwmod,
3150 .clk = "l3_gclk",
3151 .addr = am33xx_tptc1_addr_space,
3152 .user = OCP_USER_MPU,
3153 };
3154
3155 /* l3 main -> tpcc2 */
3156 static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
3157 {
3158 .pa_start = 0x49a00000,
3159 .pa_end = 0x49a00000 + SZ_8K - 1,
3160 .flags = ADDR_TYPE_RT,
3161 },
3162 { }
3163 };
3164
3165 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
3166 .master = &am33xx_l3_main_hwmod,
3167 .slave = &am33xx_tptc2_hwmod,
3168 .clk = "l3_gclk",
3169 .addr = am33xx_tptc2_addr_space,
3170 .user = OCP_USER_MPU,
3171 };
3172
3173 /* l4 wkup -> uart1 */
3174 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
3175 {
3176 .pa_start = 0x44E09000,
3177 .pa_end = 0x44E09000 + SZ_8K - 1,
3178 .flags = ADDR_TYPE_RT,
3179 },
3180 { }
3181 };
3182
3183 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
3184 .master = &am33xx_l4_wkup_hwmod,
3185 .slave = &am33xx_uart1_hwmod,
3186 .clk = "dpll_core_m4_div2_ck",
3187 .addr = am33xx_uart1_addr_space,
3188 .user = OCP_USER_MPU,
3189 };
3190
3191 /* l4 ls -> uart2 */
3192 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
3193 {
3194 .pa_start = 0x48022000,
3195 .pa_end = 0x48022000 + SZ_8K - 1,
3196 .flags = ADDR_TYPE_RT,
3197 },
3198 { }
3199 };
3200
3201 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
3202 .master = &am33xx_l4_ls_hwmod,
3203 .slave = &am33xx_uart2_hwmod,
3204 .clk = "l4ls_gclk",
3205 .addr = am33xx_uart2_addr_space,
3206 .user = OCP_USER_MPU,
3207 };
3208
3209 /* l4 ls -> uart3 */
3210 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
3211 {
3212 .pa_start = 0x48024000,
3213 .pa_end = 0x48024000 + SZ_8K - 1,
3214 .flags = ADDR_TYPE_RT,
3215 },
3216 { }
3217 };
3218
3219 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
3220 .master = &am33xx_l4_ls_hwmod,
3221 .slave = &am33xx_uart3_hwmod,
3222 .clk = "l4ls_gclk",
3223 .addr = am33xx_uart3_addr_space,
3224 .user = OCP_USER_MPU,
3225 };
3226
3227 /* l4 ls -> uart4 */
3228 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
3229 {
3230 .pa_start = 0x481A6000,
3231 .pa_end = 0x481A6000 + SZ_8K - 1,
3232 .flags = ADDR_TYPE_RT,
3233 },
3234 { }
3235 };
3236
3237 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
3238 .master = &am33xx_l4_ls_hwmod,
3239 .slave = &am33xx_uart4_hwmod,
3240 .clk = "l4ls_gclk",
3241 .addr = am33xx_uart4_addr_space,
3242 .user = OCP_USER_MPU,
3243 };
3244
3245 /* l4 ls -> uart5 */
3246 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
3247 {
3248 .pa_start = 0x481A8000,
3249 .pa_end = 0x481A8000 + SZ_8K - 1,
3250 .flags = ADDR_TYPE_RT,
3251 },
3252 { }
3253 };
3254
3255 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
3256 .master = &am33xx_l4_ls_hwmod,
3257 .slave = &am33xx_uart5_hwmod,
3258 .clk = "l4ls_gclk",
3259 .addr = am33xx_uart5_addr_space,
3260 .user = OCP_USER_MPU,
3261 };
3262
3263 /* l4 ls -> uart6 */
3264 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
3265 {
3266 .pa_start = 0x481aa000,
3267 .pa_end = 0x481aa000 + SZ_8K - 1,
3268 .flags = ADDR_TYPE_RT,
3269 },
3270 { }
3271 };
3272
3273 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
3274 .master = &am33xx_l4_ls_hwmod,
3275 .slave = &am33xx_uart6_hwmod,
3276 .clk = "l4ls_gclk",
3277 .addr = am33xx_uart6_addr_space,
3278 .user = OCP_USER_MPU,
3279 };
3280
3281 /* l4 wkup -> wd_timer1 */
3282 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
3283 {
3284 .pa_start = 0x44e35000,
3285 .pa_end = 0x44e35000 + SZ_4K - 1,
3286 .flags = ADDR_TYPE_RT
3287 },
3288 { }
3289 };
3290
3291 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
3292 .master = &am33xx_l4_wkup_hwmod,
3293 .slave = &am33xx_wd_timer1_hwmod,
3294 .clk = "dpll_core_m4_div2_ck",
3295 .addr = am33xx_wd_timer1_addrs,
3296 .user = OCP_USER_MPU,
3297 };
3298
3299 /* usbss */
3300 /* l3 s -> USBSS interface */
3301 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
3302 {
3303 .name = "usbss",
3304 .pa_start = 0x47400000,
3305 .pa_end = 0x47400000 + SZ_4K - 1,
3306 .flags = ADDR_TYPE_RT
3307 },
3308 {
3309 .name = "musb0",
3310 .pa_start = 0x47401000,
3311 .pa_end = 0x47401000 + SZ_2K - 1,
3312 .flags = ADDR_TYPE_RT
3313 },
3314 {
3315 .name = "musb1",
3316 .pa_start = 0x47401800,
3317 .pa_end = 0x47401800 + SZ_2K - 1,
3318 .flags = ADDR_TYPE_RT
3319 },
3320 { }
3321 };
3322
3323 static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
3324 .master = &am33xx_l3_s_hwmod,
3325 .slave = &am33xx_usbss_hwmod,
3326 .clk = "l3s_gclk",
3327 .addr = am33xx_usbss_addr_space,
3328 .user = OCP_USER_MPU,
3329 .flags = OCPIF_SWSUP_IDLE,
3330 };
3331
3332 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3333 &am33xx_l4_fw__emif_fw,
3334 &am33xx_l3_main__emif,
3335 &am33xx_mpu__l3_main,
3336 &am33xx_mpu__prcm,
3337 &am33xx_l3_s__l4_ls,
3338 &am33xx_l3_s__l4_wkup,
3339 &am33xx_l3_s__l4_fw,
3340 &am33xx_l3_main__l4_hs,
3341 &am33xx_l3_main__l3_s,
3342 &am33xx_l3_main__l3_instr,
3343 &am33xx_l3_main__gfx,
3344 &am33xx_l3_s__l3_main,
3345 &am33xx_pruss__l3_main,
3346 &am33xx_wkup_m3__l4_wkup,
3347 &am33xx_gfx__l3_main,
3348 &am33xx_l4_wkup__wkup_m3,
3349 &am33xx_l4_wkup__control,
3350 &am33xx_l4_wkup__smartreflex0,
3351 &am33xx_l4_wkup__smartreflex1,
3352 &am33xx_l4_wkup__uart1,
3353 &am33xx_l4_wkup__timer1,
3354 &am33xx_l4_wkup__rtc,
3355 &am33xx_l4_wkup__i2c1,
3356 &am33xx_l4_wkup__gpio0,
3357 &am33xx_l4_wkup__adc_tsc,
3358 &am33xx_l4_wkup__wd_timer1,
3359 &am33xx_l4_hs__pruss,
3360 &am33xx_l4_per__dcan0,
3361 &am33xx_l4_per__dcan1,
3362 &am33xx_l4_per__gpio1,
3363 &am33xx_l4_per__gpio2,
3364 &am33xx_l4_per__gpio3,
3365 &am33xx_l4_per__i2c2,
3366 &am33xx_l4_per__i2c3,
3367 &am33xx_l4_per__mailbox,
3368 &am33xx_l4_ls__mcasp0,
3369 &am33xx_l3_s__mcasp0_data,
3370 &am33xx_l4_ls__mcasp1,
3371 &am33xx_l3_s__mcasp1_data,
3372 &am33xx_l4_ls__mmc0,
3373 &am33xx_l4_ls__mmc1,
3374 &am33xx_l3_s__mmc2,
3375 &am33xx_l4_ls__timer2,
3376 &am33xx_l4_ls__timer3,
3377 &am33xx_l4_ls__timer4,
3378 &am33xx_l4_ls__timer5,
3379 &am33xx_l4_ls__timer6,
3380 &am33xx_l4_ls__timer7,
3381 &am33xx_l3_main__tpcc,
3382 &am33xx_l4_ls__uart2,
3383 &am33xx_l4_ls__uart3,
3384 &am33xx_l4_ls__uart4,
3385 &am33xx_l4_ls__uart5,
3386 &am33xx_l4_ls__uart6,
3387 &am33xx_l4_ls__spinlock,
3388 &am33xx_l4_ls__elm,
3389 &am33xx_l4_ls__ehrpwm0,
3390 &am33xx_l4_ls__ehrpwm1,
3391 &am33xx_l4_ls__ehrpwm2,
3392 &am33xx_l4_ls__ecap0,
3393 &am33xx_l4_ls__ecap1,
3394 &am33xx_l4_ls__ecap2,
3395 &am33xx_l3_s__gpmc,
3396 &am33xx_l3_main__lcdc,
3397 &am33xx_l4_ls__mcspi0,
3398 &am33xx_l4_ls__mcspi1,
3399 &am33xx_l3_main__tptc0,
3400 &am33xx_l3_main__tptc1,
3401 &am33xx_l3_main__tptc2,
3402 &am33xx_l3_s__usbss,
3403 &am33xx_l4_hs__cpgmac0,
3404 &am33xx_cpgmac0__mdio,
3405 NULL,
3406 };
3407
3408 int __init am33xx_hwmod_init(void)
3409 {
3410 omap_hwmod_init();
3411 return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);
3412 }
Linux kernel - Deliverables
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