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Merge git://git.kernel.org/pub/scm/linux/kernel/git/steve/gfs2-3.0-fixes
[deliverable/linux.git] / arch / arm / mach-omap2 / omap_hwmod_44xx_data.c
1 /*
2 * Hardware modules present on the OMAP44xx chips
3 *
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
6 *
7 * Paul Walmsley
8 * Benoit Cousson
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 * Note that this file is currently not in sync with autogeneration scripts.
16 * The above note to be removed, once it is synced up.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23 #include <linux/io.h>
24 #include <linux/platform_data/gpio-omap.h>
25 #include <linux/power/smartreflex.h>
26 #include <linux/i2c-omap.h>
27
28 #include <linux/omap-dma.h>
29
30 #include <linux/platform_data/spi-omap2-mcspi.h>
31 #include <linux/platform_data/asoc-ti-mcbsp.h>
32 #include <linux/platform_data/iommu-omap.h>
33 #include <plat/dmtimer.h>
34
35 #include "omap_hwmod.h"
36 #include "omap_hwmod_common_data.h"
37 #include "cm1_44xx.h"
38 #include "cm2_44xx.h"
39 #include "prm44xx.h"
40 #include "prm-regbits-44xx.h"
41 #include "i2c.h"
42 #include "mmc.h"
43 #include "wd_timer.h"
44
45 /* Base offset for all OMAP4 interrupts external to MPUSS */
46 #define OMAP44XX_IRQ_GIC_START 32
47
48 /* Base offset for all OMAP4 dma requests */
49 #define OMAP44XX_DMA_REQ_START 1
50
51 /*
52 * IP blocks
53 */
54
55 /*
56 * 'dmm' class
57 * instance(s): dmm
58 */
59 static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
60 .name = "dmm",
61 };
62
63 /* dmm */
64 static struct omap_hwmod omap44xx_dmm_hwmod = {
65 .name = "dmm",
66 .class = &omap44xx_dmm_hwmod_class,
67 .clkdm_name = "l3_emif_clkdm",
68 .prcm = {
69 .omap4 = {
70 .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
71 .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
72 },
73 },
74 };
75
76 /*
77 * 'l3' class
78 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
79 */
80 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
81 .name = "l3",
82 };
83
84 /* l3_instr */
85 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
86 .name = "l3_instr",
87 .class = &omap44xx_l3_hwmod_class,
88 .clkdm_name = "l3_instr_clkdm",
89 .prcm = {
90 .omap4 = {
91 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
92 .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
93 .modulemode = MODULEMODE_HWCTRL,
94 },
95 },
96 };
97
98 /* l3_main_1 */
99 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
100 .name = "l3_main_1",
101 .class = &omap44xx_l3_hwmod_class,
102 .clkdm_name = "l3_1_clkdm",
103 .prcm = {
104 .omap4 = {
105 .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
106 .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
107 },
108 },
109 };
110
111 /* l3_main_2 */
112 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
113 .name = "l3_main_2",
114 .class = &omap44xx_l3_hwmod_class,
115 .clkdm_name = "l3_2_clkdm",
116 .prcm = {
117 .omap4 = {
118 .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
119 .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
120 },
121 },
122 };
123
124 /* l3_main_3 */
125 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
126 .name = "l3_main_3",
127 .class = &omap44xx_l3_hwmod_class,
128 .clkdm_name = "l3_instr_clkdm",
129 .prcm = {
130 .omap4 = {
131 .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
132 .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
133 .modulemode = MODULEMODE_HWCTRL,
134 },
135 },
136 };
137
138 /*
139 * 'l4' class
140 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
141 */
142 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
143 .name = "l4",
144 };
145
146 /* l4_abe */
147 static struct omap_hwmod omap44xx_l4_abe_hwmod = {
148 .name = "l4_abe",
149 .class = &omap44xx_l4_hwmod_class,
150 .clkdm_name = "abe_clkdm",
151 .prcm = {
152 .omap4 = {
153 .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
154 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
155 .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
156 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
157 },
158 },
159 };
160
161 /* l4_cfg */
162 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
163 .name = "l4_cfg",
164 .class = &omap44xx_l4_hwmod_class,
165 .clkdm_name = "l4_cfg_clkdm",
166 .prcm = {
167 .omap4 = {
168 .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
169 .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
170 },
171 },
172 };
173
174 /* l4_per */
175 static struct omap_hwmod omap44xx_l4_per_hwmod = {
176 .name = "l4_per",
177 .class = &omap44xx_l4_hwmod_class,
178 .clkdm_name = "l4_per_clkdm",
179 .prcm = {
180 .omap4 = {
181 .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
182 .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
183 },
184 },
185 };
186
187 /* l4_wkup */
188 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
189 .name = "l4_wkup",
190 .class = &omap44xx_l4_hwmod_class,
191 .clkdm_name = "l4_wkup_clkdm",
192 .prcm = {
193 .omap4 = {
194 .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
195 .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
196 },
197 },
198 };
199
200 /*
201 * 'mpu_bus' class
202 * instance(s): mpu_private
203 */
204 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
205 .name = "mpu_bus",
206 };
207
208 /* mpu_private */
209 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
210 .name = "mpu_private",
211 .class = &omap44xx_mpu_bus_hwmod_class,
212 .clkdm_name = "mpuss_clkdm",
213 .prcm = {
214 .omap4 = {
215 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
216 },
217 },
218 };
219
220 /*
221 * 'ocp_wp_noc' class
222 * instance(s): ocp_wp_noc
223 */
224 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
225 .name = "ocp_wp_noc",
226 };
227
228 /* ocp_wp_noc */
229 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
230 .name = "ocp_wp_noc",
231 .class = &omap44xx_ocp_wp_noc_hwmod_class,
232 .clkdm_name = "l3_instr_clkdm",
233 .prcm = {
234 .omap4 = {
235 .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
236 .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
237 .modulemode = MODULEMODE_HWCTRL,
238 },
239 },
240 };
241
242 /*
243 * Modules omap_hwmod structures
244 *
245 * The following IPs are excluded for the moment because:
246 * - They do not need an explicit SW control using omap_hwmod API.
247 * - They still need to be validated with the driver
248 * properly adapted to omap_hwmod / omap_device
249 *
250 * usim
251 */
252
253 /*
254 * 'aess' class
255 * audio engine sub system
256 */
257
258 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
259 .rev_offs = 0x0000,
260 .sysc_offs = 0x0010,
261 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
262 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
263 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
264 MSTANDBY_SMART_WKUP),
265 .sysc_fields = &omap_hwmod_sysc_type2,
266 };
267
268 static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
269 .name = "aess",
270 .sysc = &omap44xx_aess_sysc,
271 .enable_preprogram = omap_hwmod_aess_preprogram,
272 };
273
274 /* aess */
275 static struct omap_hwmod omap44xx_aess_hwmod = {
276 .name = "aess",
277 .class = &omap44xx_aess_hwmod_class,
278 .clkdm_name = "abe_clkdm",
279 .main_clk = "aess_fclk",
280 .prcm = {
281 .omap4 = {
282 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
283 .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
284 .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
285 .modulemode = MODULEMODE_SWCTRL,
286 },
287 },
288 };
289
290 /*
291 * 'c2c' class
292 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
293 * soc
294 */
295
296 static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
297 .name = "c2c",
298 };
299
300 /* c2c */
301 static struct omap_hwmod omap44xx_c2c_hwmod = {
302 .name = "c2c",
303 .class = &omap44xx_c2c_hwmod_class,
304 .clkdm_name = "d2d_clkdm",
305 .prcm = {
306 .omap4 = {
307 .clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
308 .context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
309 },
310 },
311 };
312
313 /*
314 * 'counter' class
315 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
316 */
317
318 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
319 .rev_offs = 0x0000,
320 .sysc_offs = 0x0004,
321 .sysc_flags = SYSC_HAS_SIDLEMODE,
322 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
323 .sysc_fields = &omap_hwmod_sysc_type1,
324 };
325
326 static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
327 .name = "counter",
328 .sysc = &omap44xx_counter_sysc,
329 };
330
331 /* counter_32k */
332 static struct omap_hwmod omap44xx_counter_32k_hwmod = {
333 .name = "counter_32k",
334 .class = &omap44xx_counter_hwmod_class,
335 .clkdm_name = "l4_wkup_clkdm",
336 .flags = HWMOD_SWSUP_SIDLE,
337 .main_clk = "sys_32k_ck",
338 .prcm = {
339 .omap4 = {
340 .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
341 .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
342 },
343 },
344 };
345
346 /*
347 * 'ctrl_module' class
348 * attila core control module + core pad control module + wkup pad control
349 * module + attila wkup control module
350 */
351
352 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
353 .rev_offs = 0x0000,
354 .sysc_offs = 0x0010,
355 .sysc_flags = SYSC_HAS_SIDLEMODE,
356 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
357 SIDLE_SMART_WKUP),
358 .sysc_fields = &omap_hwmod_sysc_type2,
359 };
360
361 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
362 .name = "ctrl_module",
363 .sysc = &omap44xx_ctrl_module_sysc,
364 };
365
366 /* ctrl_module_core */
367 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
368 .name = "ctrl_module_core",
369 .class = &omap44xx_ctrl_module_hwmod_class,
370 .clkdm_name = "l4_cfg_clkdm",
371 .prcm = {
372 .omap4 = {
373 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
374 },
375 },
376 };
377
378 /* ctrl_module_pad_core */
379 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
380 .name = "ctrl_module_pad_core",
381 .class = &omap44xx_ctrl_module_hwmod_class,
382 .clkdm_name = "l4_cfg_clkdm",
383 .prcm = {
384 .omap4 = {
385 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
386 },
387 },
388 };
389
390 /* ctrl_module_wkup */
391 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
392 .name = "ctrl_module_wkup",
393 .class = &omap44xx_ctrl_module_hwmod_class,
394 .clkdm_name = "l4_wkup_clkdm",
395 .prcm = {
396 .omap4 = {
397 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
398 },
399 },
400 };
401
402 /* ctrl_module_pad_wkup */
403 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
404 .name = "ctrl_module_pad_wkup",
405 .class = &omap44xx_ctrl_module_hwmod_class,
406 .clkdm_name = "l4_wkup_clkdm",
407 .prcm = {
408 .omap4 = {
409 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
410 },
411 },
412 };
413
414 /*
415 * 'debugss' class
416 * debug and emulation sub system
417 */
418
419 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
420 .name = "debugss",
421 };
422
423 /* debugss */
424 static struct omap_hwmod omap44xx_debugss_hwmod = {
425 .name = "debugss",
426 .class = &omap44xx_debugss_hwmod_class,
427 .clkdm_name = "emu_sys_clkdm",
428 .main_clk = "trace_clk_div_ck",
429 .prcm = {
430 .omap4 = {
431 .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
432 .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
433 },
434 },
435 };
436
437 /*
438 * 'dma' class
439 * dma controller for data exchange between memory to memory (i.e. internal or
440 * external memory) and gp peripherals to memory or memory to gp peripherals
441 */
442
443 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
444 .rev_offs = 0x0000,
445 .sysc_offs = 0x002c,
446 .syss_offs = 0x0028,
447 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
448 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
449 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
450 SYSS_HAS_RESET_STATUS),
451 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
452 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
453 .sysc_fields = &omap_hwmod_sysc_type1,
454 };
455
456 static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
457 .name = "dma",
458 .sysc = &omap44xx_dma_sysc,
459 };
460
461 /* dma dev_attr */
462 static struct omap_dma_dev_attr dma_dev_attr = {
463 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
464 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
465 .lch_count = 32,
466 };
467
468 /* dma_system */
469 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
470 { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
471 { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
472 { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
473 { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
474 { .irq = -1 }
475 };
476
477 static struct omap_hwmod omap44xx_dma_system_hwmod = {
478 .name = "dma_system",
479 .class = &omap44xx_dma_hwmod_class,
480 .clkdm_name = "l3_dma_clkdm",
481 .mpu_irqs = omap44xx_dma_system_irqs,
482 .main_clk = "l3_div_ck",
483 .prcm = {
484 .omap4 = {
485 .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
486 .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
487 },
488 },
489 .dev_attr = &dma_dev_attr,
490 };
491
492 /*
493 * 'dmic' class
494 * digital microphone controller
495 */
496
497 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
498 .rev_offs = 0x0000,
499 .sysc_offs = 0x0010,
500 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
501 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
502 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
503 SIDLE_SMART_WKUP),
504 .sysc_fields = &omap_hwmod_sysc_type2,
505 };
506
507 static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
508 .name = "dmic",
509 .sysc = &omap44xx_dmic_sysc,
510 };
511
512 /* dmic */
513 static struct omap_hwmod omap44xx_dmic_hwmod = {
514 .name = "dmic",
515 .class = &omap44xx_dmic_hwmod_class,
516 .clkdm_name = "abe_clkdm",
517 .main_clk = "func_dmic_abe_gfclk",
518 .prcm = {
519 .omap4 = {
520 .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
521 .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
522 .modulemode = MODULEMODE_SWCTRL,
523 },
524 },
525 };
526
527 /*
528 * 'dsp' class
529 * dsp sub-system
530 */
531
532 static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
533 .name = "dsp",
534 };
535
536 /* dsp */
537 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
538 { .name = "dsp", .rst_shift = 0 },
539 };
540
541 static struct omap_hwmod omap44xx_dsp_hwmod = {
542 .name = "dsp",
543 .class = &omap44xx_dsp_hwmod_class,
544 .clkdm_name = "tesla_clkdm",
545 .rst_lines = omap44xx_dsp_resets,
546 .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
547 .main_clk = "dpll_iva_m4x2_ck",
548 .prcm = {
549 .omap4 = {
550 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
551 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
552 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
553 .modulemode = MODULEMODE_HWCTRL,
554 },
555 },
556 };
557
558 /*
559 * 'dss' class
560 * display sub-system
561 */
562
563 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
564 .rev_offs = 0x0000,
565 .syss_offs = 0x0014,
566 .sysc_flags = SYSS_HAS_RESET_STATUS,
567 };
568
569 static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
570 .name = "dss",
571 .sysc = &omap44xx_dss_sysc,
572 .reset = omap_dss_reset,
573 };
574
575 /* dss */
576 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
577 { .role = "sys_clk", .clk = "dss_sys_clk" },
578 { .role = "tv_clk", .clk = "dss_tv_clk" },
579 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
580 };
581
582 static struct omap_hwmod omap44xx_dss_hwmod = {
583 .name = "dss_core",
584 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
585 .class = &omap44xx_dss_hwmod_class,
586 .clkdm_name = "l3_dss_clkdm",
587 .main_clk = "dss_dss_clk",
588 .prcm = {
589 .omap4 = {
590 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
591 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
592 },
593 },
594 .opt_clks = dss_opt_clks,
595 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
596 };
597
598 /*
599 * 'dispc' class
600 * display controller
601 */
602
603 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
604 .rev_offs = 0x0000,
605 .sysc_offs = 0x0010,
606 .syss_offs = 0x0014,
607 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
608 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
609 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
610 SYSS_HAS_RESET_STATUS),
611 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
612 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
613 .sysc_fields = &omap_hwmod_sysc_type1,
614 };
615
616 static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
617 .name = "dispc",
618 .sysc = &omap44xx_dispc_sysc,
619 };
620
621 /* dss_dispc */
622 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
623 { .irq = 25 + OMAP44XX_IRQ_GIC_START },
624 { .irq = -1 }
625 };
626
627 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
628 { .dma_req = 5 + OMAP44XX_DMA_REQ_START },
629 { .dma_req = -1 }
630 };
631
632 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
633 .manager_count = 3,
634 .has_framedonetv_irq = 1
635 };
636
637 static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
638 .name = "dss_dispc",
639 .class = &omap44xx_dispc_hwmod_class,
640 .clkdm_name = "l3_dss_clkdm",
641 .mpu_irqs = omap44xx_dss_dispc_irqs,
642 .sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
643 .main_clk = "dss_dss_clk",
644 .prcm = {
645 .omap4 = {
646 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
647 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
648 },
649 },
650 .dev_attr = &omap44xx_dss_dispc_dev_attr
651 };
652
653 /*
654 * 'dsi' class
655 * display serial interface controller
656 */
657
658 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
659 .rev_offs = 0x0000,
660 .sysc_offs = 0x0010,
661 .syss_offs = 0x0014,
662 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
663 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
664 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
665 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
666 .sysc_fields = &omap_hwmod_sysc_type1,
667 };
668
669 static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
670 .name = "dsi",
671 .sysc = &omap44xx_dsi_sysc,
672 };
673
674 /* dss_dsi1 */
675 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
676 { .irq = 53 + OMAP44XX_IRQ_GIC_START },
677 { .irq = -1 }
678 };
679
680 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
681 { .dma_req = 74 + OMAP44XX_DMA_REQ_START },
682 { .dma_req = -1 }
683 };
684
685 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
686 { .role = "sys_clk", .clk = "dss_sys_clk" },
687 };
688
689 static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
690 .name = "dss_dsi1",
691 .class = &omap44xx_dsi_hwmod_class,
692 .clkdm_name = "l3_dss_clkdm",
693 .mpu_irqs = omap44xx_dss_dsi1_irqs,
694 .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
695 .main_clk = "dss_dss_clk",
696 .prcm = {
697 .omap4 = {
698 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
699 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
700 },
701 },
702 .opt_clks = dss_dsi1_opt_clks,
703 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
704 };
705
706 /* dss_dsi2 */
707 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
708 { .irq = 84 + OMAP44XX_IRQ_GIC_START },
709 { .irq = -1 }
710 };
711
712 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
713 { .dma_req = 83 + OMAP44XX_DMA_REQ_START },
714 { .dma_req = -1 }
715 };
716
717 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
718 { .role = "sys_clk", .clk = "dss_sys_clk" },
719 };
720
721 static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
722 .name = "dss_dsi2",
723 .class = &omap44xx_dsi_hwmod_class,
724 .clkdm_name = "l3_dss_clkdm",
725 .mpu_irqs = omap44xx_dss_dsi2_irqs,
726 .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
727 .main_clk = "dss_dss_clk",
728 .prcm = {
729 .omap4 = {
730 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
731 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
732 },
733 },
734 .opt_clks = dss_dsi2_opt_clks,
735 .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
736 };
737
738 /*
739 * 'hdmi' class
740 * hdmi controller
741 */
742
743 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
744 .rev_offs = 0x0000,
745 .sysc_offs = 0x0010,
746 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
747 SYSC_HAS_SOFTRESET),
748 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
749 SIDLE_SMART_WKUP),
750 .sysc_fields = &omap_hwmod_sysc_type2,
751 };
752
753 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
754 .name = "hdmi",
755 .sysc = &omap44xx_hdmi_sysc,
756 };
757
758 /* dss_hdmi */
759 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
760 { .irq = 101 + OMAP44XX_IRQ_GIC_START },
761 { .irq = -1 }
762 };
763
764 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
765 { .dma_req = 75 + OMAP44XX_DMA_REQ_START },
766 { .dma_req = -1 }
767 };
768
769 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
770 { .role = "sys_clk", .clk = "dss_sys_clk" },
771 };
772
773 static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
774 .name = "dss_hdmi",
775 .class = &omap44xx_hdmi_hwmod_class,
776 .clkdm_name = "l3_dss_clkdm",
777 /*
778 * HDMI audio requires to use no-idle mode. Hence,
779 * set idle mode by software.
780 */
781 .flags = HWMOD_SWSUP_SIDLE,
782 .mpu_irqs = omap44xx_dss_hdmi_irqs,
783 .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
784 .main_clk = "dss_48mhz_clk",
785 .prcm = {
786 .omap4 = {
787 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
788 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
789 },
790 },
791 .opt_clks = dss_hdmi_opt_clks,
792 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
793 };
794
795 /*
796 * 'rfbi' class
797 * remote frame buffer interface
798 */
799
800 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
801 .rev_offs = 0x0000,
802 .sysc_offs = 0x0010,
803 .syss_offs = 0x0014,
804 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
805 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
806 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
807 .sysc_fields = &omap_hwmod_sysc_type1,
808 };
809
810 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
811 .name = "rfbi",
812 .sysc = &omap44xx_rfbi_sysc,
813 };
814
815 /* dss_rfbi */
816 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
817 { .dma_req = 13 + OMAP44XX_DMA_REQ_START },
818 { .dma_req = -1 }
819 };
820
821 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
822 { .role = "ick", .clk = "dss_fck" },
823 };
824
825 static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
826 .name = "dss_rfbi",
827 .class = &omap44xx_rfbi_hwmod_class,
828 .clkdm_name = "l3_dss_clkdm",
829 .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
830 .main_clk = "dss_dss_clk",
831 .prcm = {
832 .omap4 = {
833 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
834 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
835 },
836 },
837 .opt_clks = dss_rfbi_opt_clks,
838 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
839 };
840
841 /*
842 * 'venc' class
843 * video encoder
844 */
845
846 static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
847 .name = "venc",
848 };
849
850 /* dss_venc */
851 static struct omap_hwmod omap44xx_dss_venc_hwmod = {
852 .name = "dss_venc",
853 .class = &omap44xx_venc_hwmod_class,
854 .clkdm_name = "l3_dss_clkdm",
855 .main_clk = "dss_tv_clk",
856 .prcm = {
857 .omap4 = {
858 .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
859 .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
860 },
861 },
862 };
863
864 /*
865 * 'elm' class
866 * bch error location module
867 */
868
869 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
870 .rev_offs = 0x0000,
871 .sysc_offs = 0x0010,
872 .syss_offs = 0x0014,
873 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
874 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
875 SYSS_HAS_RESET_STATUS),
876 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
877 .sysc_fields = &omap_hwmod_sysc_type1,
878 };
879
880 static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
881 .name = "elm",
882 .sysc = &omap44xx_elm_sysc,
883 };
884
885 /* elm */
886 static struct omap_hwmod omap44xx_elm_hwmod = {
887 .name = "elm",
888 .class = &omap44xx_elm_hwmod_class,
889 .clkdm_name = "l4_per_clkdm",
890 .prcm = {
891 .omap4 = {
892 .clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
893 .context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
894 },
895 },
896 };
897
898 /*
899 * 'emif' class
900 * external memory interface no1
901 */
902
903 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
904 .rev_offs = 0x0000,
905 };
906
907 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
908 .name = "emif",
909 .sysc = &omap44xx_emif_sysc,
910 };
911
912 /* emif1 */
913 static struct omap_hwmod omap44xx_emif1_hwmod = {
914 .name = "emif1",
915 .class = &omap44xx_emif_hwmod_class,
916 .clkdm_name = "l3_emif_clkdm",
917 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
918 .main_clk = "ddrphy_ck",
919 .prcm = {
920 .omap4 = {
921 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
922 .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
923 .modulemode = MODULEMODE_HWCTRL,
924 },
925 },
926 };
927
928 /* emif2 */
929 static struct omap_hwmod omap44xx_emif2_hwmod = {
930 .name = "emif2",
931 .class = &omap44xx_emif_hwmod_class,
932 .clkdm_name = "l3_emif_clkdm",
933 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
934 .main_clk = "ddrphy_ck",
935 .prcm = {
936 .omap4 = {
937 .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
938 .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
939 .modulemode = MODULEMODE_HWCTRL,
940 },
941 },
942 };
943
944 /*
945 * 'fdif' class
946 * face detection hw accelerator module
947 */
948
949 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
950 .rev_offs = 0x0000,
951 .sysc_offs = 0x0010,
952 /*
953 * FDIF needs 100 OCP clk cycles delay after a softreset before
954 * accessing sysconfig again.
955 * The lowest frequency at the moment for L3 bus is 100 MHz, so
956 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
957 *
958 * TODO: Indicate errata when available.
959 */
960 .srst_udelay = 2,
961 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
962 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
963 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
964 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
965 .sysc_fields = &omap_hwmod_sysc_type2,
966 };
967
968 static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
969 .name = "fdif",
970 .sysc = &omap44xx_fdif_sysc,
971 };
972
973 /* fdif */
974 static struct omap_hwmod omap44xx_fdif_hwmod = {
975 .name = "fdif",
976 .class = &omap44xx_fdif_hwmod_class,
977 .clkdm_name = "iss_clkdm",
978 .main_clk = "fdif_fck",
979 .prcm = {
980 .omap4 = {
981 .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
982 .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
983 .modulemode = MODULEMODE_SWCTRL,
984 },
985 },
986 };
987
988 /*
989 * 'gpio' class
990 * general purpose io module
991 */
992
993 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
994 .rev_offs = 0x0000,
995 .sysc_offs = 0x0010,
996 .syss_offs = 0x0114,
997 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
998 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
999 SYSS_HAS_RESET_STATUS),
1000 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1001 SIDLE_SMART_WKUP),
1002 .sysc_fields = &omap_hwmod_sysc_type1,
1003 };
1004
1005 static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1006 .name = "gpio",
1007 .sysc = &omap44xx_gpio_sysc,
1008 .rev = 2,
1009 };
1010
1011 /* gpio dev_attr */
1012 static struct omap_gpio_dev_attr gpio_dev_attr = {
1013 .bank_width = 32,
1014 .dbck_flag = true,
1015 };
1016
1017 /* gpio1 */
1018 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1019 { .role = "dbclk", .clk = "gpio1_dbclk" },
1020 };
1021
1022 static struct omap_hwmod omap44xx_gpio1_hwmod = {
1023 .name = "gpio1",
1024 .class = &omap44xx_gpio_hwmod_class,
1025 .clkdm_name = "l4_wkup_clkdm",
1026 .main_clk = "l4_wkup_clk_mux_ck",
1027 .prcm = {
1028 .omap4 = {
1029 .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1030 .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1031 .modulemode = MODULEMODE_HWCTRL,
1032 },
1033 },
1034 .opt_clks = gpio1_opt_clks,
1035 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1036 .dev_attr = &gpio_dev_attr,
1037 };
1038
1039 /* gpio2 */
1040 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1041 { .role = "dbclk", .clk = "gpio2_dbclk" },
1042 };
1043
1044 static struct omap_hwmod omap44xx_gpio2_hwmod = {
1045 .name = "gpio2",
1046 .class = &omap44xx_gpio_hwmod_class,
1047 .clkdm_name = "l4_per_clkdm",
1048 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1049 .main_clk = "l4_div_ck",
1050 .prcm = {
1051 .omap4 = {
1052 .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1053 .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1054 .modulemode = MODULEMODE_HWCTRL,
1055 },
1056 },
1057 .opt_clks = gpio2_opt_clks,
1058 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1059 .dev_attr = &gpio_dev_attr,
1060 };
1061
1062 /* gpio3 */
1063 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1064 { .role = "dbclk", .clk = "gpio3_dbclk" },
1065 };
1066
1067 static struct omap_hwmod omap44xx_gpio3_hwmod = {
1068 .name = "gpio3",
1069 .class = &omap44xx_gpio_hwmod_class,
1070 .clkdm_name = "l4_per_clkdm",
1071 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1072 .main_clk = "l4_div_ck",
1073 .prcm = {
1074 .omap4 = {
1075 .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1076 .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1077 .modulemode = MODULEMODE_HWCTRL,
1078 },
1079 },
1080 .opt_clks = gpio3_opt_clks,
1081 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1082 .dev_attr = &gpio_dev_attr,
1083 };
1084
1085 /* gpio4 */
1086 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1087 { .role = "dbclk", .clk = "gpio4_dbclk" },
1088 };
1089
1090 static struct omap_hwmod omap44xx_gpio4_hwmod = {
1091 .name = "gpio4",
1092 .class = &omap44xx_gpio_hwmod_class,
1093 .clkdm_name = "l4_per_clkdm",
1094 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1095 .main_clk = "l4_div_ck",
1096 .prcm = {
1097 .omap4 = {
1098 .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1099 .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1100 .modulemode = MODULEMODE_HWCTRL,
1101 },
1102 },
1103 .opt_clks = gpio4_opt_clks,
1104 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
1105 .dev_attr = &gpio_dev_attr,
1106 };
1107
1108 /* gpio5 */
1109 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1110 { .role = "dbclk", .clk = "gpio5_dbclk" },
1111 };
1112
1113 static struct omap_hwmod omap44xx_gpio5_hwmod = {
1114 .name = "gpio5",
1115 .class = &omap44xx_gpio_hwmod_class,
1116 .clkdm_name = "l4_per_clkdm",
1117 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1118 .main_clk = "l4_div_ck",
1119 .prcm = {
1120 .omap4 = {
1121 .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1122 .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1123 .modulemode = MODULEMODE_HWCTRL,
1124 },
1125 },
1126 .opt_clks = gpio5_opt_clks,
1127 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
1128 .dev_attr = &gpio_dev_attr,
1129 };
1130
1131 /* gpio6 */
1132 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1133 { .role = "dbclk", .clk = "gpio6_dbclk" },
1134 };
1135
1136 static struct omap_hwmod omap44xx_gpio6_hwmod = {
1137 .name = "gpio6",
1138 .class = &omap44xx_gpio_hwmod_class,
1139 .clkdm_name = "l4_per_clkdm",
1140 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1141 .main_clk = "l4_div_ck",
1142 .prcm = {
1143 .omap4 = {
1144 .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1145 .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1146 .modulemode = MODULEMODE_HWCTRL,
1147 },
1148 },
1149 .opt_clks = gpio6_opt_clks,
1150 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
1151 .dev_attr = &gpio_dev_attr,
1152 };
1153
1154 /*
1155 * 'gpmc' class
1156 * general purpose memory controller
1157 */
1158
1159 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1160 .rev_offs = 0x0000,
1161 .sysc_offs = 0x0010,
1162 .syss_offs = 0x0014,
1163 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1164 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1165 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1166 .sysc_fields = &omap_hwmod_sysc_type1,
1167 };
1168
1169 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1170 .name = "gpmc",
1171 .sysc = &omap44xx_gpmc_sysc,
1172 };
1173
1174 /* gpmc */
1175 static struct omap_hwmod omap44xx_gpmc_hwmod = {
1176 .name = "gpmc",
1177 .class = &omap44xx_gpmc_hwmod_class,
1178 .clkdm_name = "l3_2_clkdm",
1179 /*
1180 * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
1181 * block. It is not being added due to any known bugs with
1182 * resetting the GPMC IP block, but rather because any timings
1183 * set by the bootloader are not being correctly programmed by
1184 * the kernel from the board file or DT data.
1185 * HWMOD_INIT_NO_RESET should be removed ASAP.
1186 */
1187 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1188 .prcm = {
1189 .omap4 = {
1190 .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1191 .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1192 .modulemode = MODULEMODE_HWCTRL,
1193 },
1194 },
1195 };
1196
1197 /*
1198 * 'gpu' class
1199 * 2d/3d graphics accelerator
1200 */
1201
1202 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1203 .rev_offs = 0x1fc00,
1204 .sysc_offs = 0x1fc10,
1205 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1206 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1207 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1208 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1209 .sysc_fields = &omap_hwmod_sysc_type2,
1210 };
1211
1212 static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1213 .name = "gpu",
1214 .sysc = &omap44xx_gpu_sysc,
1215 };
1216
1217 /* gpu */
1218 static struct omap_hwmod omap44xx_gpu_hwmod = {
1219 .name = "gpu",
1220 .class = &omap44xx_gpu_hwmod_class,
1221 .clkdm_name = "l3_gfx_clkdm",
1222 .main_clk = "sgx_clk_mux",
1223 .prcm = {
1224 .omap4 = {
1225 .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1226 .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1227 .modulemode = MODULEMODE_SWCTRL,
1228 },
1229 },
1230 };
1231
1232 /*
1233 * 'hdq1w' class
1234 * hdq / 1-wire serial interface controller
1235 */
1236
1237 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1238 .rev_offs = 0x0000,
1239 .sysc_offs = 0x0014,
1240 .syss_offs = 0x0018,
1241 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1242 SYSS_HAS_RESET_STATUS),
1243 .sysc_fields = &omap_hwmod_sysc_type1,
1244 };
1245
1246 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1247 .name = "hdq1w",
1248 .sysc = &omap44xx_hdq1w_sysc,
1249 };
1250
1251 /* hdq1w */
1252 static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1253 .name = "hdq1w",
1254 .class = &omap44xx_hdq1w_hwmod_class,
1255 .clkdm_name = "l4_per_clkdm",
1256 .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */
1257 .main_clk = "func_12m_fclk",
1258 .prcm = {
1259 .omap4 = {
1260 .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1261 .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1262 .modulemode = MODULEMODE_SWCTRL,
1263 },
1264 },
1265 };
1266
1267 /*
1268 * 'hsi' class
1269 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1270 * serial if)
1271 */
1272
1273 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1274 .rev_offs = 0x0000,
1275 .sysc_offs = 0x0010,
1276 .syss_offs = 0x0014,
1277 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1278 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1279 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1280 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1281 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1282 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1283 .sysc_fields = &omap_hwmod_sysc_type1,
1284 };
1285
1286 static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1287 .name = "hsi",
1288 .sysc = &omap44xx_hsi_sysc,
1289 };
1290
1291 /* hsi */
1292 static struct omap_hwmod omap44xx_hsi_hwmod = {
1293 .name = "hsi",
1294 .class = &omap44xx_hsi_hwmod_class,
1295 .clkdm_name = "l3_init_clkdm",
1296 .main_clk = "hsi_fck",
1297 .prcm = {
1298 .omap4 = {
1299 .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1300 .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1301 .modulemode = MODULEMODE_HWCTRL,
1302 },
1303 },
1304 };
1305
1306 /*
1307 * 'i2c' class
1308 * multimaster high-speed i2c controller
1309 */
1310
1311 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1312 .sysc_offs = 0x0010,
1313 .syss_offs = 0x0090,
1314 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1315 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1316 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1317 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1318 SIDLE_SMART_WKUP),
1319 .clockact = CLOCKACT_TEST_ICLK,
1320 .sysc_fields = &omap_hwmod_sysc_type1,
1321 };
1322
1323 static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1324 .name = "i2c",
1325 .sysc = &omap44xx_i2c_sysc,
1326 .rev = OMAP_I2C_IP_VERSION_2,
1327 .reset = &omap_i2c_reset,
1328 };
1329
1330 static struct omap_i2c_dev_attr i2c_dev_attr = {
1331 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1332 };
1333
1334 /* i2c1 */
1335 static struct omap_hwmod omap44xx_i2c1_hwmod = {
1336 .name = "i2c1",
1337 .class = &omap44xx_i2c_hwmod_class,
1338 .clkdm_name = "l4_per_clkdm",
1339 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1340 .main_clk = "func_96m_fclk",
1341 .prcm = {
1342 .omap4 = {
1343 .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1344 .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1345 .modulemode = MODULEMODE_SWCTRL,
1346 },
1347 },
1348 .dev_attr = &i2c_dev_attr,
1349 };
1350
1351 /* i2c2 */
1352 static struct omap_hwmod omap44xx_i2c2_hwmod = {
1353 .name = "i2c2",
1354 .class = &omap44xx_i2c_hwmod_class,
1355 .clkdm_name = "l4_per_clkdm",
1356 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1357 .main_clk = "func_96m_fclk",
1358 .prcm = {
1359 .omap4 = {
1360 .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1361 .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1362 .modulemode = MODULEMODE_SWCTRL,
1363 },
1364 },
1365 .dev_attr = &i2c_dev_attr,
1366 };
1367
1368 /* i2c3 */
1369 static struct omap_hwmod omap44xx_i2c3_hwmod = {
1370 .name = "i2c3",
1371 .class = &omap44xx_i2c_hwmod_class,
1372 .clkdm_name = "l4_per_clkdm",
1373 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1374 .main_clk = "func_96m_fclk",
1375 .prcm = {
1376 .omap4 = {
1377 .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1378 .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1379 .modulemode = MODULEMODE_SWCTRL,
1380 },
1381 },
1382 .dev_attr = &i2c_dev_attr,
1383 };
1384
1385 /* i2c4 */
1386 static struct omap_hwmod omap44xx_i2c4_hwmod = {
1387 .name = "i2c4",
1388 .class = &omap44xx_i2c_hwmod_class,
1389 .clkdm_name = "l4_per_clkdm",
1390 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1391 .main_clk = "func_96m_fclk",
1392 .prcm = {
1393 .omap4 = {
1394 .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1395 .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1396 .modulemode = MODULEMODE_SWCTRL,
1397 },
1398 },
1399 .dev_attr = &i2c_dev_attr,
1400 };
1401
1402 /*
1403 * 'ipu' class
1404 * imaging processor unit
1405 */
1406
1407 static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1408 .name = "ipu",
1409 };
1410
1411 /* ipu */
1412 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1413 { .name = "cpu0", .rst_shift = 0 },
1414 { .name = "cpu1", .rst_shift = 1 },
1415 };
1416
1417 static struct omap_hwmod omap44xx_ipu_hwmod = {
1418 .name = "ipu",
1419 .class = &omap44xx_ipu_hwmod_class,
1420 .clkdm_name = "ducati_clkdm",
1421 .rst_lines = omap44xx_ipu_resets,
1422 .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
1423 .main_clk = "ducati_clk_mux_ck",
1424 .prcm = {
1425 .omap4 = {
1426 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1427 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1428 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1429 .modulemode = MODULEMODE_HWCTRL,
1430 },
1431 },
1432 };
1433
1434 /*
1435 * 'iss' class
1436 * external images sensor pixel data processor
1437 */
1438
1439 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1440 .rev_offs = 0x0000,
1441 .sysc_offs = 0x0010,
1442 /*
1443 * ISS needs 100 OCP clk cycles delay after a softreset before
1444 * accessing sysconfig again.
1445 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1446 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1447 *
1448 * TODO: Indicate errata when available.
1449 */
1450 .srst_udelay = 2,
1451 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1452 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1453 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1454 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1455 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1456 .sysc_fields = &omap_hwmod_sysc_type2,
1457 };
1458
1459 static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1460 .name = "iss",
1461 .sysc = &omap44xx_iss_sysc,
1462 };
1463
1464 /* iss */
1465 static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1466 { .role = "ctrlclk", .clk = "iss_ctrlclk" },
1467 };
1468
1469 static struct omap_hwmod omap44xx_iss_hwmod = {
1470 .name = "iss",
1471 .class = &omap44xx_iss_hwmod_class,
1472 .clkdm_name = "iss_clkdm",
1473 .main_clk = "ducati_clk_mux_ck",
1474 .prcm = {
1475 .omap4 = {
1476 .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1477 .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1478 .modulemode = MODULEMODE_SWCTRL,
1479 },
1480 },
1481 .opt_clks = iss_opt_clks,
1482 .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
1483 };
1484
1485 /*
1486 * 'iva' class
1487 * multi-standard video encoder/decoder hardware accelerator
1488 */
1489
1490 static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1491 .name = "iva",
1492 };
1493
1494 /* iva */
1495 static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1496 { .name = "seq0", .rst_shift = 0 },
1497 { .name = "seq1", .rst_shift = 1 },
1498 { .name = "logic", .rst_shift = 2 },
1499 };
1500
1501 static struct omap_hwmod omap44xx_iva_hwmod = {
1502 .name = "iva",
1503 .class = &omap44xx_iva_hwmod_class,
1504 .clkdm_name = "ivahd_clkdm",
1505 .rst_lines = omap44xx_iva_resets,
1506 .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
1507 .main_clk = "dpll_iva_m5x2_ck",
1508 .prcm = {
1509 .omap4 = {
1510 .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1511 .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1512 .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1513 .modulemode = MODULEMODE_HWCTRL,
1514 },
1515 },
1516 };
1517
1518 /*
1519 * 'kbd' class
1520 * keyboard controller
1521 */
1522
1523 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1524 .rev_offs = 0x0000,
1525 .sysc_offs = 0x0010,
1526 .syss_offs = 0x0014,
1527 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1528 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1529 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1530 SYSS_HAS_RESET_STATUS),
1531 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1532 .sysc_fields = &omap_hwmod_sysc_type1,
1533 };
1534
1535 static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1536 .name = "kbd",
1537 .sysc = &omap44xx_kbd_sysc,
1538 };
1539
1540 /* kbd */
1541 static struct omap_hwmod omap44xx_kbd_hwmod = {
1542 .name = "kbd",
1543 .class = &omap44xx_kbd_hwmod_class,
1544 .clkdm_name = "l4_wkup_clkdm",
1545 .main_clk = "sys_32k_ck",
1546 .prcm = {
1547 .omap4 = {
1548 .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1549 .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1550 .modulemode = MODULEMODE_SWCTRL,
1551 },
1552 },
1553 };
1554
1555 /*
1556 * 'mailbox' class
1557 * mailbox module allowing communication between the on-chip processors using a
1558 * queued mailbox-interrupt mechanism.
1559 */
1560
1561 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1562 .rev_offs = 0x0000,
1563 .sysc_offs = 0x0010,
1564 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1565 SYSC_HAS_SOFTRESET),
1566 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1567 .sysc_fields = &omap_hwmod_sysc_type2,
1568 };
1569
1570 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1571 .name = "mailbox",
1572 .sysc = &omap44xx_mailbox_sysc,
1573 };
1574
1575 /* mailbox */
1576 static struct omap_hwmod omap44xx_mailbox_hwmod = {
1577 .name = "mailbox",
1578 .class = &omap44xx_mailbox_hwmod_class,
1579 .clkdm_name = "l4_cfg_clkdm",
1580 .prcm = {
1581 .omap4 = {
1582 .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1583 .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1584 },
1585 },
1586 };
1587
1588 /*
1589 * 'mcasp' class
1590 * multi-channel audio serial port controller
1591 */
1592
1593 /* The IP is not compliant to type1 / type2 scheme */
1594 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp = {
1595 .sidle_shift = 0,
1596 };
1597
1598 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1599 .sysc_offs = 0x0004,
1600 .sysc_flags = SYSC_HAS_SIDLEMODE,
1601 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1602 SIDLE_SMART_WKUP),
1603 .sysc_fields = &omap_hwmod_sysc_type_mcasp,
1604 };
1605
1606 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1607 .name = "mcasp",
1608 .sysc = &omap44xx_mcasp_sysc,
1609 };
1610
1611 /* mcasp */
1612 static struct omap_hwmod omap44xx_mcasp_hwmod = {
1613 .name = "mcasp",
1614 .class = &omap44xx_mcasp_hwmod_class,
1615 .clkdm_name = "abe_clkdm",
1616 .main_clk = "func_mcasp_abe_gfclk",
1617 .prcm = {
1618 .omap4 = {
1619 .clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1620 .context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1621 .modulemode = MODULEMODE_SWCTRL,
1622 },
1623 },
1624 };
1625
1626 /*
1627 * 'mcbsp' class
1628 * multi channel buffered serial port controller
1629 */
1630
1631 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1632 .sysc_offs = 0x008c,
1633 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1634 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1635 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1636 .sysc_fields = &omap_hwmod_sysc_type1,
1637 };
1638
1639 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1640 .name = "mcbsp",
1641 .sysc = &omap44xx_mcbsp_sysc,
1642 .rev = MCBSP_CONFIG_TYPE4,
1643 };
1644
1645 /* mcbsp1 */
1646 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1647 { .role = "pad_fck", .clk = "pad_clks_ck" },
1648 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1649 };
1650
1651 static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1652 .name = "mcbsp1",
1653 .class = &omap44xx_mcbsp_hwmod_class,
1654 .clkdm_name = "abe_clkdm",
1655 .main_clk = "func_mcbsp1_gfclk",
1656 .prcm = {
1657 .omap4 = {
1658 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1659 .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1660 .modulemode = MODULEMODE_SWCTRL,
1661 },
1662 },
1663 .opt_clks = mcbsp1_opt_clks,
1664 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
1665 };
1666
1667 /* mcbsp2 */
1668 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1669 { .role = "pad_fck", .clk = "pad_clks_ck" },
1670 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1671 };
1672
1673 static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1674 .name = "mcbsp2",
1675 .class = &omap44xx_mcbsp_hwmod_class,
1676 .clkdm_name = "abe_clkdm",
1677 .main_clk = "func_mcbsp2_gfclk",
1678 .prcm = {
1679 .omap4 = {
1680 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1681 .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1682 .modulemode = MODULEMODE_SWCTRL,
1683 },
1684 },
1685 .opt_clks = mcbsp2_opt_clks,
1686 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
1687 };
1688
1689 /* mcbsp3 */
1690 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1691 { .role = "pad_fck", .clk = "pad_clks_ck" },
1692 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1693 };
1694
1695 static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
1696 .name = "mcbsp3",
1697 .class = &omap44xx_mcbsp_hwmod_class,
1698 .clkdm_name = "abe_clkdm",
1699 .main_clk = "func_mcbsp3_gfclk",
1700 .prcm = {
1701 .omap4 = {
1702 .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
1703 .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1704 .modulemode = MODULEMODE_SWCTRL,
1705 },
1706 },
1707 .opt_clks = mcbsp3_opt_clks,
1708 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
1709 };
1710
1711 /* mcbsp4 */
1712 static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
1713 { .role = "pad_fck", .clk = "pad_clks_ck" },
1714 { .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
1715 };
1716
1717 static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
1718 .name = "mcbsp4",
1719 .class = &omap44xx_mcbsp_hwmod_class,
1720 .clkdm_name = "l4_per_clkdm",
1721 .main_clk = "per_mcbsp4_gfclk",
1722 .prcm = {
1723 .omap4 = {
1724 .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
1725 .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
1726 .modulemode = MODULEMODE_SWCTRL,
1727 },
1728 },
1729 .opt_clks = mcbsp4_opt_clks,
1730 .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks),
1731 };
1732
1733 /*
1734 * 'mcpdm' class
1735 * multi channel pdm controller (proprietary interface with phoenix power
1736 * ic)
1737 */
1738
1739 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
1740 .rev_offs = 0x0000,
1741 .sysc_offs = 0x0010,
1742 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1743 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1744 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1745 SIDLE_SMART_WKUP),
1746 .sysc_fields = &omap_hwmod_sysc_type2,
1747 };
1748
1749 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
1750 .name = "mcpdm",
1751 .sysc = &omap44xx_mcpdm_sysc,
1752 };
1753
1754 /* mcpdm */
1755 static struct omap_hwmod omap44xx_mcpdm_hwmod = {
1756 .name = "mcpdm",
1757 .class = &omap44xx_mcpdm_hwmod_class,
1758 .clkdm_name = "abe_clkdm",
1759 /*
1760 * It's suspected that the McPDM requires an off-chip main
1761 * functional clock, controlled via I2C. This IP block is
1762 * currently reset very early during boot, before I2C is
1763 * available, so it doesn't seem that we have any choice in
1764 * the kernel other than to avoid resetting it.
1765 *
1766 * Also, McPDM needs to be configured to NO_IDLE mode when it
1767 * is in used otherwise vital clocks will be gated which
1768 * results 'slow motion' audio playback.
1769 */
1770 .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1771 .main_clk = "pad_clks_ck",
1772 .prcm = {
1773 .omap4 = {
1774 .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
1775 .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
1776 .modulemode = MODULEMODE_SWCTRL,
1777 },
1778 },
1779 };
1780
1781 /*
1782 * 'mcspi' class
1783 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1784 * bus
1785 */
1786
1787 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
1788 .rev_offs = 0x0000,
1789 .sysc_offs = 0x0010,
1790 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1791 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1792 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1793 SIDLE_SMART_WKUP),
1794 .sysc_fields = &omap_hwmod_sysc_type2,
1795 };
1796
1797 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
1798 .name = "mcspi",
1799 .sysc = &omap44xx_mcspi_sysc,
1800 .rev = OMAP4_MCSPI_REV,
1801 };
1802
1803 /* mcspi1 */
1804 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
1805 { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
1806 { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
1807 { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
1808 { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
1809 { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
1810 { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
1811 { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
1812 { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
1813 { .dma_req = -1 }
1814 };
1815
1816 /* mcspi1 dev_attr */
1817 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1818 .num_chipselect = 4,
1819 };
1820
1821 static struct omap_hwmod omap44xx_mcspi1_hwmod = {
1822 .name = "mcspi1",
1823 .class = &omap44xx_mcspi_hwmod_class,
1824 .clkdm_name = "l4_per_clkdm",
1825 .sdma_reqs = omap44xx_mcspi1_sdma_reqs,
1826 .main_clk = "func_48m_fclk",
1827 .prcm = {
1828 .omap4 = {
1829 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1830 .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1831 .modulemode = MODULEMODE_SWCTRL,
1832 },
1833 },
1834 .dev_attr = &mcspi1_dev_attr,
1835 };
1836
1837 /* mcspi2 */
1838 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
1839 { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
1840 { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
1841 { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
1842 { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
1843 { .dma_req = -1 }
1844 };
1845
1846 /* mcspi2 dev_attr */
1847 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1848 .num_chipselect = 2,
1849 };
1850
1851 static struct omap_hwmod omap44xx_mcspi2_hwmod = {
1852 .name = "mcspi2",
1853 .class = &omap44xx_mcspi_hwmod_class,
1854 .clkdm_name = "l4_per_clkdm",
1855 .sdma_reqs = omap44xx_mcspi2_sdma_reqs,
1856 .main_clk = "func_48m_fclk",
1857 .prcm = {
1858 .omap4 = {
1859 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1860 .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1861 .modulemode = MODULEMODE_SWCTRL,
1862 },
1863 },
1864 .dev_attr = &mcspi2_dev_attr,
1865 };
1866
1867 /* mcspi3 */
1868 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
1869 { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
1870 { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
1871 { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
1872 { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
1873 { .dma_req = -1 }
1874 };
1875
1876 /* mcspi3 dev_attr */
1877 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1878 .num_chipselect = 2,
1879 };
1880
1881 static struct omap_hwmod omap44xx_mcspi3_hwmod = {
1882 .name = "mcspi3",
1883 .class = &omap44xx_mcspi_hwmod_class,
1884 .clkdm_name = "l4_per_clkdm",
1885 .sdma_reqs = omap44xx_mcspi3_sdma_reqs,
1886 .main_clk = "func_48m_fclk",
1887 .prcm = {
1888 .omap4 = {
1889 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1890 .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1891 .modulemode = MODULEMODE_SWCTRL,
1892 },
1893 },
1894 .dev_attr = &mcspi3_dev_attr,
1895 };
1896
1897 /* mcspi4 */
1898 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
1899 { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
1900 { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
1901 { .dma_req = -1 }
1902 };
1903
1904 /* mcspi4 dev_attr */
1905 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1906 .num_chipselect = 1,
1907 };
1908
1909 static struct omap_hwmod omap44xx_mcspi4_hwmod = {
1910 .name = "mcspi4",
1911 .class = &omap44xx_mcspi_hwmod_class,
1912 .clkdm_name = "l4_per_clkdm",
1913 .sdma_reqs = omap44xx_mcspi4_sdma_reqs,
1914 .main_clk = "func_48m_fclk",
1915 .prcm = {
1916 .omap4 = {
1917 .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1918 .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1919 .modulemode = MODULEMODE_SWCTRL,
1920 },
1921 },
1922 .dev_attr = &mcspi4_dev_attr,
1923 };
1924
1925 /*
1926 * 'mmc' class
1927 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1928 */
1929
1930 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
1931 .rev_offs = 0x0000,
1932 .sysc_offs = 0x0010,
1933 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1934 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1935 SYSC_HAS_SOFTRESET),
1936 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1937 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1938 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1939 .sysc_fields = &omap_hwmod_sysc_type2,
1940 };
1941
1942 static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
1943 .name = "mmc",
1944 .sysc = &omap44xx_mmc_sysc,
1945 };
1946
1947 /* mmc1 */
1948 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
1949 { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
1950 { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
1951 { .dma_req = -1 }
1952 };
1953
1954 /* mmc1 dev_attr */
1955 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1956 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1957 };
1958
1959 static struct omap_hwmod omap44xx_mmc1_hwmod = {
1960 .name = "mmc1",
1961 .class = &omap44xx_mmc_hwmod_class,
1962 .clkdm_name = "l3_init_clkdm",
1963 .sdma_reqs = omap44xx_mmc1_sdma_reqs,
1964 .main_clk = "hsmmc1_fclk",
1965 .prcm = {
1966 .omap4 = {
1967 .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1968 .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1969 .modulemode = MODULEMODE_SWCTRL,
1970 },
1971 },
1972 .dev_attr = &mmc1_dev_attr,
1973 };
1974
1975 /* mmc2 */
1976 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
1977 { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
1978 { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
1979 { .dma_req = -1 }
1980 };
1981
1982 static struct omap_hwmod omap44xx_mmc2_hwmod = {
1983 .name = "mmc2",
1984 .class = &omap44xx_mmc_hwmod_class,
1985 .clkdm_name = "l3_init_clkdm",
1986 .sdma_reqs = omap44xx_mmc2_sdma_reqs,
1987 .main_clk = "hsmmc2_fclk",
1988 .prcm = {
1989 .omap4 = {
1990 .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1991 .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1992 .modulemode = MODULEMODE_SWCTRL,
1993 },
1994 },
1995 };
1996
1997 /* mmc3 */
1998 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
1999 { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
2000 { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
2001 { .dma_req = -1 }
2002 };
2003
2004 static struct omap_hwmod omap44xx_mmc3_hwmod = {
2005 .name = "mmc3",
2006 .class = &omap44xx_mmc_hwmod_class,
2007 .clkdm_name = "l4_per_clkdm",
2008 .sdma_reqs = omap44xx_mmc3_sdma_reqs,
2009 .main_clk = "func_48m_fclk",
2010 .prcm = {
2011 .omap4 = {
2012 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
2013 .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
2014 .modulemode = MODULEMODE_SWCTRL,
2015 },
2016 },
2017 };
2018
2019 /* mmc4 */
2020 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
2021 { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
2022 { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
2023 { .dma_req = -1 }
2024 };
2025
2026 static struct omap_hwmod omap44xx_mmc4_hwmod = {
2027 .name = "mmc4",
2028 .class = &omap44xx_mmc_hwmod_class,
2029 .clkdm_name = "l4_per_clkdm",
2030 .sdma_reqs = omap44xx_mmc4_sdma_reqs,
2031 .main_clk = "func_48m_fclk",
2032 .prcm = {
2033 .omap4 = {
2034 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
2035 .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
2036 .modulemode = MODULEMODE_SWCTRL,
2037 },
2038 },
2039 };
2040
2041 /* mmc5 */
2042 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
2043 { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
2044 { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
2045 { .dma_req = -1 }
2046 };
2047
2048 static struct omap_hwmod omap44xx_mmc5_hwmod = {
2049 .name = "mmc5",
2050 .class = &omap44xx_mmc_hwmod_class,
2051 .clkdm_name = "l4_per_clkdm",
2052 .sdma_reqs = omap44xx_mmc5_sdma_reqs,
2053 .main_clk = "func_48m_fclk",
2054 .prcm = {
2055 .omap4 = {
2056 .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
2057 .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
2058 .modulemode = MODULEMODE_SWCTRL,
2059 },
2060 },
2061 };
2062
2063 /*
2064 * 'mmu' class
2065 * The memory management unit performs virtual to physical address translation
2066 * for its requestors.
2067 */
2068
2069 static struct omap_hwmod_class_sysconfig mmu_sysc = {
2070 .rev_offs = 0x000,
2071 .sysc_offs = 0x010,
2072 .syss_offs = 0x014,
2073 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2074 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2075 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2076 .sysc_fields = &omap_hwmod_sysc_type1,
2077 };
2078
2079 static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2080 .name = "mmu",
2081 .sysc = &mmu_sysc,
2082 };
2083
2084 /* mmu ipu */
2085
2086 static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
2087 .da_start = 0x0,
2088 .da_end = 0xfffff000,
2089 .nr_tlb_entries = 32,
2090 };
2091
2092 static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2093 static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2094 { .name = "mmu_cache", .rst_shift = 2 },
2095 };
2096
2097 static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
2098 {
2099 .pa_start = 0x55082000,
2100 .pa_end = 0x550820ff,
2101 .flags = ADDR_TYPE_RT,
2102 },
2103 { }
2104 };
2105
2106 /* l3_main_2 -> mmu_ipu */
2107 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2108 .master = &omap44xx_l3_main_2_hwmod,
2109 .slave = &omap44xx_mmu_ipu_hwmod,
2110 .clk = "l3_div_ck",
2111 .addr = omap44xx_mmu_ipu_addrs,
2112 .user = OCP_USER_MPU | OCP_USER_SDMA,
2113 };
2114
2115 static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2116 .name = "mmu_ipu",
2117 .class = &omap44xx_mmu_hwmod_class,
2118 .clkdm_name = "ducati_clkdm",
2119 .rst_lines = omap44xx_mmu_ipu_resets,
2120 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2121 .main_clk = "ducati_clk_mux_ck",
2122 .prcm = {
2123 .omap4 = {
2124 .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2125 .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2126 .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2127 .modulemode = MODULEMODE_HWCTRL,
2128 },
2129 },
2130 .dev_attr = &mmu_ipu_dev_attr,
2131 };
2132
2133 /* mmu dsp */
2134
2135 static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
2136 .da_start = 0x0,
2137 .da_end = 0xfffff000,
2138 .nr_tlb_entries = 32,
2139 };
2140
2141 static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2142 static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2143 { .name = "mmu_cache", .rst_shift = 1 },
2144 };
2145
2146 static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
2147 {
2148 .pa_start = 0x4a066000,
2149 .pa_end = 0x4a0660ff,
2150 .flags = ADDR_TYPE_RT,
2151 },
2152 { }
2153 };
2154
2155 /* l4_cfg -> dsp */
2156 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2157 .master = &omap44xx_l4_cfg_hwmod,
2158 .slave = &omap44xx_mmu_dsp_hwmod,
2159 .clk = "l4_div_ck",
2160 .addr = omap44xx_mmu_dsp_addrs,
2161 .user = OCP_USER_MPU | OCP_USER_SDMA,
2162 };
2163
2164 static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2165 .name = "mmu_dsp",
2166 .class = &omap44xx_mmu_hwmod_class,
2167 .clkdm_name = "tesla_clkdm",
2168 .rst_lines = omap44xx_mmu_dsp_resets,
2169 .rst_lines_cnt = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2170 .main_clk = "dpll_iva_m4x2_ck",
2171 .prcm = {
2172 .omap4 = {
2173 .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2174 .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2175 .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2176 .modulemode = MODULEMODE_HWCTRL,
2177 },
2178 },
2179 .dev_attr = &mmu_dsp_dev_attr,
2180 };
2181
2182 /*
2183 * 'mpu' class
2184 * mpu sub-system
2185 */
2186
2187 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2188 .name = "mpu",
2189 };
2190
2191 /* mpu */
2192 static struct omap_hwmod omap44xx_mpu_hwmod = {
2193 .name = "mpu",
2194 .class = &omap44xx_mpu_hwmod_class,
2195 .clkdm_name = "mpuss_clkdm",
2196 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
2197 .main_clk = "dpll_mpu_m2_ck",
2198 .prcm = {
2199 .omap4 = {
2200 .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2201 .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2202 },
2203 },
2204 };
2205
2206 /*
2207 * 'ocmc_ram' class
2208 * top-level core on-chip ram
2209 */
2210
2211 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2212 .name = "ocmc_ram",
2213 };
2214
2215 /* ocmc_ram */
2216 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2217 .name = "ocmc_ram",
2218 .class = &omap44xx_ocmc_ram_hwmod_class,
2219 .clkdm_name = "l3_2_clkdm",
2220 .prcm = {
2221 .omap4 = {
2222 .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2223 .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2224 },
2225 },
2226 };
2227
2228 /*
2229 * 'ocp2scp' class
2230 * bridge to transform ocp interface protocol to scp (serial control port)
2231 * protocol
2232 */
2233
2234 static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2235 .rev_offs = 0x0000,
2236 .sysc_offs = 0x0010,
2237 .syss_offs = 0x0014,
2238 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2239 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2240 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2241 .sysc_fields = &omap_hwmod_sysc_type1,
2242 };
2243
2244 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2245 .name = "ocp2scp",
2246 .sysc = &omap44xx_ocp2scp_sysc,
2247 };
2248
2249 /* ocp2scp_usb_phy */
2250 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2251 .name = "ocp2scp_usb_phy",
2252 .class = &omap44xx_ocp2scp_hwmod_class,
2253 .clkdm_name = "l3_init_clkdm",
2254 /*
2255 * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
2256 * block as an "optional clock," and normally should never be
2257 * specified as the main_clk for an OMAP IP block. However it
2258 * turns out that this clock is actually the main clock for
2259 * the ocp2scp_usb_phy IP block:
2260 * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
2261 * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
2262 * to be the best workaround.
2263 */
2264 .main_clk = "ocp2scp_usb_phy_phy_48m",
2265 .prcm = {
2266 .omap4 = {
2267 .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2268 .context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2269 .modulemode = MODULEMODE_HWCTRL,
2270 },
2271 },
2272 };
2273
2274 /*
2275 * 'prcm' class
2276 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2277 * + clock manager 1 (in always on power domain) + local prm in mpu
2278 */
2279
2280 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2281 .name = "prcm",
2282 };
2283
2284 /* prcm_mpu */
2285 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2286 .name = "prcm_mpu",
2287 .class = &omap44xx_prcm_hwmod_class,
2288 .clkdm_name = "l4_wkup_clkdm",
2289 .flags = HWMOD_NO_IDLEST,
2290 .prcm = {
2291 .omap4 = {
2292 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2293 },
2294 },
2295 };
2296
2297 /* cm_core_aon */
2298 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2299 .name = "cm_core_aon",
2300 .class = &omap44xx_prcm_hwmod_class,
2301 .flags = HWMOD_NO_IDLEST,
2302 .prcm = {
2303 .omap4 = {
2304 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2305 },
2306 },
2307 };
2308
2309 /* cm_core */
2310 static struct omap_hwmod omap44xx_cm_core_hwmod = {
2311 .name = "cm_core",
2312 .class = &omap44xx_prcm_hwmod_class,
2313 .flags = HWMOD_NO_IDLEST,
2314 .prcm = {
2315 .omap4 = {
2316 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2317 },
2318 },
2319 };
2320
2321 /* prm */
2322 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2323 { .name = "rst_global_warm_sw", .rst_shift = 0 },
2324 { .name = "rst_global_cold_sw", .rst_shift = 1 },
2325 };
2326
2327 static struct omap_hwmod omap44xx_prm_hwmod = {
2328 .name = "prm",
2329 .class = &omap44xx_prcm_hwmod_class,
2330 .rst_lines = omap44xx_prm_resets,
2331 .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
2332 };
2333
2334 /*
2335 * 'scrm' class
2336 * system clock and reset manager
2337 */
2338
2339 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2340 .name = "scrm",
2341 };
2342
2343 /* scrm */
2344 static struct omap_hwmod omap44xx_scrm_hwmod = {
2345 .name = "scrm",
2346 .class = &omap44xx_scrm_hwmod_class,
2347 .clkdm_name = "l4_wkup_clkdm",
2348 .prcm = {
2349 .omap4 = {
2350 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2351 },
2352 },
2353 };
2354
2355 /*
2356 * 'sl2if' class
2357 * shared level 2 memory interface
2358 */
2359
2360 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2361 .name = "sl2if",
2362 };
2363
2364 /* sl2if */
2365 static struct omap_hwmod omap44xx_sl2if_hwmod = {
2366 .name = "sl2if",
2367 .class = &omap44xx_sl2if_hwmod_class,
2368 .clkdm_name = "ivahd_clkdm",
2369 .prcm = {
2370 .omap4 = {
2371 .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2372 .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2373 .modulemode = MODULEMODE_HWCTRL,
2374 },
2375 },
2376 };
2377
2378 /*
2379 * 'slimbus' class
2380 * bidirectional, multi-drop, multi-channel two-line serial interface between
2381 * the device and external components
2382 */
2383
2384 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2385 .rev_offs = 0x0000,
2386 .sysc_offs = 0x0010,
2387 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2388 SYSC_HAS_SOFTRESET),
2389 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2390 SIDLE_SMART_WKUP),
2391 .sysc_fields = &omap_hwmod_sysc_type2,
2392 };
2393
2394 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2395 .name = "slimbus",
2396 .sysc = &omap44xx_slimbus_sysc,
2397 };
2398
2399 /* slimbus1 */
2400 static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2401 { .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2402 { .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2403 { .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2404 { .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2405 };
2406
2407 static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2408 .name = "slimbus1",
2409 .class = &omap44xx_slimbus_hwmod_class,
2410 .clkdm_name = "abe_clkdm",
2411 .prcm = {
2412 .omap4 = {
2413 .clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2414 .context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2415 .modulemode = MODULEMODE_SWCTRL,
2416 },
2417 },
2418 .opt_clks = slimbus1_opt_clks,
2419 .opt_clks_cnt = ARRAY_SIZE(slimbus1_opt_clks),
2420 };
2421
2422 /* slimbus2 */
2423 static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2424 { .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2425 { .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2426 { .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2427 };
2428
2429 static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2430 .name = "slimbus2",
2431 .class = &omap44xx_slimbus_hwmod_class,
2432 .clkdm_name = "l4_per_clkdm",
2433 .prcm = {
2434 .omap4 = {
2435 .clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2436 .context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2437 .modulemode = MODULEMODE_SWCTRL,
2438 },
2439 },
2440 .opt_clks = slimbus2_opt_clks,
2441 .opt_clks_cnt = ARRAY_SIZE(slimbus2_opt_clks),
2442 };
2443
2444 /*
2445 * 'smartreflex' class
2446 * smartreflex module (monitor silicon performance and outputs a measure of
2447 * performance error)
2448 */
2449
2450 /* The IP is not compliant to type1 / type2 scheme */
2451 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2452 .sidle_shift = 24,
2453 .enwkup_shift = 26,
2454 };
2455
2456 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2457 .sysc_offs = 0x0038,
2458 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2459 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2460 SIDLE_SMART_WKUP),
2461 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2462 };
2463
2464 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2465 .name = "smartreflex",
2466 .sysc = &omap44xx_smartreflex_sysc,
2467 .rev = 2,
2468 };
2469
2470 /* smartreflex_core */
2471 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2472 .sensor_voltdm_name = "core",
2473 };
2474
2475 static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2476 .name = "smartreflex_core",
2477 .class = &omap44xx_smartreflex_hwmod_class,
2478 .clkdm_name = "l4_ao_clkdm",
2479
2480 .main_clk = "smartreflex_core_fck",
2481 .prcm = {
2482 .omap4 = {
2483 .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2484 .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2485 .modulemode = MODULEMODE_SWCTRL,
2486 },
2487 },
2488 .dev_attr = &smartreflex_core_dev_attr,
2489 };
2490
2491 /* smartreflex_iva */
2492 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2493 .sensor_voltdm_name = "iva",
2494 };
2495
2496 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2497 .name = "smartreflex_iva",
2498 .class = &omap44xx_smartreflex_hwmod_class,
2499 .clkdm_name = "l4_ao_clkdm",
2500 .main_clk = "smartreflex_iva_fck",
2501 .prcm = {
2502 .omap4 = {
2503 .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2504 .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2505 .modulemode = MODULEMODE_SWCTRL,
2506 },
2507 },
2508 .dev_attr = &smartreflex_iva_dev_attr,
2509 };
2510
2511 /* smartreflex_mpu */
2512 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2513 .sensor_voltdm_name = "mpu",
2514 };
2515
2516 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2517 .name = "smartreflex_mpu",
2518 .class = &omap44xx_smartreflex_hwmod_class,
2519 .clkdm_name = "l4_ao_clkdm",
2520 .main_clk = "smartreflex_mpu_fck",
2521 .prcm = {
2522 .omap4 = {
2523 .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2524 .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2525 .modulemode = MODULEMODE_SWCTRL,
2526 },
2527 },
2528 .dev_attr = &smartreflex_mpu_dev_attr,
2529 };
2530
2531 /*
2532 * 'spinlock' class
2533 * spinlock provides hardware assistance for synchronizing the processes
2534 * running on multiple processors
2535 */
2536
2537 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2538 .rev_offs = 0x0000,
2539 .sysc_offs = 0x0010,
2540 .syss_offs = 0x0014,
2541 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2542 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2543 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2544 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2545 SIDLE_SMART_WKUP),
2546 .sysc_fields = &omap_hwmod_sysc_type1,
2547 };
2548
2549 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2550 .name = "spinlock",
2551 .sysc = &omap44xx_spinlock_sysc,
2552 };
2553
2554 /* spinlock */
2555 static struct omap_hwmod omap44xx_spinlock_hwmod = {
2556 .name = "spinlock",
2557 .class = &omap44xx_spinlock_hwmod_class,
2558 .clkdm_name = "l4_cfg_clkdm",
2559 .prcm = {
2560 .omap4 = {
2561 .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2562 .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2563 },
2564 },
2565 };
2566
2567 /*
2568 * 'timer' class
2569 * general purpose timer module with accurate 1ms tick
2570 * This class contains several variants: ['timer_1ms', 'timer']
2571 */
2572
2573 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2574 .rev_offs = 0x0000,
2575 .sysc_offs = 0x0010,
2576 .syss_offs = 0x0014,
2577 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2578 SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2579 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2580 SYSS_HAS_RESET_STATUS),
2581 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2582 .clockact = CLOCKACT_TEST_ICLK,
2583 .sysc_fields = &omap_hwmod_sysc_type1,
2584 };
2585
2586 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2587 .name = "timer",
2588 .sysc = &omap44xx_timer_1ms_sysc,
2589 };
2590
2591 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2592 .rev_offs = 0x0000,
2593 .sysc_offs = 0x0010,
2594 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2595 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2596 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2597 SIDLE_SMART_WKUP),
2598 .sysc_fields = &omap_hwmod_sysc_type2,
2599 };
2600
2601 static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2602 .name = "timer",
2603 .sysc = &omap44xx_timer_sysc,
2604 };
2605
2606 /* always-on timers dev attribute */
2607 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
2608 .timer_capability = OMAP_TIMER_ALWON,
2609 };
2610
2611 /* pwm timers dev attribute */
2612 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
2613 .timer_capability = OMAP_TIMER_HAS_PWM,
2614 };
2615
2616 /* timers with DSP interrupt dev attribute */
2617 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
2618 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ,
2619 };
2620
2621 /* pwm timers with DSP interrupt dev attribute */
2622 static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
2623 .timer_capability = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
2624 };
2625
2626 /* timer1 */
2627 static struct omap_hwmod omap44xx_timer1_hwmod = {
2628 .name = "timer1",
2629 .class = &omap44xx_timer_1ms_hwmod_class,
2630 .clkdm_name = "l4_wkup_clkdm",
2631 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2632 .main_clk = "dmt1_clk_mux",
2633 .prcm = {
2634 .omap4 = {
2635 .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2636 .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2637 .modulemode = MODULEMODE_SWCTRL,
2638 },
2639 },
2640 .dev_attr = &capability_alwon_dev_attr,
2641 };
2642
2643 /* timer2 */
2644 static struct omap_hwmod omap44xx_timer2_hwmod = {
2645 .name = "timer2",
2646 .class = &omap44xx_timer_1ms_hwmod_class,
2647 .clkdm_name = "l4_per_clkdm",
2648 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2649 .main_clk = "cm2_dm2_mux",
2650 .prcm = {
2651 .omap4 = {
2652 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2653 .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2654 .modulemode = MODULEMODE_SWCTRL,
2655 },
2656 },
2657 };
2658
2659 /* timer3 */
2660 static struct omap_hwmod omap44xx_timer3_hwmod = {
2661 .name = "timer3",
2662 .class = &omap44xx_timer_hwmod_class,
2663 .clkdm_name = "l4_per_clkdm",
2664 .main_clk = "cm2_dm3_mux",
2665 .prcm = {
2666 .omap4 = {
2667 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2668 .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2669 .modulemode = MODULEMODE_SWCTRL,
2670 },
2671 },
2672 };
2673
2674 /* timer4 */
2675 static struct omap_hwmod omap44xx_timer4_hwmod = {
2676 .name = "timer4",
2677 .class = &omap44xx_timer_hwmod_class,
2678 .clkdm_name = "l4_per_clkdm",
2679 .main_clk = "cm2_dm4_mux",
2680 .prcm = {
2681 .omap4 = {
2682 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2683 .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2684 .modulemode = MODULEMODE_SWCTRL,
2685 },
2686 },
2687 };
2688
2689 /* timer5 */
2690 static struct omap_hwmod omap44xx_timer5_hwmod = {
2691 .name = "timer5",
2692 .class = &omap44xx_timer_hwmod_class,
2693 .clkdm_name = "abe_clkdm",
2694 .main_clk = "timer5_sync_mux",
2695 .prcm = {
2696 .omap4 = {
2697 .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
2698 .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
2699 .modulemode = MODULEMODE_SWCTRL,
2700 },
2701 },
2702 .dev_attr = &capability_dsp_dev_attr,
2703 };
2704
2705 /* timer6 */
2706 static struct omap_hwmod omap44xx_timer6_hwmod = {
2707 .name = "timer6",
2708 .class = &omap44xx_timer_hwmod_class,
2709 .clkdm_name = "abe_clkdm",
2710 .main_clk = "timer6_sync_mux",
2711 .prcm = {
2712 .omap4 = {
2713 .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
2714 .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
2715 .modulemode = MODULEMODE_SWCTRL,
2716 },
2717 },
2718 .dev_attr = &capability_dsp_dev_attr,
2719 };
2720
2721 /* timer7 */
2722 static struct omap_hwmod omap44xx_timer7_hwmod = {
2723 .name = "timer7",
2724 .class = &omap44xx_timer_hwmod_class,
2725 .clkdm_name = "abe_clkdm",
2726 .main_clk = "timer7_sync_mux",
2727 .prcm = {
2728 .omap4 = {
2729 .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
2730 .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
2731 .modulemode = MODULEMODE_SWCTRL,
2732 },
2733 },
2734 .dev_attr = &capability_dsp_dev_attr,
2735 };
2736
2737 /* timer8 */
2738 static struct omap_hwmod omap44xx_timer8_hwmod = {
2739 .name = "timer8",
2740 .class = &omap44xx_timer_hwmod_class,
2741 .clkdm_name = "abe_clkdm",
2742 .main_clk = "timer8_sync_mux",
2743 .prcm = {
2744 .omap4 = {
2745 .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
2746 .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
2747 .modulemode = MODULEMODE_SWCTRL,
2748 },
2749 },
2750 .dev_attr = &capability_dsp_pwm_dev_attr,
2751 };
2752
2753 /* timer9 */
2754 static struct omap_hwmod omap44xx_timer9_hwmod = {
2755 .name = "timer9",
2756 .class = &omap44xx_timer_hwmod_class,
2757 .clkdm_name = "l4_per_clkdm",
2758 .main_clk = "cm2_dm9_mux",
2759 .prcm = {
2760 .omap4 = {
2761 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
2762 .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
2763 .modulemode = MODULEMODE_SWCTRL,
2764 },
2765 },
2766 .dev_attr = &capability_pwm_dev_attr,
2767 };
2768
2769 /* timer10 */
2770 static struct omap_hwmod omap44xx_timer10_hwmod = {
2771 .name = "timer10",
2772 .class = &omap44xx_timer_1ms_hwmod_class,
2773 .clkdm_name = "l4_per_clkdm",
2774 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
2775 .main_clk = "cm2_dm10_mux",
2776 .prcm = {
2777 .omap4 = {
2778 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
2779 .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
2780 .modulemode = MODULEMODE_SWCTRL,
2781 },
2782 },
2783 .dev_attr = &capability_pwm_dev_attr,
2784 };
2785
2786 /* timer11 */
2787 static struct omap_hwmod omap44xx_timer11_hwmod = {
2788 .name = "timer11",
2789 .class = &omap44xx_timer_hwmod_class,
2790 .clkdm_name = "l4_per_clkdm",
2791 .main_clk = "cm2_dm11_mux",
2792 .prcm = {
2793 .omap4 = {
2794 .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
2795 .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
2796 .modulemode = MODULEMODE_SWCTRL,
2797 },
2798 },
2799 .dev_attr = &capability_pwm_dev_attr,
2800 };
2801
2802 /*
2803 * 'uart' class
2804 * universal asynchronous receiver/transmitter (uart)
2805 */
2806
2807 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
2808 .rev_offs = 0x0050,
2809 .sysc_offs = 0x0054,
2810 .syss_offs = 0x0058,
2811 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2812 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2813 SYSS_HAS_RESET_STATUS),
2814 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2815 SIDLE_SMART_WKUP),
2816 .sysc_fields = &omap_hwmod_sysc_type1,
2817 };
2818
2819 static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
2820 .name = "uart",
2821 .sysc = &omap44xx_uart_sysc,
2822 };
2823
2824 /* uart1 */
2825 static struct omap_hwmod omap44xx_uart1_hwmod = {
2826 .name = "uart1",
2827 .class = &omap44xx_uart_hwmod_class,
2828 .clkdm_name = "l4_per_clkdm",
2829 .flags = HWMOD_SWSUP_SIDLE_ACT,
2830 .main_clk = "func_48m_fclk",
2831 .prcm = {
2832 .omap4 = {
2833 .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
2834 .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
2835 .modulemode = MODULEMODE_SWCTRL,
2836 },
2837 },
2838 };
2839
2840 /* uart2 */
2841 static struct omap_hwmod omap44xx_uart2_hwmod = {
2842 .name = "uart2",
2843 .class = &omap44xx_uart_hwmod_class,
2844 .clkdm_name = "l4_per_clkdm",
2845 .flags = HWMOD_SWSUP_SIDLE_ACT,
2846 .main_clk = "func_48m_fclk",
2847 .prcm = {
2848 .omap4 = {
2849 .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
2850 .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
2851 .modulemode = MODULEMODE_SWCTRL,
2852 },
2853 },
2854 };
2855
2856 /* uart3 */
2857 static struct omap_hwmod omap44xx_uart3_hwmod = {
2858 .name = "uart3",
2859 .class = &omap44xx_uart_hwmod_class,
2860 .clkdm_name = "l4_per_clkdm",
2861 .flags = DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2862 .main_clk = "func_48m_fclk",
2863 .prcm = {
2864 .omap4 = {
2865 .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
2866 .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
2867 .modulemode = MODULEMODE_SWCTRL,
2868 },
2869 },
2870 };
2871
2872 /* uart4 */
2873 static struct omap_hwmod omap44xx_uart4_hwmod = {
2874 .name = "uart4",
2875 .class = &omap44xx_uart_hwmod_class,
2876 .clkdm_name = "l4_per_clkdm",
2877 .flags = DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2878 .main_clk = "func_48m_fclk",
2879 .prcm = {
2880 .omap4 = {
2881 .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
2882 .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
2883 .modulemode = MODULEMODE_SWCTRL,
2884 },
2885 },
2886 };
2887
2888 /*
2889 * 'usb_host_fs' class
2890 * full-speed usb host controller
2891 */
2892
2893 /* The IP is not compliant to type1 / type2 scheme */
2894 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs = {
2895 .midle_shift = 4,
2896 .sidle_shift = 2,
2897 .srst_shift = 1,
2898 };
2899
2900 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
2901 .rev_offs = 0x0000,
2902 .sysc_offs = 0x0210,
2903 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2904 SYSC_HAS_SOFTRESET),
2905 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2906 SIDLE_SMART_WKUP),
2907 .sysc_fields = &omap_hwmod_sysc_type_usb_host_fs,
2908 };
2909
2910 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
2911 .name = "usb_host_fs",
2912 .sysc = &omap44xx_usb_host_fs_sysc,
2913 };
2914
2915 /* usb_host_fs */
2916 static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
2917 .name = "usb_host_fs",
2918 .class = &omap44xx_usb_host_fs_hwmod_class,
2919 .clkdm_name = "l3_init_clkdm",
2920 .main_clk = "usb_host_fs_fck",
2921 .prcm = {
2922 .omap4 = {
2923 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
2924 .context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
2925 .modulemode = MODULEMODE_SWCTRL,
2926 },
2927 },
2928 };
2929
2930 /*
2931 * 'usb_host_hs' class
2932 * high-speed multi-port usb host controller
2933 */
2934
2935 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
2936 .rev_offs = 0x0000,
2937 .sysc_offs = 0x0010,
2938 .syss_offs = 0x0014,
2939 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2940 SYSC_HAS_SOFTRESET),
2941 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2942 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2943 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2944 .sysc_fields = &omap_hwmod_sysc_type2,
2945 };
2946
2947 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
2948 .name = "usb_host_hs",
2949 .sysc = &omap44xx_usb_host_hs_sysc,
2950 };
2951
2952 /* usb_host_hs */
2953 static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
2954 .name = "usb_host_hs",
2955 .class = &omap44xx_usb_host_hs_hwmod_class,
2956 .clkdm_name = "l3_init_clkdm",
2957 .main_clk = "usb_host_hs_fck",
2958 .prcm = {
2959 .omap4 = {
2960 .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
2961 .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
2962 .modulemode = MODULEMODE_SWCTRL,
2963 },
2964 },
2965
2966 /*
2967 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
2968 * id: i660
2969 *
2970 * Description:
2971 * In the following configuration :
2972 * - USBHOST module is set to smart-idle mode
2973 * - PRCM asserts idle_req to the USBHOST module ( This typically
2974 * happens when the system is going to a low power mode : all ports
2975 * have been suspended, the master part of the USBHOST module has
2976 * entered the standby state, and SW has cut the functional clocks)
2977 * - an USBHOST interrupt occurs before the module is able to answer
2978 * idle_ack, typically a remote wakeup IRQ.
2979 * Then the USB HOST module will enter a deadlock situation where it
2980 * is no more accessible nor functional.
2981 *
2982 * Workaround:
2983 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2984 */
2985
2986 /*
2987 * Errata: USB host EHCI may stall when entering smart-standby mode
2988 * Id: i571
2989 *
2990 * Description:
2991 * When the USBHOST module is set to smart-standby mode, and when it is
2992 * ready to enter the standby state (i.e. all ports are suspended and
2993 * all attached devices are in suspend mode), then it can wrongly assert
2994 * the Mstandby signal too early while there are still some residual OCP
2995 * transactions ongoing. If this condition occurs, the internal state
2996 * machine may go to an undefined state and the USB link may be stuck
2997 * upon the next resume.
2998 *
2999 * Workaround:
3000 * Don't use smart standby; use only force standby,
3001 * hence HWMOD_SWSUP_MSTANDBY
3002 */
3003
3004 /*
3005 * During system boot; If the hwmod framework resets the module
3006 * the module will have smart idle settings; which can lead to deadlock
3007 * (above Errata Id:i660); so, dont reset the module during boot;
3008 * Use HWMOD_INIT_NO_RESET.
3009 */
3010
3011 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
3012 HWMOD_INIT_NO_RESET,
3013 };
3014
3015 /*
3016 * 'usb_otg_hs' class
3017 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3018 */
3019
3020 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
3021 .rev_offs = 0x0400,
3022 .sysc_offs = 0x0404,
3023 .syss_offs = 0x0408,
3024 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
3025 SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
3026 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3027 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3028 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
3029 MSTANDBY_SMART),
3030 .sysc_fields = &omap_hwmod_sysc_type1,
3031 };
3032
3033 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
3034 .name = "usb_otg_hs",
3035 .sysc = &omap44xx_usb_otg_hs_sysc,
3036 };
3037
3038 /* usb_otg_hs */
3039 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
3040 { .role = "xclk", .clk = "usb_otg_hs_xclk" },
3041 };
3042
3043 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
3044 .name = "usb_otg_hs",
3045 .class = &omap44xx_usb_otg_hs_hwmod_class,
3046 .clkdm_name = "l3_init_clkdm",
3047 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
3048 .main_clk = "usb_otg_hs_ick",
3049 .prcm = {
3050 .omap4 = {
3051 .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
3052 .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
3053 .modulemode = MODULEMODE_HWCTRL,
3054 },
3055 },
3056 .opt_clks = usb_otg_hs_opt_clks,
3057 .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
3058 };
3059
3060 /*
3061 * 'usb_tll_hs' class
3062 * usb_tll_hs module is the adapter on the usb_host_hs ports
3063 */
3064
3065 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
3066 .rev_offs = 0x0000,
3067 .sysc_offs = 0x0010,
3068 .syss_offs = 0x0014,
3069 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3070 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3071 SYSC_HAS_AUTOIDLE),
3072 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3073 .sysc_fields = &omap_hwmod_sysc_type1,
3074 };
3075
3076 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
3077 .name = "usb_tll_hs",
3078 .sysc = &omap44xx_usb_tll_hs_sysc,
3079 };
3080
3081 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
3082 .name = "usb_tll_hs",
3083 .class = &omap44xx_usb_tll_hs_hwmod_class,
3084 .clkdm_name = "l3_init_clkdm",
3085 .main_clk = "usb_tll_hs_ick",
3086 .prcm = {
3087 .omap4 = {
3088 .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
3089 .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
3090 .modulemode = MODULEMODE_HWCTRL,
3091 },
3092 },
3093 };
3094
3095 /*
3096 * 'wd_timer' class
3097 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3098 * overflow condition
3099 */
3100
3101 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
3102 .rev_offs = 0x0000,
3103 .sysc_offs = 0x0010,
3104 .syss_offs = 0x0014,
3105 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
3106 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
3107 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
3108 SIDLE_SMART_WKUP),
3109 .sysc_fields = &omap_hwmod_sysc_type1,
3110 };
3111
3112 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
3113 .name = "wd_timer",
3114 .sysc = &omap44xx_wd_timer_sysc,
3115 .pre_shutdown = &omap2_wd_timer_disable,
3116 .reset = &omap2_wd_timer_reset,
3117 };
3118
3119 /* wd_timer2 */
3120 static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
3121 .name = "wd_timer2",
3122 .class = &omap44xx_wd_timer_hwmod_class,
3123 .clkdm_name = "l4_wkup_clkdm",
3124 .main_clk = "sys_32k_ck",
3125 .prcm = {
3126 .omap4 = {
3127 .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
3128 .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
3129 .modulemode = MODULEMODE_SWCTRL,
3130 },
3131 },
3132 };
3133
3134 /* wd_timer3 */
3135 static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
3136 .name = "wd_timer3",
3137 .class = &omap44xx_wd_timer_hwmod_class,
3138 .clkdm_name = "abe_clkdm",
3139 .main_clk = "sys_32k_ck",
3140 .prcm = {
3141 .omap4 = {
3142 .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3143 .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3144 .modulemode = MODULEMODE_SWCTRL,
3145 },
3146 },
3147 };
3148
3149
3150 /*
3151 * interfaces
3152 */
3153
3154 /* l3_main_1 -> dmm */
3155 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3156 .master = &omap44xx_l3_main_1_hwmod,
3157 .slave = &omap44xx_dmm_hwmod,
3158 .clk = "l3_div_ck",
3159 .user = OCP_USER_SDMA,
3160 };
3161
3162 /* mpu -> dmm */
3163 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3164 .master = &omap44xx_mpu_hwmod,
3165 .slave = &omap44xx_dmm_hwmod,
3166 .clk = "l3_div_ck",
3167 .user = OCP_USER_MPU,
3168 };
3169
3170 /* iva -> l3_instr */
3171 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3172 .master = &omap44xx_iva_hwmod,
3173 .slave = &omap44xx_l3_instr_hwmod,
3174 .clk = "l3_div_ck",
3175 .user = OCP_USER_MPU | OCP_USER_SDMA,
3176 };
3177
3178 /* l3_main_3 -> l3_instr */
3179 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3180 .master = &omap44xx_l3_main_3_hwmod,
3181 .slave = &omap44xx_l3_instr_hwmod,
3182 .clk = "l3_div_ck",
3183 .user = OCP_USER_MPU | OCP_USER_SDMA,
3184 };
3185
3186 /* ocp_wp_noc -> l3_instr */
3187 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3188 .master = &omap44xx_ocp_wp_noc_hwmod,
3189 .slave = &omap44xx_l3_instr_hwmod,
3190 .clk = "l3_div_ck",
3191 .user = OCP_USER_MPU | OCP_USER_SDMA,
3192 };
3193
3194 /* dsp -> l3_main_1 */
3195 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3196 .master = &omap44xx_dsp_hwmod,
3197 .slave = &omap44xx_l3_main_1_hwmod,
3198 .clk = "l3_div_ck",
3199 .user = OCP_USER_MPU | OCP_USER_SDMA,
3200 };
3201
3202 /* dss -> l3_main_1 */
3203 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3204 .master = &omap44xx_dss_hwmod,
3205 .slave = &omap44xx_l3_main_1_hwmod,
3206 .clk = "l3_div_ck",
3207 .user = OCP_USER_MPU | OCP_USER_SDMA,
3208 };
3209
3210 /* l3_main_2 -> l3_main_1 */
3211 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3212 .master = &omap44xx_l3_main_2_hwmod,
3213 .slave = &omap44xx_l3_main_1_hwmod,
3214 .clk = "l3_div_ck",
3215 .user = OCP_USER_MPU | OCP_USER_SDMA,
3216 };
3217
3218 /* l4_cfg -> l3_main_1 */
3219 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3220 .master = &omap44xx_l4_cfg_hwmod,
3221 .slave = &omap44xx_l3_main_1_hwmod,
3222 .clk = "l4_div_ck",
3223 .user = OCP_USER_MPU | OCP_USER_SDMA,
3224 };
3225
3226 /* mmc1 -> l3_main_1 */
3227 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3228 .master = &omap44xx_mmc1_hwmod,
3229 .slave = &omap44xx_l3_main_1_hwmod,
3230 .clk = "l3_div_ck",
3231 .user = OCP_USER_MPU | OCP_USER_SDMA,
3232 };
3233
3234 /* mmc2 -> l3_main_1 */
3235 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3236 .master = &omap44xx_mmc2_hwmod,
3237 .slave = &omap44xx_l3_main_1_hwmod,
3238 .clk = "l3_div_ck",
3239 .user = OCP_USER_MPU | OCP_USER_SDMA,
3240 };
3241
3242 /* mpu -> l3_main_1 */
3243 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3244 .master = &omap44xx_mpu_hwmod,
3245 .slave = &omap44xx_l3_main_1_hwmod,
3246 .clk = "l3_div_ck",
3247 .user = OCP_USER_MPU,
3248 };
3249
3250 /* debugss -> l3_main_2 */
3251 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3252 .master = &omap44xx_debugss_hwmod,
3253 .slave = &omap44xx_l3_main_2_hwmod,
3254 .clk = "dbgclk_mux_ck",
3255 .user = OCP_USER_MPU | OCP_USER_SDMA,
3256 };
3257
3258 /* dma_system -> l3_main_2 */
3259 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3260 .master = &omap44xx_dma_system_hwmod,
3261 .slave = &omap44xx_l3_main_2_hwmod,
3262 .clk = "l3_div_ck",
3263 .user = OCP_USER_MPU | OCP_USER_SDMA,
3264 };
3265
3266 /* fdif -> l3_main_2 */
3267 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3268 .master = &omap44xx_fdif_hwmod,
3269 .slave = &omap44xx_l3_main_2_hwmod,
3270 .clk = "l3_div_ck",
3271 .user = OCP_USER_MPU | OCP_USER_SDMA,
3272 };
3273
3274 /* gpu -> l3_main_2 */
3275 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3276 .master = &omap44xx_gpu_hwmod,
3277 .slave = &omap44xx_l3_main_2_hwmod,
3278 .clk = "l3_div_ck",
3279 .user = OCP_USER_MPU | OCP_USER_SDMA,
3280 };
3281
3282 /* hsi -> l3_main_2 */
3283 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3284 .master = &omap44xx_hsi_hwmod,
3285 .slave = &omap44xx_l3_main_2_hwmod,
3286 .clk = "l3_div_ck",
3287 .user = OCP_USER_MPU | OCP_USER_SDMA,
3288 };
3289
3290 /* ipu -> l3_main_2 */
3291 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3292 .master = &omap44xx_ipu_hwmod,
3293 .slave = &omap44xx_l3_main_2_hwmod,
3294 .clk = "l3_div_ck",
3295 .user = OCP_USER_MPU | OCP_USER_SDMA,
3296 };
3297
3298 /* iss -> l3_main_2 */
3299 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3300 .master = &omap44xx_iss_hwmod,
3301 .slave = &omap44xx_l3_main_2_hwmod,
3302 .clk = "l3_div_ck",
3303 .user = OCP_USER_MPU | OCP_USER_SDMA,
3304 };
3305
3306 /* iva -> l3_main_2 */
3307 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3308 .master = &omap44xx_iva_hwmod,
3309 .slave = &omap44xx_l3_main_2_hwmod,
3310 .clk = "l3_div_ck",
3311 .user = OCP_USER_MPU | OCP_USER_SDMA,
3312 };
3313
3314 /* l3_main_1 -> l3_main_2 */
3315 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3316 .master = &omap44xx_l3_main_1_hwmod,
3317 .slave = &omap44xx_l3_main_2_hwmod,
3318 .clk = "l3_div_ck",
3319 .user = OCP_USER_MPU,
3320 };
3321
3322 /* l4_cfg -> l3_main_2 */
3323 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3324 .master = &omap44xx_l4_cfg_hwmod,
3325 .slave = &omap44xx_l3_main_2_hwmod,
3326 .clk = "l4_div_ck",
3327 .user = OCP_USER_MPU | OCP_USER_SDMA,
3328 };
3329
3330 /* usb_host_fs -> l3_main_2 */
3331 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3332 .master = &omap44xx_usb_host_fs_hwmod,
3333 .slave = &omap44xx_l3_main_2_hwmod,
3334 .clk = "l3_div_ck",
3335 .user = OCP_USER_MPU | OCP_USER_SDMA,
3336 };
3337
3338 /* usb_host_hs -> l3_main_2 */
3339 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3340 .master = &omap44xx_usb_host_hs_hwmod,
3341 .slave = &omap44xx_l3_main_2_hwmod,
3342 .clk = "l3_div_ck",
3343 .user = OCP_USER_MPU | OCP_USER_SDMA,
3344 };
3345
3346 /* usb_otg_hs -> l3_main_2 */
3347 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3348 .master = &omap44xx_usb_otg_hs_hwmod,
3349 .slave = &omap44xx_l3_main_2_hwmod,
3350 .clk = "l3_div_ck",
3351 .user = OCP_USER_MPU | OCP_USER_SDMA,
3352 };
3353
3354 /* l3_main_1 -> l3_main_3 */
3355 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3356 .master = &omap44xx_l3_main_1_hwmod,
3357 .slave = &omap44xx_l3_main_3_hwmod,
3358 .clk = "l3_div_ck",
3359 .user = OCP_USER_MPU,
3360 };
3361
3362 /* l3_main_2 -> l3_main_3 */
3363 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3364 .master = &omap44xx_l3_main_2_hwmod,
3365 .slave = &omap44xx_l3_main_3_hwmod,
3366 .clk = "l3_div_ck",
3367 .user = OCP_USER_MPU | OCP_USER_SDMA,
3368 };
3369
3370 /* l4_cfg -> l3_main_3 */
3371 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3372 .master = &omap44xx_l4_cfg_hwmod,
3373 .slave = &omap44xx_l3_main_3_hwmod,
3374 .clk = "l4_div_ck",
3375 .user = OCP_USER_MPU | OCP_USER_SDMA,
3376 };
3377
3378 /* aess -> l4_abe */
3379 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3380 .master = &omap44xx_aess_hwmod,
3381 .slave = &omap44xx_l4_abe_hwmod,
3382 .clk = "ocp_abe_iclk",
3383 .user = OCP_USER_MPU | OCP_USER_SDMA,
3384 };
3385
3386 /* dsp -> l4_abe */
3387 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3388 .master = &omap44xx_dsp_hwmod,
3389 .slave = &omap44xx_l4_abe_hwmod,
3390 .clk = "ocp_abe_iclk",
3391 .user = OCP_USER_MPU | OCP_USER_SDMA,
3392 };
3393
3394 /* l3_main_1 -> l4_abe */
3395 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3396 .master = &omap44xx_l3_main_1_hwmod,
3397 .slave = &omap44xx_l4_abe_hwmod,
3398 .clk = "l3_div_ck",
3399 .user = OCP_USER_MPU | OCP_USER_SDMA,
3400 };
3401
3402 /* mpu -> l4_abe */
3403 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3404 .master = &omap44xx_mpu_hwmod,
3405 .slave = &omap44xx_l4_abe_hwmod,
3406 .clk = "ocp_abe_iclk",
3407 .user = OCP_USER_MPU | OCP_USER_SDMA,
3408 };
3409
3410 /* l3_main_1 -> l4_cfg */
3411 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3412 .master = &omap44xx_l3_main_1_hwmod,
3413 .slave = &omap44xx_l4_cfg_hwmod,
3414 .clk = "l3_div_ck",
3415 .user = OCP_USER_MPU | OCP_USER_SDMA,
3416 };
3417
3418 /* l3_main_2 -> l4_per */
3419 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3420 .master = &omap44xx_l3_main_2_hwmod,
3421 .slave = &omap44xx_l4_per_hwmod,
3422 .clk = "l3_div_ck",
3423 .user = OCP_USER_MPU | OCP_USER_SDMA,
3424 };
3425
3426 /* l4_cfg -> l4_wkup */
3427 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3428 .master = &omap44xx_l4_cfg_hwmod,
3429 .slave = &omap44xx_l4_wkup_hwmod,
3430 .clk = "l4_div_ck",
3431 .user = OCP_USER_MPU | OCP_USER_SDMA,
3432 };
3433
3434 /* mpu -> mpu_private */
3435 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3436 .master = &omap44xx_mpu_hwmod,
3437 .slave = &omap44xx_mpu_private_hwmod,
3438 .clk = "l3_div_ck",
3439 .user = OCP_USER_MPU | OCP_USER_SDMA,
3440 };
3441
3442 /* l4_cfg -> ocp_wp_noc */
3443 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3444 .master = &omap44xx_l4_cfg_hwmod,
3445 .slave = &omap44xx_ocp_wp_noc_hwmod,
3446 .clk = "l4_div_ck",
3447 .user = OCP_USER_MPU | OCP_USER_SDMA,
3448 };
3449
3450 static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
3451 {
3452 .name = "dmem",
3453 .pa_start = 0x40180000,
3454 .pa_end = 0x4018ffff
3455 },
3456 {
3457 .name = "cmem",
3458 .pa_start = 0x401a0000,
3459 .pa_end = 0x401a1fff
3460 },
3461 {
3462 .name = "smem",
3463 .pa_start = 0x401c0000,
3464 .pa_end = 0x401c5fff
3465 },
3466 {
3467 .name = "pmem",
3468 .pa_start = 0x401e0000,
3469 .pa_end = 0x401e1fff
3470 },
3471 {
3472 .name = "mpu",
3473 .pa_start = 0x401f1000,
3474 .pa_end = 0x401f13ff,
3475 .flags = ADDR_TYPE_RT
3476 },
3477 { }
3478 };
3479
3480 /* l4_abe -> aess */
3481 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
3482 .master = &omap44xx_l4_abe_hwmod,
3483 .slave = &omap44xx_aess_hwmod,
3484 .clk = "ocp_abe_iclk",
3485 .addr = omap44xx_aess_addrs,
3486 .user = OCP_USER_MPU,
3487 };
3488
3489 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
3490 {
3491 .name = "dmem_dma",
3492 .pa_start = 0x49080000,
3493 .pa_end = 0x4908ffff
3494 },
3495 {
3496 .name = "cmem_dma",
3497 .pa_start = 0x490a0000,
3498 .pa_end = 0x490a1fff
3499 },
3500 {
3501 .name = "smem_dma",
3502 .pa_start = 0x490c0000,
3503 .pa_end = 0x490c5fff
3504 },
3505 {
3506 .name = "pmem_dma",
3507 .pa_start = 0x490e0000,
3508 .pa_end = 0x490e1fff
3509 },
3510 {
3511 .name = "dma",
3512 .pa_start = 0x490f1000,
3513 .pa_end = 0x490f13ff,
3514 .flags = ADDR_TYPE_RT
3515 },
3516 { }
3517 };
3518
3519 /* l4_abe -> aess (dma) */
3520 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
3521 .master = &omap44xx_l4_abe_hwmod,
3522 .slave = &omap44xx_aess_hwmod,
3523 .clk = "ocp_abe_iclk",
3524 .addr = omap44xx_aess_dma_addrs,
3525 .user = OCP_USER_SDMA,
3526 };
3527
3528 /* l3_main_2 -> c2c */
3529 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
3530 .master = &omap44xx_l3_main_2_hwmod,
3531 .slave = &omap44xx_c2c_hwmod,
3532 .clk = "l3_div_ck",
3533 .user = OCP_USER_MPU | OCP_USER_SDMA,
3534 };
3535
3536 /* l4_wkup -> counter_32k */
3537 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
3538 .master = &omap44xx_l4_wkup_hwmod,
3539 .slave = &omap44xx_counter_32k_hwmod,
3540 .clk = "l4_wkup_clk_mux_ck",
3541 .user = OCP_USER_MPU | OCP_USER_SDMA,
3542 };
3543
3544 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs[] = {
3545 {
3546 .pa_start = 0x4a002000,
3547 .pa_end = 0x4a0027ff,
3548 .flags = ADDR_TYPE_RT
3549 },
3550 { }
3551 };
3552
3553 /* l4_cfg -> ctrl_module_core */
3554 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
3555 .master = &omap44xx_l4_cfg_hwmod,
3556 .slave = &omap44xx_ctrl_module_core_hwmod,
3557 .clk = "l4_div_ck",
3558 .addr = omap44xx_ctrl_module_core_addrs,
3559 .user = OCP_USER_MPU | OCP_USER_SDMA,
3560 };
3561
3562 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs[] = {
3563 {
3564 .pa_start = 0x4a100000,
3565 .pa_end = 0x4a1007ff,
3566 .flags = ADDR_TYPE_RT
3567 },
3568 { }
3569 };
3570
3571 /* l4_cfg -> ctrl_module_pad_core */
3572 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
3573 .master = &omap44xx_l4_cfg_hwmod,
3574 .slave = &omap44xx_ctrl_module_pad_core_hwmod,
3575 .clk = "l4_div_ck",
3576 .addr = omap44xx_ctrl_module_pad_core_addrs,
3577 .user = OCP_USER_MPU | OCP_USER_SDMA,
3578 };
3579
3580 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs[] = {
3581 {
3582 .pa_start = 0x4a30c000,
3583 .pa_end = 0x4a30c7ff,
3584 .flags = ADDR_TYPE_RT
3585 },
3586 { }
3587 };
3588
3589 /* l4_wkup -> ctrl_module_wkup */
3590 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
3591 .master = &omap44xx_l4_wkup_hwmod,
3592 .slave = &omap44xx_ctrl_module_wkup_hwmod,
3593 .clk = "l4_wkup_clk_mux_ck",
3594 .addr = omap44xx_ctrl_module_wkup_addrs,
3595 .user = OCP_USER_MPU | OCP_USER_SDMA,
3596 };
3597
3598 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs[] = {
3599 {
3600 .pa_start = 0x4a31e000,
3601 .pa_end = 0x4a31e7ff,
3602 .flags = ADDR_TYPE_RT
3603 },
3604 { }
3605 };
3606
3607 /* l4_wkup -> ctrl_module_pad_wkup */
3608 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
3609 .master = &omap44xx_l4_wkup_hwmod,
3610 .slave = &omap44xx_ctrl_module_pad_wkup_hwmod,
3611 .clk = "l4_wkup_clk_mux_ck",
3612 .addr = omap44xx_ctrl_module_pad_wkup_addrs,
3613 .user = OCP_USER_MPU | OCP_USER_SDMA,
3614 };
3615
3616 /* l3_instr -> debugss */
3617 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
3618 .master = &omap44xx_l3_instr_hwmod,
3619 .slave = &omap44xx_debugss_hwmod,
3620 .clk = "l3_div_ck",
3621 .user = OCP_USER_MPU | OCP_USER_SDMA,
3622 };
3623
3624 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
3625 {
3626 .pa_start = 0x4a056000,
3627 .pa_end = 0x4a056fff,
3628 .flags = ADDR_TYPE_RT
3629 },
3630 { }
3631 };
3632
3633 /* l4_cfg -> dma_system */
3634 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
3635 .master = &omap44xx_l4_cfg_hwmod,
3636 .slave = &omap44xx_dma_system_hwmod,
3637 .clk = "l4_div_ck",
3638 .addr = omap44xx_dma_system_addrs,
3639 .user = OCP_USER_MPU | OCP_USER_SDMA,
3640 };
3641
3642 /* l4_abe -> dmic */
3643 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
3644 .master = &omap44xx_l4_abe_hwmod,
3645 .slave = &omap44xx_dmic_hwmod,
3646 .clk = "ocp_abe_iclk",
3647 .user = OCP_USER_MPU,
3648 };
3649
3650 /* l4_abe -> dmic (dma) */
3651 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
3652 .master = &omap44xx_l4_abe_hwmod,
3653 .slave = &omap44xx_dmic_hwmod,
3654 .clk = "ocp_abe_iclk",
3655 .user = OCP_USER_SDMA,
3656 };
3657
3658 /* dsp -> iva */
3659 static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
3660 .master = &omap44xx_dsp_hwmod,
3661 .slave = &omap44xx_iva_hwmod,
3662 .clk = "dpll_iva_m5x2_ck",
3663 .user = OCP_USER_DSP,
3664 };
3665
3666 /* dsp -> sl2if */
3667 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
3668 .master = &omap44xx_dsp_hwmod,
3669 .slave = &omap44xx_sl2if_hwmod,
3670 .clk = "dpll_iva_m5x2_ck",
3671 .user = OCP_USER_DSP,
3672 };
3673
3674 /* l4_cfg -> dsp */
3675 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
3676 .master = &omap44xx_l4_cfg_hwmod,
3677 .slave = &omap44xx_dsp_hwmod,
3678 .clk = "l4_div_ck",
3679 .user = OCP_USER_MPU | OCP_USER_SDMA,
3680 };
3681
3682 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
3683 {
3684 .pa_start = 0x58000000,
3685 .pa_end = 0x5800007f,
3686 .flags = ADDR_TYPE_RT
3687 },
3688 { }
3689 };
3690
3691 /* l3_main_2 -> dss */
3692 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
3693 .master = &omap44xx_l3_main_2_hwmod,
3694 .slave = &omap44xx_dss_hwmod,
3695 .clk = "dss_fck",
3696 .addr = omap44xx_dss_dma_addrs,
3697 .user = OCP_USER_SDMA,
3698 };
3699
3700 static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
3701 {
3702 .pa_start = 0x48040000,
3703 .pa_end = 0x4804007f,
3704 .flags = ADDR_TYPE_RT
3705 },
3706 { }
3707 };
3708
3709 /* l4_per -> dss */
3710 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
3711 .master = &omap44xx_l4_per_hwmod,
3712 .slave = &omap44xx_dss_hwmod,
3713 .clk = "l4_div_ck",
3714 .addr = omap44xx_dss_addrs,
3715 .user = OCP_USER_MPU,
3716 };
3717
3718 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
3719 {
3720 .pa_start = 0x58001000,
3721 .pa_end = 0x58001fff,
3722 .flags = ADDR_TYPE_RT
3723 },
3724 { }
3725 };
3726
3727 /* l3_main_2 -> dss_dispc */
3728 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
3729 .master = &omap44xx_l3_main_2_hwmod,
3730 .slave = &omap44xx_dss_dispc_hwmod,
3731 .clk = "dss_fck",
3732 .addr = omap44xx_dss_dispc_dma_addrs,
3733 .user = OCP_USER_SDMA,
3734 };
3735
3736 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
3737 {
3738 .pa_start = 0x48041000,
3739 .pa_end = 0x48041fff,
3740 .flags = ADDR_TYPE_RT
3741 },
3742 { }
3743 };
3744
3745 /* l4_per -> dss_dispc */
3746 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
3747 .master = &omap44xx_l4_per_hwmod,
3748 .slave = &omap44xx_dss_dispc_hwmod,
3749 .clk = "l4_div_ck",
3750 .addr = omap44xx_dss_dispc_addrs,
3751 .user = OCP_USER_MPU,
3752 };
3753
3754 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
3755 {
3756 .pa_start = 0x58004000,
3757 .pa_end = 0x580041ff,
3758 .flags = ADDR_TYPE_RT
3759 },
3760 { }
3761 };
3762
3763 /* l3_main_2 -> dss_dsi1 */
3764 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
3765 .master = &omap44xx_l3_main_2_hwmod,
3766 .slave = &omap44xx_dss_dsi1_hwmod,
3767 .clk = "dss_fck",
3768 .addr = omap44xx_dss_dsi1_dma_addrs,
3769 .user = OCP_USER_SDMA,
3770 };
3771
3772 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
3773 {
3774 .pa_start = 0x48044000,
3775 .pa_end = 0x480441ff,
3776 .flags = ADDR_TYPE_RT
3777 },
3778 { }
3779 };
3780
3781 /* l4_per -> dss_dsi1 */
3782 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
3783 .master = &omap44xx_l4_per_hwmod,
3784 .slave = &omap44xx_dss_dsi1_hwmod,
3785 .clk = "l4_div_ck",
3786 .addr = omap44xx_dss_dsi1_addrs,
3787 .user = OCP_USER_MPU,
3788 };
3789
3790 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
3791 {
3792 .pa_start = 0x58005000,
3793 .pa_end = 0x580051ff,
3794 .flags = ADDR_TYPE_RT
3795 },
3796 { }
3797 };
3798
3799 /* l3_main_2 -> dss_dsi2 */
3800 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
3801 .master = &omap44xx_l3_main_2_hwmod,
3802 .slave = &omap44xx_dss_dsi2_hwmod,
3803 .clk = "dss_fck",
3804 .addr = omap44xx_dss_dsi2_dma_addrs,
3805 .user = OCP_USER_SDMA,
3806 };
3807
3808 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
3809 {
3810 .pa_start = 0x48045000,
3811 .pa_end = 0x480451ff,
3812 .flags = ADDR_TYPE_RT
3813 },
3814 { }
3815 };
3816
3817 /* l4_per -> dss_dsi2 */
3818 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
3819 .master = &omap44xx_l4_per_hwmod,
3820 .slave = &omap44xx_dss_dsi2_hwmod,
3821 .clk = "l4_div_ck",
3822 .addr = omap44xx_dss_dsi2_addrs,
3823 .user = OCP_USER_MPU,
3824 };
3825
3826 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
3827 {
3828 .pa_start = 0x58006000,
3829 .pa_end = 0x58006fff,
3830 .flags = ADDR_TYPE_RT
3831 },
3832 { }
3833 };
3834
3835 /* l3_main_2 -> dss_hdmi */
3836 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
3837 .master = &omap44xx_l3_main_2_hwmod,
3838 .slave = &omap44xx_dss_hdmi_hwmod,
3839 .clk = "dss_fck",
3840 .addr = omap44xx_dss_hdmi_dma_addrs,
3841 .user = OCP_USER_SDMA,
3842 };
3843
3844 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
3845 {
3846 .pa_start = 0x48046000,
3847 .pa_end = 0x48046fff,
3848 .flags = ADDR_TYPE_RT
3849 },
3850 { }
3851 };
3852
3853 /* l4_per -> dss_hdmi */
3854 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
3855 .master = &omap44xx_l4_per_hwmod,
3856 .slave = &omap44xx_dss_hdmi_hwmod,
3857 .clk = "l4_div_ck",
3858 .addr = omap44xx_dss_hdmi_addrs,
3859 .user = OCP_USER_MPU,
3860 };
3861
3862 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
3863 {
3864 .pa_start = 0x58002000,
3865 .pa_end = 0x580020ff,
3866 .flags = ADDR_TYPE_RT
3867 },
3868 { }
3869 };
3870
3871 /* l3_main_2 -> dss_rfbi */
3872 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
3873 .master = &omap44xx_l3_main_2_hwmod,
3874 .slave = &omap44xx_dss_rfbi_hwmod,
3875 .clk = "dss_fck",
3876 .addr = omap44xx_dss_rfbi_dma_addrs,
3877 .user = OCP_USER_SDMA,
3878 };
3879
3880 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
3881 {
3882 .pa_start = 0x48042000,
3883 .pa_end = 0x480420ff,
3884 .flags = ADDR_TYPE_RT
3885 },
3886 { }
3887 };
3888
3889 /* l4_per -> dss_rfbi */
3890 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
3891 .master = &omap44xx_l4_per_hwmod,
3892 .slave = &omap44xx_dss_rfbi_hwmod,
3893 .clk = "l4_div_ck",
3894 .addr = omap44xx_dss_rfbi_addrs,
3895 .user = OCP_USER_MPU,
3896 };
3897
3898 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
3899 {
3900 .pa_start = 0x58003000,
3901 .pa_end = 0x580030ff,
3902 .flags = ADDR_TYPE_RT
3903 },
3904 { }
3905 };
3906
3907 /* l3_main_2 -> dss_venc */
3908 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
3909 .master = &omap44xx_l3_main_2_hwmod,
3910 .slave = &omap44xx_dss_venc_hwmod,
3911 .clk = "dss_fck",
3912 .addr = omap44xx_dss_venc_dma_addrs,
3913 .user = OCP_USER_SDMA,
3914 };
3915
3916 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
3917 {
3918 .pa_start = 0x48043000,
3919 .pa_end = 0x480430ff,
3920 .flags = ADDR_TYPE_RT
3921 },
3922 { }
3923 };
3924
3925 /* l4_per -> dss_venc */
3926 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
3927 .master = &omap44xx_l4_per_hwmod,
3928 .slave = &omap44xx_dss_venc_hwmod,
3929 .clk = "l4_div_ck",
3930 .addr = omap44xx_dss_venc_addrs,
3931 .user = OCP_USER_MPU,
3932 };
3933
3934 static struct omap_hwmod_addr_space omap44xx_elm_addrs[] = {
3935 {
3936 .pa_start = 0x48078000,
3937 .pa_end = 0x48078fff,
3938 .flags = ADDR_TYPE_RT
3939 },
3940 { }
3941 };
3942
3943 /* l4_per -> elm */
3944 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
3945 .master = &omap44xx_l4_per_hwmod,
3946 .slave = &omap44xx_elm_hwmod,
3947 .clk = "l4_div_ck",
3948 .addr = omap44xx_elm_addrs,
3949 .user = OCP_USER_MPU | OCP_USER_SDMA,
3950 };
3951
3952 static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = {
3953 {
3954 .pa_start = 0x4a10a000,
3955 .pa_end = 0x4a10a1ff,
3956 .flags = ADDR_TYPE_RT
3957 },
3958 { }
3959 };
3960
3961 /* l4_cfg -> fdif */
3962 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
3963 .master = &omap44xx_l4_cfg_hwmod,
3964 .slave = &omap44xx_fdif_hwmod,
3965 .clk = "l4_div_ck",
3966 .addr = omap44xx_fdif_addrs,
3967 .user = OCP_USER_MPU | OCP_USER_SDMA,
3968 };
3969
3970 /* l4_wkup -> gpio1 */
3971 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
3972 .master = &omap44xx_l4_wkup_hwmod,
3973 .slave = &omap44xx_gpio1_hwmod,
3974 .clk = "l4_wkup_clk_mux_ck",
3975 .user = OCP_USER_MPU | OCP_USER_SDMA,
3976 };
3977
3978 /* l4_per -> gpio2 */
3979 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
3980 .master = &omap44xx_l4_per_hwmod,
3981 .slave = &omap44xx_gpio2_hwmod,
3982 .clk = "l4_div_ck",
3983 .user = OCP_USER_MPU | OCP_USER_SDMA,
3984 };
3985
3986 /* l4_per -> gpio3 */
3987 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
3988 .master = &omap44xx_l4_per_hwmod,
3989 .slave = &omap44xx_gpio3_hwmod,
3990 .clk = "l4_div_ck",
3991 .user = OCP_USER_MPU | OCP_USER_SDMA,
3992 };
3993
3994 /* l4_per -> gpio4 */
3995 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
3996 .master = &omap44xx_l4_per_hwmod,
3997 .slave = &omap44xx_gpio4_hwmod,
3998 .clk = "l4_div_ck",
3999 .user = OCP_USER_MPU | OCP_USER_SDMA,
4000 };
4001
4002 /* l4_per -> gpio5 */
4003 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
4004 .master = &omap44xx_l4_per_hwmod,
4005 .slave = &omap44xx_gpio5_hwmod,
4006 .clk = "l4_div_ck",
4007 .user = OCP_USER_MPU | OCP_USER_SDMA,
4008 };
4009
4010 /* l4_per -> gpio6 */
4011 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
4012 .master = &omap44xx_l4_per_hwmod,
4013 .slave = &omap44xx_gpio6_hwmod,
4014 .clk = "l4_div_ck",
4015 .user = OCP_USER_MPU | OCP_USER_SDMA,
4016 };
4017
4018 /* l3_main_2 -> gpmc */
4019 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
4020 .master = &omap44xx_l3_main_2_hwmod,
4021 .slave = &omap44xx_gpmc_hwmod,
4022 .clk = "l3_div_ck",
4023 .user = OCP_USER_MPU | OCP_USER_SDMA,
4024 };
4025
4026 static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = {
4027 {
4028 .pa_start = 0x56000000,
4029 .pa_end = 0x5600ffff,
4030 .flags = ADDR_TYPE_RT
4031 },
4032 { }
4033 };
4034
4035 /* l3_main_2 -> gpu */
4036 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
4037 .master = &omap44xx_l3_main_2_hwmod,
4038 .slave = &omap44xx_gpu_hwmod,
4039 .clk = "l3_div_ck",
4040 .addr = omap44xx_gpu_addrs,
4041 .user = OCP_USER_MPU | OCP_USER_SDMA,
4042 };
4043
4044 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = {
4045 {
4046 .pa_start = 0x480b2000,
4047 .pa_end = 0x480b201f,
4048 .flags = ADDR_TYPE_RT
4049 },
4050 { }
4051 };
4052
4053 /* l4_per -> hdq1w */
4054 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
4055 .master = &omap44xx_l4_per_hwmod,
4056 .slave = &omap44xx_hdq1w_hwmod,
4057 .clk = "l4_div_ck",
4058 .addr = omap44xx_hdq1w_addrs,
4059 .user = OCP_USER_MPU | OCP_USER_SDMA,
4060 };
4061
4062 static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
4063 {
4064 .pa_start = 0x4a058000,
4065 .pa_end = 0x4a05bfff,
4066 .flags = ADDR_TYPE_RT
4067 },
4068 { }
4069 };
4070
4071 /* l4_cfg -> hsi */
4072 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
4073 .master = &omap44xx_l4_cfg_hwmod,
4074 .slave = &omap44xx_hsi_hwmod,
4075 .clk = "l4_div_ck",
4076 .addr = omap44xx_hsi_addrs,
4077 .user = OCP_USER_MPU | OCP_USER_SDMA,
4078 };
4079
4080 /* l4_per -> i2c1 */
4081 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
4082 .master = &omap44xx_l4_per_hwmod,
4083 .slave = &omap44xx_i2c1_hwmod,
4084 .clk = "l4_div_ck",
4085 .user = OCP_USER_MPU | OCP_USER_SDMA,
4086 };
4087
4088 /* l4_per -> i2c2 */
4089 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
4090 .master = &omap44xx_l4_per_hwmod,
4091 .slave = &omap44xx_i2c2_hwmod,
4092 .clk = "l4_div_ck",
4093 .user = OCP_USER_MPU | OCP_USER_SDMA,
4094 };
4095
4096 /* l4_per -> i2c3 */
4097 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
4098 .master = &omap44xx_l4_per_hwmod,
4099 .slave = &omap44xx_i2c3_hwmod,
4100 .clk = "l4_div_ck",
4101 .user = OCP_USER_MPU | OCP_USER_SDMA,
4102 };
4103
4104 /* l4_per -> i2c4 */
4105 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
4106 .master = &omap44xx_l4_per_hwmod,
4107 .slave = &omap44xx_i2c4_hwmod,
4108 .clk = "l4_div_ck",
4109 .user = OCP_USER_MPU | OCP_USER_SDMA,
4110 };
4111
4112 /* l3_main_2 -> ipu */
4113 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
4114 .master = &omap44xx_l3_main_2_hwmod,
4115 .slave = &omap44xx_ipu_hwmod,
4116 .clk = "l3_div_ck",
4117 .user = OCP_USER_MPU | OCP_USER_SDMA,
4118 };
4119
4120 static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
4121 {
4122 .pa_start = 0x52000000,
4123 .pa_end = 0x520000ff,
4124 .flags = ADDR_TYPE_RT
4125 },
4126 { }
4127 };
4128
4129 /* l3_main_2 -> iss */
4130 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
4131 .master = &omap44xx_l3_main_2_hwmod,
4132 .slave = &omap44xx_iss_hwmod,
4133 .clk = "l3_div_ck",
4134 .addr = omap44xx_iss_addrs,
4135 .user = OCP_USER_MPU | OCP_USER_SDMA,
4136 };
4137
4138 /* iva -> sl2if */
4139 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
4140 .master = &omap44xx_iva_hwmod,
4141 .slave = &omap44xx_sl2if_hwmod,
4142 .clk = "dpll_iva_m5x2_ck",
4143 .user = OCP_USER_IVA,
4144 };
4145
4146 /* l3_main_2 -> iva */
4147 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
4148 .master = &omap44xx_l3_main_2_hwmod,
4149 .slave = &omap44xx_iva_hwmod,
4150 .clk = "l3_div_ck",
4151 .user = OCP_USER_MPU,
4152 };
4153
4154 /* l4_wkup -> kbd */
4155 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
4156 .master = &omap44xx_l4_wkup_hwmod,
4157 .slave = &omap44xx_kbd_hwmod,
4158 .clk = "l4_wkup_clk_mux_ck",
4159 .user = OCP_USER_MPU | OCP_USER_SDMA,
4160 };
4161
4162 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
4163 {
4164 .pa_start = 0x4a0f4000,
4165 .pa_end = 0x4a0f41ff,
4166 .flags = ADDR_TYPE_RT
4167 },
4168 { }
4169 };
4170
4171 /* l4_cfg -> mailbox */
4172 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
4173 .master = &omap44xx_l4_cfg_hwmod,
4174 .slave = &omap44xx_mailbox_hwmod,
4175 .clk = "l4_div_ck",
4176 .addr = omap44xx_mailbox_addrs,
4177 .user = OCP_USER_MPU | OCP_USER_SDMA,
4178 };
4179
4180 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs[] = {
4181 {
4182 .pa_start = 0x40128000,
4183 .pa_end = 0x401283ff,
4184 .flags = ADDR_TYPE_RT
4185 },
4186 { }
4187 };
4188
4189 /* l4_abe -> mcasp */
4190 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
4191 .master = &omap44xx_l4_abe_hwmod,
4192 .slave = &omap44xx_mcasp_hwmod,
4193 .clk = "ocp_abe_iclk",
4194 .addr = omap44xx_mcasp_addrs,
4195 .user = OCP_USER_MPU,
4196 };
4197
4198 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs[] = {
4199 {
4200 .pa_start = 0x49028000,
4201 .pa_end = 0x490283ff,
4202 .flags = ADDR_TYPE_RT
4203 },
4204 { }
4205 };
4206
4207 /* l4_abe -> mcasp (dma) */
4208 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
4209 .master = &omap44xx_l4_abe_hwmod,
4210 .slave = &omap44xx_mcasp_hwmod,
4211 .clk = "ocp_abe_iclk",
4212 .addr = omap44xx_mcasp_dma_addrs,
4213 .user = OCP_USER_SDMA,
4214 };
4215
4216 /* l4_abe -> mcbsp1 */
4217 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
4218 .master = &omap44xx_l4_abe_hwmod,
4219 .slave = &omap44xx_mcbsp1_hwmod,
4220 .clk = "ocp_abe_iclk",
4221 .user = OCP_USER_MPU,
4222 };
4223
4224 /* l4_abe -> mcbsp1 (dma) */
4225 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
4226 .master = &omap44xx_l4_abe_hwmod,
4227 .slave = &omap44xx_mcbsp1_hwmod,
4228 .clk = "ocp_abe_iclk",
4229 .user = OCP_USER_SDMA,
4230 };
4231
4232 /* l4_abe -> mcbsp2 */
4233 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
4234 .master = &omap44xx_l4_abe_hwmod,
4235 .slave = &omap44xx_mcbsp2_hwmod,
4236 .clk = "ocp_abe_iclk",
4237 .user = OCP_USER_MPU,
4238 };
4239
4240 /* l4_abe -> mcbsp2 (dma) */
4241 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
4242 .master = &omap44xx_l4_abe_hwmod,
4243 .slave = &omap44xx_mcbsp2_hwmod,
4244 .clk = "ocp_abe_iclk",
4245 .user = OCP_USER_SDMA,
4246 };
4247
4248 /* l4_abe -> mcbsp3 */
4249 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
4250 .master = &omap44xx_l4_abe_hwmod,
4251 .slave = &omap44xx_mcbsp3_hwmod,
4252 .clk = "ocp_abe_iclk",
4253 .user = OCP_USER_MPU,
4254 };
4255
4256 /* l4_abe -> mcbsp3 (dma) */
4257 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
4258 .master = &omap44xx_l4_abe_hwmod,
4259 .slave = &omap44xx_mcbsp3_hwmod,
4260 .clk = "ocp_abe_iclk",
4261 .user = OCP_USER_SDMA,
4262 };
4263
4264 /* l4_per -> mcbsp4 */
4265 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
4266 .master = &omap44xx_l4_per_hwmod,
4267 .slave = &omap44xx_mcbsp4_hwmod,
4268 .clk = "l4_div_ck",
4269 .user = OCP_USER_MPU | OCP_USER_SDMA,
4270 };
4271
4272 /* l4_abe -> mcpdm */
4273 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
4274 .master = &omap44xx_l4_abe_hwmod,
4275 .slave = &omap44xx_mcpdm_hwmod,
4276 .clk = "ocp_abe_iclk",
4277 .user = OCP_USER_MPU,
4278 };
4279
4280 /* l4_abe -> mcpdm (dma) */
4281 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
4282 .master = &omap44xx_l4_abe_hwmod,
4283 .slave = &omap44xx_mcpdm_hwmod,
4284 .clk = "ocp_abe_iclk",
4285 .user = OCP_USER_SDMA,
4286 };
4287
4288 /* l4_per -> mcspi1 */
4289 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
4290 .master = &omap44xx_l4_per_hwmod,
4291 .slave = &omap44xx_mcspi1_hwmod,
4292 .clk = "l4_div_ck",
4293 .user = OCP_USER_MPU | OCP_USER_SDMA,
4294 };
4295
4296 /* l4_per -> mcspi2 */
4297 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
4298 .master = &omap44xx_l4_per_hwmod,
4299 .slave = &omap44xx_mcspi2_hwmod,
4300 .clk = "l4_div_ck",
4301 .user = OCP_USER_MPU | OCP_USER_SDMA,
4302 };
4303
4304 /* l4_per -> mcspi3 */
4305 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
4306 .master = &omap44xx_l4_per_hwmod,
4307 .slave = &omap44xx_mcspi3_hwmod,
4308 .clk = "l4_div_ck",
4309 .user = OCP_USER_MPU | OCP_USER_SDMA,
4310 };
4311
4312 /* l4_per -> mcspi4 */
4313 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
4314 .master = &omap44xx_l4_per_hwmod,
4315 .slave = &omap44xx_mcspi4_hwmod,
4316 .clk = "l4_div_ck",
4317 .user = OCP_USER_MPU | OCP_USER_SDMA,
4318 };
4319
4320 /* l4_per -> mmc1 */
4321 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
4322 .master = &omap44xx_l4_per_hwmod,
4323 .slave = &omap44xx_mmc1_hwmod,
4324 .clk = "l4_div_ck",
4325 .user = OCP_USER_MPU | OCP_USER_SDMA,
4326 };
4327
4328 /* l4_per -> mmc2 */
4329 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
4330 .master = &omap44xx_l4_per_hwmod,
4331 .slave = &omap44xx_mmc2_hwmod,
4332 .clk = "l4_div_ck",
4333 .user = OCP_USER_MPU | OCP_USER_SDMA,
4334 };
4335
4336 /* l4_per -> mmc3 */
4337 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
4338 .master = &omap44xx_l4_per_hwmod,
4339 .slave = &omap44xx_mmc3_hwmod,
4340 .clk = "l4_div_ck",
4341 .user = OCP_USER_MPU | OCP_USER_SDMA,
4342 };
4343
4344 /* l4_per -> mmc4 */
4345 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
4346 .master = &omap44xx_l4_per_hwmod,
4347 .slave = &omap44xx_mmc4_hwmod,
4348 .clk = "l4_div_ck",
4349 .user = OCP_USER_MPU | OCP_USER_SDMA,
4350 };
4351
4352 /* l4_per -> mmc5 */
4353 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
4354 .master = &omap44xx_l4_per_hwmod,
4355 .slave = &omap44xx_mmc5_hwmod,
4356 .clk = "l4_div_ck",
4357 .user = OCP_USER_MPU | OCP_USER_SDMA,
4358 };
4359
4360 /* l3_main_2 -> ocmc_ram */
4361 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
4362 .master = &omap44xx_l3_main_2_hwmod,
4363 .slave = &omap44xx_ocmc_ram_hwmod,
4364 .clk = "l3_div_ck",
4365 .user = OCP_USER_MPU | OCP_USER_SDMA,
4366 };
4367
4368 /* l4_cfg -> ocp2scp_usb_phy */
4369 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
4370 .master = &omap44xx_l4_cfg_hwmod,
4371 .slave = &omap44xx_ocp2scp_usb_phy_hwmod,
4372 .clk = "l4_div_ck",
4373 .user = OCP_USER_MPU | OCP_USER_SDMA,
4374 };
4375
4376 /* mpu_private -> prcm_mpu */
4377 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
4378 .master = &omap44xx_mpu_private_hwmod,
4379 .slave = &omap44xx_prcm_mpu_hwmod,
4380 .clk = "l3_div_ck",
4381 .user = OCP_USER_MPU | OCP_USER_SDMA,
4382 };
4383
4384 /* l4_wkup -> cm_core_aon */
4385 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
4386 .master = &omap44xx_l4_wkup_hwmod,
4387 .slave = &omap44xx_cm_core_aon_hwmod,
4388 .clk = "l4_wkup_clk_mux_ck",
4389 .user = OCP_USER_MPU | OCP_USER_SDMA,
4390 };
4391
4392 /* l4_cfg -> cm_core */
4393 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
4394 .master = &omap44xx_l4_cfg_hwmod,
4395 .slave = &omap44xx_cm_core_hwmod,
4396 .clk = "l4_div_ck",
4397 .user = OCP_USER_MPU | OCP_USER_SDMA,
4398 };
4399
4400 /* l4_wkup -> prm */
4401 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
4402 .master = &omap44xx_l4_wkup_hwmod,
4403 .slave = &omap44xx_prm_hwmod,
4404 .clk = "l4_wkup_clk_mux_ck",
4405 .user = OCP_USER_MPU | OCP_USER_SDMA,
4406 };
4407
4408 /* l4_wkup -> scrm */
4409 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
4410 .master = &omap44xx_l4_wkup_hwmod,
4411 .slave = &omap44xx_scrm_hwmod,
4412 .clk = "l4_wkup_clk_mux_ck",
4413 .user = OCP_USER_MPU | OCP_USER_SDMA,
4414 };
4415
4416 /* l3_main_2 -> sl2if */
4417 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
4418 .master = &omap44xx_l3_main_2_hwmod,
4419 .slave = &omap44xx_sl2if_hwmod,
4420 .clk = "l3_div_ck",
4421 .user = OCP_USER_MPU | OCP_USER_SDMA,
4422 };
4423
4424 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs[] = {
4425 {
4426 .pa_start = 0x4012c000,
4427 .pa_end = 0x4012c3ff,
4428 .flags = ADDR_TYPE_RT
4429 },
4430 { }
4431 };
4432
4433 /* l4_abe -> slimbus1 */
4434 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
4435 .master = &omap44xx_l4_abe_hwmod,
4436 .slave = &omap44xx_slimbus1_hwmod,
4437 .clk = "ocp_abe_iclk",
4438 .addr = omap44xx_slimbus1_addrs,
4439 .user = OCP_USER_MPU,
4440 };
4441
4442 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs[] = {
4443 {
4444 .pa_start = 0x4902c000,
4445 .pa_end = 0x4902c3ff,
4446 .flags = ADDR_TYPE_RT
4447 },
4448 { }
4449 };
4450
4451 /* l4_abe -> slimbus1 (dma) */
4452 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
4453 .master = &omap44xx_l4_abe_hwmod,
4454 .slave = &omap44xx_slimbus1_hwmod,
4455 .clk = "ocp_abe_iclk",
4456 .addr = omap44xx_slimbus1_dma_addrs,
4457 .user = OCP_USER_SDMA,
4458 };
4459
4460 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs[] = {
4461 {
4462 .pa_start = 0x48076000,
4463 .pa_end = 0x480763ff,
4464 .flags = ADDR_TYPE_RT
4465 },
4466 { }
4467 };
4468
4469 /* l4_per -> slimbus2 */
4470 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
4471 .master = &omap44xx_l4_per_hwmod,
4472 .slave = &omap44xx_slimbus2_hwmod,
4473 .clk = "l4_div_ck",
4474 .addr = omap44xx_slimbus2_addrs,
4475 .user = OCP_USER_MPU | OCP_USER_SDMA,
4476 };
4477
4478 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
4479 {
4480 .pa_start = 0x4a0dd000,
4481 .pa_end = 0x4a0dd03f,
4482 .flags = ADDR_TYPE_RT
4483 },
4484 { }
4485 };
4486
4487 /* l4_cfg -> smartreflex_core */
4488 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
4489 .master = &omap44xx_l4_cfg_hwmod,
4490 .slave = &omap44xx_smartreflex_core_hwmod,
4491 .clk = "l4_div_ck",
4492 .addr = omap44xx_smartreflex_core_addrs,
4493 .user = OCP_USER_MPU | OCP_USER_SDMA,
4494 };
4495
4496 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
4497 {
4498 .pa_start = 0x4a0db000,
4499 .pa_end = 0x4a0db03f,
4500 .flags = ADDR_TYPE_RT
4501 },
4502 { }
4503 };
4504
4505 /* l4_cfg -> smartreflex_iva */
4506 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
4507 .master = &omap44xx_l4_cfg_hwmod,
4508 .slave = &omap44xx_smartreflex_iva_hwmod,
4509 .clk = "l4_div_ck",
4510 .addr = omap44xx_smartreflex_iva_addrs,
4511 .user = OCP_USER_MPU | OCP_USER_SDMA,
4512 };
4513
4514 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
4515 {
4516 .pa_start = 0x4a0d9000,
4517 .pa_end = 0x4a0d903f,
4518 .flags = ADDR_TYPE_RT
4519 },
4520 { }
4521 };
4522
4523 /* l4_cfg -> smartreflex_mpu */
4524 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
4525 .master = &omap44xx_l4_cfg_hwmod,
4526 .slave = &omap44xx_smartreflex_mpu_hwmod,
4527 .clk = "l4_div_ck",
4528 .addr = omap44xx_smartreflex_mpu_addrs,
4529 .user = OCP_USER_MPU | OCP_USER_SDMA,
4530 };
4531
4532 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
4533 {
4534 .pa_start = 0x4a0f6000,
4535 .pa_end = 0x4a0f6fff,
4536 .flags = ADDR_TYPE_RT
4537 },
4538 { }
4539 };
4540
4541 /* l4_cfg -> spinlock */
4542 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
4543 .master = &omap44xx_l4_cfg_hwmod,
4544 .slave = &omap44xx_spinlock_hwmod,
4545 .clk = "l4_div_ck",
4546 .addr = omap44xx_spinlock_addrs,
4547 .user = OCP_USER_MPU | OCP_USER_SDMA,
4548 };
4549
4550 /* l4_wkup -> timer1 */
4551 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
4552 .master = &omap44xx_l4_wkup_hwmod,
4553 .slave = &omap44xx_timer1_hwmod,
4554 .clk = "l4_wkup_clk_mux_ck",
4555 .user = OCP_USER_MPU | OCP_USER_SDMA,
4556 };
4557
4558 /* l4_per -> timer2 */
4559 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
4560 .master = &omap44xx_l4_per_hwmod,
4561 .slave = &omap44xx_timer2_hwmod,
4562 .clk = "l4_div_ck",
4563 .user = OCP_USER_MPU | OCP_USER_SDMA,
4564 };
4565
4566 /* l4_per -> timer3 */
4567 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
4568 .master = &omap44xx_l4_per_hwmod,
4569 .slave = &omap44xx_timer3_hwmod,
4570 .clk = "l4_div_ck",
4571 .user = OCP_USER_MPU | OCP_USER_SDMA,
4572 };
4573
4574 /* l4_per -> timer4 */
4575 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
4576 .master = &omap44xx_l4_per_hwmod,
4577 .slave = &omap44xx_timer4_hwmod,
4578 .clk = "l4_div_ck",
4579 .user = OCP_USER_MPU | OCP_USER_SDMA,
4580 };
4581
4582 /* l4_abe -> timer5 */
4583 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
4584 .master = &omap44xx_l4_abe_hwmod,
4585 .slave = &omap44xx_timer5_hwmod,
4586 .clk = "ocp_abe_iclk",
4587 .user = OCP_USER_MPU,
4588 };
4589
4590 /* l4_abe -> timer5 (dma) */
4591 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
4592 .master = &omap44xx_l4_abe_hwmod,
4593 .slave = &omap44xx_timer5_hwmod,
4594 .clk = "ocp_abe_iclk",
4595 .user = OCP_USER_SDMA,
4596 };
4597
4598 /* l4_abe -> timer6 */
4599 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4600 .master = &omap44xx_l4_abe_hwmod,
4601 .slave = &omap44xx_timer6_hwmod,
4602 .clk = "ocp_abe_iclk",
4603 .user = OCP_USER_MPU,
4604 };
4605
4606 /* l4_abe -> timer6 (dma) */
4607 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
4608 .master = &omap44xx_l4_abe_hwmod,
4609 .slave = &omap44xx_timer6_hwmod,
4610 .clk = "ocp_abe_iclk",
4611 .user = OCP_USER_SDMA,
4612 };
4613
4614 /* l4_abe -> timer7 */
4615 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4616 .master = &omap44xx_l4_abe_hwmod,
4617 .slave = &omap44xx_timer7_hwmod,
4618 .clk = "ocp_abe_iclk",
4619 .user = OCP_USER_MPU,
4620 };
4621
4622 /* l4_abe -> timer7 (dma) */
4623 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
4624 .master = &omap44xx_l4_abe_hwmod,
4625 .slave = &omap44xx_timer7_hwmod,
4626 .clk = "ocp_abe_iclk",
4627 .user = OCP_USER_SDMA,
4628 };
4629
4630 /* l4_abe -> timer8 */
4631 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4632 .master = &omap44xx_l4_abe_hwmod,
4633 .slave = &omap44xx_timer8_hwmod,
4634 .clk = "ocp_abe_iclk",
4635 .user = OCP_USER_MPU,
4636 };
4637
4638 /* l4_abe -> timer8 (dma) */
4639 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
4640 .master = &omap44xx_l4_abe_hwmod,
4641 .slave = &omap44xx_timer8_hwmod,
4642 .clk = "ocp_abe_iclk",
4643 .user = OCP_USER_SDMA,
4644 };
4645
4646 /* l4_per -> timer9 */
4647 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4648 .master = &omap44xx_l4_per_hwmod,
4649 .slave = &omap44xx_timer9_hwmod,
4650 .clk = "l4_div_ck",
4651 .user = OCP_USER_MPU | OCP_USER_SDMA,
4652 };
4653
4654 /* l4_per -> timer10 */
4655 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4656 .master = &omap44xx_l4_per_hwmod,
4657 .slave = &omap44xx_timer10_hwmod,
4658 .clk = "l4_div_ck",
4659 .user = OCP_USER_MPU | OCP_USER_SDMA,
4660 };
4661
4662 /* l4_per -> timer11 */
4663 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4664 .master = &omap44xx_l4_per_hwmod,
4665 .slave = &omap44xx_timer11_hwmod,
4666 .clk = "l4_div_ck",
4667 .user = OCP_USER_MPU | OCP_USER_SDMA,
4668 };
4669
4670 /* l4_per -> uart1 */
4671 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4672 .master = &omap44xx_l4_per_hwmod,
4673 .slave = &omap44xx_uart1_hwmod,
4674 .clk = "l4_div_ck",
4675 .user = OCP_USER_MPU | OCP_USER_SDMA,
4676 };
4677
4678 /* l4_per -> uart2 */
4679 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4680 .master = &omap44xx_l4_per_hwmod,
4681 .slave = &omap44xx_uart2_hwmod,
4682 .clk = "l4_div_ck",
4683 .user = OCP_USER_MPU | OCP_USER_SDMA,
4684 };
4685
4686 /* l4_per -> uart3 */
4687 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4688 .master = &omap44xx_l4_per_hwmod,
4689 .slave = &omap44xx_uart3_hwmod,
4690 .clk = "l4_div_ck",
4691 .user = OCP_USER_MPU | OCP_USER_SDMA,
4692 };
4693
4694 /* l4_per -> uart4 */
4695 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4696 .master = &omap44xx_l4_per_hwmod,
4697 .slave = &omap44xx_uart4_hwmod,
4698 .clk = "l4_div_ck",
4699 .user = OCP_USER_MPU | OCP_USER_SDMA,
4700 };
4701
4702 /* l4_cfg -> usb_host_fs */
4703 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
4704 .master = &omap44xx_l4_cfg_hwmod,
4705 .slave = &omap44xx_usb_host_fs_hwmod,
4706 .clk = "l4_div_ck",
4707 .user = OCP_USER_MPU | OCP_USER_SDMA,
4708 };
4709
4710 /* l4_cfg -> usb_host_hs */
4711 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
4712 .master = &omap44xx_l4_cfg_hwmod,
4713 .slave = &omap44xx_usb_host_hs_hwmod,
4714 .clk = "l4_div_ck",
4715 .user = OCP_USER_MPU | OCP_USER_SDMA,
4716 };
4717
4718 /* l4_cfg -> usb_otg_hs */
4719 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4720 .master = &omap44xx_l4_cfg_hwmod,
4721 .slave = &omap44xx_usb_otg_hs_hwmod,
4722 .clk = "l4_div_ck",
4723 .user = OCP_USER_MPU | OCP_USER_SDMA,
4724 };
4725
4726 /* l4_cfg -> usb_tll_hs */
4727 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
4728 .master = &omap44xx_l4_cfg_hwmod,
4729 .slave = &omap44xx_usb_tll_hs_hwmod,
4730 .clk = "l4_div_ck",
4731 .user = OCP_USER_MPU | OCP_USER_SDMA,
4732 };
4733
4734 /* l4_wkup -> wd_timer2 */
4735 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4736 .master = &omap44xx_l4_wkup_hwmod,
4737 .slave = &omap44xx_wd_timer2_hwmod,
4738 .clk = "l4_wkup_clk_mux_ck",
4739 .user = OCP_USER_MPU | OCP_USER_SDMA,
4740 };
4741
4742 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
4743 {
4744 .pa_start = 0x40130000,
4745 .pa_end = 0x4013007f,
4746 .flags = ADDR_TYPE_RT
4747 },
4748 { }
4749 };
4750
4751 /* l4_abe -> wd_timer3 */
4752 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4753 .master = &omap44xx_l4_abe_hwmod,
4754 .slave = &omap44xx_wd_timer3_hwmod,
4755 .clk = "ocp_abe_iclk",
4756 .addr = omap44xx_wd_timer3_addrs,
4757 .user = OCP_USER_MPU,
4758 };
4759
4760 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
4761 {
4762 .pa_start = 0x49030000,
4763 .pa_end = 0x4903007f,
4764 .flags = ADDR_TYPE_RT
4765 },
4766 { }
4767 };
4768
4769 /* l4_abe -> wd_timer3 (dma) */
4770 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
4771 .master = &omap44xx_l4_abe_hwmod,
4772 .slave = &omap44xx_wd_timer3_hwmod,
4773 .clk = "ocp_abe_iclk",
4774 .addr = omap44xx_wd_timer3_dma_addrs,
4775 .user = OCP_USER_SDMA,
4776 };
4777
4778 /* mpu -> emif1 */
4779 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
4780 .master = &omap44xx_mpu_hwmod,
4781 .slave = &omap44xx_emif1_hwmod,
4782 .clk = "l3_div_ck",
4783 .user = OCP_USER_MPU | OCP_USER_SDMA,
4784 };
4785
4786 /* mpu -> emif2 */
4787 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
4788 .master = &omap44xx_mpu_hwmod,
4789 .slave = &omap44xx_emif2_hwmod,
4790 .clk = "l3_div_ck",
4791 .user = OCP_USER_MPU | OCP_USER_SDMA,
4792 };
4793
4794 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4795 &omap44xx_l3_main_1__dmm,
4796 &omap44xx_mpu__dmm,
4797 &omap44xx_iva__l3_instr,
4798 &omap44xx_l3_main_3__l3_instr,
4799 &omap44xx_ocp_wp_noc__l3_instr,
4800 &omap44xx_dsp__l3_main_1,
4801 &omap44xx_dss__l3_main_1,
4802 &omap44xx_l3_main_2__l3_main_1,
4803 &omap44xx_l4_cfg__l3_main_1,
4804 &omap44xx_mmc1__l3_main_1,
4805 &omap44xx_mmc2__l3_main_1,
4806 &omap44xx_mpu__l3_main_1,
4807 &omap44xx_debugss__l3_main_2,
4808 &omap44xx_dma_system__l3_main_2,
4809 &omap44xx_fdif__l3_main_2,
4810 &omap44xx_gpu__l3_main_2,
4811 &omap44xx_hsi__l3_main_2,
4812 &omap44xx_ipu__l3_main_2,
4813 &omap44xx_iss__l3_main_2,
4814 &omap44xx_iva__l3_main_2,
4815 &omap44xx_l3_main_1__l3_main_2,
4816 &omap44xx_l4_cfg__l3_main_2,
4817 /* &omap44xx_usb_host_fs__l3_main_2, */
4818 &omap44xx_usb_host_hs__l3_main_2,
4819 &omap44xx_usb_otg_hs__l3_main_2,
4820 &omap44xx_l3_main_1__l3_main_3,
4821 &omap44xx_l3_main_2__l3_main_3,
4822 &omap44xx_l4_cfg__l3_main_3,
4823 &omap44xx_aess__l4_abe,
4824 &omap44xx_dsp__l4_abe,
4825 &omap44xx_l3_main_1__l4_abe,
4826 &omap44xx_mpu__l4_abe,
4827 &omap44xx_l3_main_1__l4_cfg,
4828 &omap44xx_l3_main_2__l4_per,
4829 &omap44xx_l4_cfg__l4_wkup,
4830 &omap44xx_mpu__mpu_private,
4831 &omap44xx_l4_cfg__ocp_wp_noc,
4832 &omap44xx_l4_abe__aess,
4833 &omap44xx_l4_abe__aess_dma,
4834 &omap44xx_l3_main_2__c2c,
4835 &omap44xx_l4_wkup__counter_32k,
4836 &omap44xx_l4_cfg__ctrl_module_core,
4837 &omap44xx_l4_cfg__ctrl_module_pad_core,
4838 &omap44xx_l4_wkup__ctrl_module_wkup,
4839 &omap44xx_l4_wkup__ctrl_module_pad_wkup,
4840 &omap44xx_l3_instr__debugss,
4841 &omap44xx_l4_cfg__dma_system,
4842 &omap44xx_l4_abe__dmic,
4843 &omap44xx_l4_abe__dmic_dma,
4844 &omap44xx_dsp__iva,
4845 /* &omap44xx_dsp__sl2if, */
4846 &omap44xx_l4_cfg__dsp,
4847 &omap44xx_l3_main_2__dss,
4848 &omap44xx_l4_per__dss,
4849 &omap44xx_l3_main_2__dss_dispc,
4850 &omap44xx_l4_per__dss_dispc,
4851 &omap44xx_l3_main_2__dss_dsi1,
4852 &omap44xx_l4_per__dss_dsi1,
4853 &omap44xx_l3_main_2__dss_dsi2,
4854 &omap44xx_l4_per__dss_dsi2,
4855 &omap44xx_l3_main_2__dss_hdmi,
4856 &omap44xx_l4_per__dss_hdmi,
4857 &omap44xx_l3_main_2__dss_rfbi,
4858 &omap44xx_l4_per__dss_rfbi,
4859 &omap44xx_l3_main_2__dss_venc,
4860 &omap44xx_l4_per__dss_venc,
4861 &omap44xx_l4_per__elm,
4862 &omap44xx_l4_cfg__fdif,
4863 &omap44xx_l4_wkup__gpio1,
4864 &omap44xx_l4_per__gpio2,
4865 &omap44xx_l4_per__gpio3,
4866 &omap44xx_l4_per__gpio4,
4867 &omap44xx_l4_per__gpio5,
4868 &omap44xx_l4_per__gpio6,
4869 &omap44xx_l3_main_2__gpmc,
4870 &omap44xx_l3_main_2__gpu,
4871 &omap44xx_l4_per__hdq1w,
4872 &omap44xx_l4_cfg__hsi,
4873 &omap44xx_l4_per__i2c1,
4874 &omap44xx_l4_per__i2c2,
4875 &omap44xx_l4_per__i2c3,
4876 &omap44xx_l4_per__i2c4,
4877 &omap44xx_l3_main_2__ipu,
4878 &omap44xx_l3_main_2__iss,
4879 /* &omap44xx_iva__sl2if, */
4880 &omap44xx_l3_main_2__iva,
4881 &omap44xx_l4_wkup__kbd,
4882 &omap44xx_l4_cfg__mailbox,
4883 &omap44xx_l4_abe__mcasp,
4884 &omap44xx_l4_abe__mcasp_dma,
4885 &omap44xx_l4_abe__mcbsp1,
4886 &omap44xx_l4_abe__mcbsp1_dma,
4887 &omap44xx_l4_abe__mcbsp2,
4888 &omap44xx_l4_abe__mcbsp2_dma,
4889 &omap44xx_l4_abe__mcbsp3,
4890 &omap44xx_l4_abe__mcbsp3_dma,
4891 &omap44xx_l4_per__mcbsp4,
4892 &omap44xx_l4_abe__mcpdm,
4893 &omap44xx_l4_abe__mcpdm_dma,
4894 &omap44xx_l4_per__mcspi1,
4895 &omap44xx_l4_per__mcspi2,
4896 &omap44xx_l4_per__mcspi3,
4897 &omap44xx_l4_per__mcspi4,
4898 &omap44xx_l4_per__mmc1,
4899 &omap44xx_l4_per__mmc2,
4900 &omap44xx_l4_per__mmc3,
4901 &omap44xx_l4_per__mmc4,
4902 &omap44xx_l4_per__mmc5,
4903 &omap44xx_l3_main_2__mmu_ipu,
4904 &omap44xx_l4_cfg__mmu_dsp,
4905 &omap44xx_l3_main_2__ocmc_ram,
4906 &omap44xx_l4_cfg__ocp2scp_usb_phy,
4907 &omap44xx_mpu_private__prcm_mpu,
4908 &omap44xx_l4_wkup__cm_core_aon,
4909 &omap44xx_l4_cfg__cm_core,
4910 &omap44xx_l4_wkup__prm,
4911 &omap44xx_l4_wkup__scrm,
4912 /* &omap44xx_l3_main_2__sl2if, */
4913 &omap44xx_l4_abe__slimbus1,
4914 &omap44xx_l4_abe__slimbus1_dma,
4915 &omap44xx_l4_per__slimbus2,
4916 &omap44xx_l4_cfg__smartreflex_core,
4917 &omap44xx_l4_cfg__smartreflex_iva,
4918 &omap44xx_l4_cfg__smartreflex_mpu,
4919 &omap44xx_l4_cfg__spinlock,
4920 &omap44xx_l4_wkup__timer1,
4921 &omap44xx_l4_per__timer2,
4922 &omap44xx_l4_per__timer3,
4923 &omap44xx_l4_per__timer4,
4924 &omap44xx_l4_abe__timer5,
4925 &omap44xx_l4_abe__timer5_dma,
4926 &omap44xx_l4_abe__timer6,
4927 &omap44xx_l4_abe__timer6_dma,
4928 &omap44xx_l4_abe__timer7,
4929 &omap44xx_l4_abe__timer7_dma,
4930 &omap44xx_l4_abe__timer8,
4931 &omap44xx_l4_abe__timer8_dma,
4932 &omap44xx_l4_per__timer9,
4933 &omap44xx_l4_per__timer10,
4934 &omap44xx_l4_per__timer11,
4935 &omap44xx_l4_per__uart1,
4936 &omap44xx_l4_per__uart2,
4937 &omap44xx_l4_per__uart3,
4938 &omap44xx_l4_per__uart4,
4939 /* &omap44xx_l4_cfg__usb_host_fs, */
4940 &omap44xx_l4_cfg__usb_host_hs,
4941 &omap44xx_l4_cfg__usb_otg_hs,
4942 &omap44xx_l4_cfg__usb_tll_hs,
4943 &omap44xx_l4_wkup__wd_timer2,
4944 &omap44xx_l4_abe__wd_timer3,
4945 &omap44xx_l4_abe__wd_timer3_dma,
4946 &omap44xx_mpu__emif1,
4947 &omap44xx_mpu__emif2,
4948 NULL,
4949 };
4950
4951 int __init omap44xx_hwmod_init(void)
4952 {
4953 omap_hwmod_init();
4954 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
4955 }
4956
Linux kernel - Deliverables
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