2 * Hardware modules present on the OMAP44xx chips
4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
22 #include <linux/power/smartreflex.h>
24 #include <plat/omap_hwmod.h>
27 #include <plat/gpio.h>
29 #include <plat/mcspi.h>
30 #include <plat/mcbsp.h>
32 #include <plat/dmtimer.h>
33 #include <plat/common.h>
35 #include "omap_hwmod_common_data.h"
39 #include "prm-regbits-44xx.h"
42 /* Base offset for all OMAP4 interrupts external to MPUSS */
43 #define OMAP44XX_IRQ_GIC_START 32
45 /* Base offset for all OMAP4 dma requests */
46 #define OMAP44XX_DMA_REQ_START 1
53 * 'c2c_target_fw' class
54 * instance(s): c2c_target_fw
56 static struct omap_hwmod_class omap44xx_c2c_target_fw_hwmod_class
= {
57 .name
= "c2c_target_fw",
61 static struct omap_hwmod omap44xx_c2c_target_fw_hwmod
= {
62 .name
= "c2c_target_fw",
63 .class = &omap44xx_c2c_target_fw_hwmod_class
,
64 .clkdm_name
= "d2d_clkdm",
67 .clkctrl_offs
= OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET
,
68 .context_offs
= OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET
,
77 static struct omap_hwmod_class omap44xx_dmm_hwmod_class
= {
82 static struct omap_hwmod_irq_info omap44xx_dmm_irqs
[] = {
83 { .irq
= 113 + OMAP44XX_IRQ_GIC_START
},
87 static struct omap_hwmod omap44xx_dmm_hwmod
= {
89 .class = &omap44xx_dmm_hwmod_class
,
90 .clkdm_name
= "l3_emif_clkdm",
91 .mpu_irqs
= omap44xx_dmm_irqs
,
94 .clkctrl_offs
= OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET
,
95 .context_offs
= OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET
,
102 * instance(s): emif_fw
104 static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class
= {
109 static struct omap_hwmod omap44xx_emif_fw_hwmod
= {
111 .class = &omap44xx_emif_fw_hwmod_class
,
112 .clkdm_name
= "l3_emif_clkdm",
115 .clkctrl_offs
= OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET
,
116 .context_offs
= OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET
,
123 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
125 static struct omap_hwmod_class omap44xx_l3_hwmod_class
= {
130 static struct omap_hwmod omap44xx_l3_instr_hwmod
= {
132 .class = &omap44xx_l3_hwmod_class
,
133 .clkdm_name
= "l3_instr_clkdm",
136 .clkctrl_offs
= OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET
,
137 .context_offs
= OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET
,
138 .modulemode
= MODULEMODE_HWCTRL
,
144 static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs
[] = {
145 { .name
= "dbg_err", .irq
= 9 + OMAP44XX_IRQ_GIC_START
},
146 { .name
= "app_err", .irq
= 10 + OMAP44XX_IRQ_GIC_START
},
150 static struct omap_hwmod omap44xx_l3_main_1_hwmod
= {
152 .class = &omap44xx_l3_hwmod_class
,
153 .clkdm_name
= "l3_1_clkdm",
154 .mpu_irqs
= omap44xx_l3_main_1_irqs
,
157 .clkctrl_offs
= OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET
,
158 .context_offs
= OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET
,
164 static struct omap_hwmod omap44xx_l3_main_2_hwmod
= {
166 .class = &omap44xx_l3_hwmod_class
,
167 .clkdm_name
= "l3_2_clkdm",
170 .clkctrl_offs
= OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET
,
171 .context_offs
= OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET
,
177 static struct omap_hwmod omap44xx_l3_main_3_hwmod
= {
179 .class = &omap44xx_l3_hwmod_class
,
180 .clkdm_name
= "l3_instr_clkdm",
183 .clkctrl_offs
= OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET
,
184 .context_offs
= OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET
,
185 .modulemode
= MODULEMODE_HWCTRL
,
192 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
194 static struct omap_hwmod_class omap44xx_l4_hwmod_class
= {
199 static struct omap_hwmod omap44xx_l4_abe_hwmod
= {
201 .class = &omap44xx_l4_hwmod_class
,
202 .clkdm_name
= "abe_clkdm",
205 .clkctrl_offs
= OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET
,
211 static struct omap_hwmod omap44xx_l4_cfg_hwmod
= {
213 .class = &omap44xx_l4_hwmod_class
,
214 .clkdm_name
= "l4_cfg_clkdm",
217 .clkctrl_offs
= OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET
,
218 .context_offs
= OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET
,
224 static struct omap_hwmod omap44xx_l4_per_hwmod
= {
226 .class = &omap44xx_l4_hwmod_class
,
227 .clkdm_name
= "l4_per_clkdm",
230 .clkctrl_offs
= OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET
,
231 .context_offs
= OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET
,
237 static struct omap_hwmod omap44xx_l4_wkup_hwmod
= {
239 .class = &omap44xx_l4_hwmod_class
,
240 .clkdm_name
= "l4_wkup_clkdm",
243 .clkctrl_offs
= OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET
,
244 .context_offs
= OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET
,
251 * instance(s): mpu_private
253 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class
= {
258 static struct omap_hwmod omap44xx_mpu_private_hwmod
= {
259 .name
= "mpu_private",
260 .class = &omap44xx_mpu_bus_hwmod_class
,
261 .clkdm_name
= "mpuss_clkdm",
266 * instance(s): ocp_wp_noc
268 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class
= {
269 .name
= "ocp_wp_noc",
273 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod
= {
274 .name
= "ocp_wp_noc",
275 .class = &omap44xx_ocp_wp_noc_hwmod_class
,
276 .clkdm_name
= "l3_instr_clkdm",
279 .clkctrl_offs
= OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET
,
280 .context_offs
= OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET
,
281 .modulemode
= MODULEMODE_HWCTRL
,
287 * Modules omap_hwmod structures
289 * The following IPs are excluded for the moment because:
290 * - They do not need an explicit SW control using omap_hwmod API.
291 * - They still need to be validated with the driver
292 * properly adapted to omap_hwmod / omap_device
299 * audio engine sub system
302 static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc
= {
305 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
),
306 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
307 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
|
308 MSTANDBY_SMART_WKUP
),
309 .sysc_fields
= &omap_hwmod_sysc_type2
,
312 static struct omap_hwmod_class omap44xx_aess_hwmod_class
= {
314 .sysc
= &omap44xx_aess_sysc
,
318 static struct omap_hwmod_irq_info omap44xx_aess_irqs
[] = {
319 { .irq
= 99 + OMAP44XX_IRQ_GIC_START
},
323 static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs
[] = {
324 { .name
= "fifo0", .dma_req
= 100 + OMAP44XX_DMA_REQ_START
},
325 { .name
= "fifo1", .dma_req
= 101 + OMAP44XX_DMA_REQ_START
},
326 { .name
= "fifo2", .dma_req
= 102 + OMAP44XX_DMA_REQ_START
},
327 { .name
= "fifo3", .dma_req
= 103 + OMAP44XX_DMA_REQ_START
},
328 { .name
= "fifo4", .dma_req
= 104 + OMAP44XX_DMA_REQ_START
},
329 { .name
= "fifo5", .dma_req
= 105 + OMAP44XX_DMA_REQ_START
},
330 { .name
= "fifo6", .dma_req
= 106 + OMAP44XX_DMA_REQ_START
},
331 { .name
= "fifo7", .dma_req
= 107 + OMAP44XX_DMA_REQ_START
},
335 static struct omap_hwmod omap44xx_aess_hwmod
= {
337 .class = &omap44xx_aess_hwmod_class
,
338 .clkdm_name
= "abe_clkdm",
339 .mpu_irqs
= omap44xx_aess_irqs
,
340 .sdma_reqs
= omap44xx_aess_sdma_reqs
,
341 .main_clk
= "aess_fck",
344 .clkctrl_offs
= OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET
,
345 .context_offs
= OMAP4_RM_ABE_AESS_CONTEXT_OFFSET
,
346 .modulemode
= MODULEMODE_SWCTRL
,
353 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
357 static struct omap_hwmod_class omap44xx_c2c_hwmod_class
= {
362 static struct omap_hwmod_irq_info omap44xx_c2c_irqs
[] = {
363 { .irq
= 88 + OMAP44XX_IRQ_GIC_START
},
367 static struct omap_hwmod_dma_info omap44xx_c2c_sdma_reqs
[] = {
368 { .dma_req
= 68 + OMAP44XX_DMA_REQ_START
},
372 static struct omap_hwmod omap44xx_c2c_hwmod
= {
374 .class = &omap44xx_c2c_hwmod_class
,
375 .clkdm_name
= "d2d_clkdm",
376 .mpu_irqs
= omap44xx_c2c_irqs
,
377 .sdma_reqs
= omap44xx_c2c_sdma_reqs
,
380 .clkctrl_offs
= OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET
,
381 .context_offs
= OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET
,
388 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
391 static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc
= {
394 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
395 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
),
396 .sysc_fields
= &omap_hwmod_sysc_type1
,
399 static struct omap_hwmod_class omap44xx_counter_hwmod_class
= {
401 .sysc
= &omap44xx_counter_sysc
,
405 static struct omap_hwmod omap44xx_counter_32k_hwmod
= {
406 .name
= "counter_32k",
407 .class = &omap44xx_counter_hwmod_class
,
408 .clkdm_name
= "l4_wkup_clkdm",
409 .flags
= HWMOD_SWSUP_SIDLE
,
410 .main_clk
= "sys_32k_ck",
413 .clkctrl_offs
= OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET
,
414 .context_offs
= OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET
,
420 * 'ctrl_module' class
421 * attila core control module + core pad control module + wkup pad control
422 * module + attila wkup control module
425 static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc
= {
428 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
429 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
431 .sysc_fields
= &omap_hwmod_sysc_type2
,
434 static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class
= {
435 .name
= "ctrl_module",
436 .sysc
= &omap44xx_ctrl_module_sysc
,
439 /* ctrl_module_core */
440 static struct omap_hwmod_irq_info omap44xx_ctrl_module_core_irqs
[] = {
441 { .irq
= 8 + OMAP44XX_IRQ_GIC_START
},
445 static struct omap_hwmod omap44xx_ctrl_module_core_hwmod
= {
446 .name
= "ctrl_module_core",
447 .class = &omap44xx_ctrl_module_hwmod_class
,
448 .clkdm_name
= "l4_cfg_clkdm",
449 .mpu_irqs
= omap44xx_ctrl_module_core_irqs
,
452 /* ctrl_module_pad_core */
453 static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod
= {
454 .name
= "ctrl_module_pad_core",
455 .class = &omap44xx_ctrl_module_hwmod_class
,
456 .clkdm_name
= "l4_cfg_clkdm",
459 /* ctrl_module_wkup */
460 static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod
= {
461 .name
= "ctrl_module_wkup",
462 .class = &omap44xx_ctrl_module_hwmod_class
,
463 .clkdm_name
= "l4_wkup_clkdm",
466 /* ctrl_module_pad_wkup */
467 static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod
= {
468 .name
= "ctrl_module_pad_wkup",
469 .class = &omap44xx_ctrl_module_hwmod_class
,
470 .clkdm_name
= "l4_wkup_clkdm",
475 * debug and emulation sub system
478 static struct omap_hwmod_class omap44xx_debugss_hwmod_class
= {
483 static struct omap_hwmod omap44xx_debugss_hwmod
= {
485 .class = &omap44xx_debugss_hwmod_class
,
486 .clkdm_name
= "emu_sys_clkdm",
487 .main_clk
= "trace_clk_div_ck",
490 .clkctrl_offs
= OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET
,
491 .context_offs
= OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET
,
498 * dma controller for data exchange between memory to memory (i.e. internal or
499 * external memory) and gp peripherals to memory or memory to gp peripherals
502 static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc
= {
506 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
507 SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
508 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
509 SYSS_HAS_RESET_STATUS
),
510 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
511 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
512 .sysc_fields
= &omap_hwmod_sysc_type1
,
515 static struct omap_hwmod_class omap44xx_dma_hwmod_class
= {
517 .sysc
= &omap44xx_dma_sysc
,
521 static struct omap_dma_dev_attr dma_dev_attr
= {
522 .dev_caps
= RESERVE_CHANNEL
| DMA_LINKED_LCH
| GLOBAL_PRIORITY
|
523 IS_CSSA_32
| IS_CDSA_32
| IS_RW_PRIORITY
,
528 static struct omap_hwmod_irq_info omap44xx_dma_system_irqs
[] = {
529 { .name
= "0", .irq
= 12 + OMAP44XX_IRQ_GIC_START
},
530 { .name
= "1", .irq
= 13 + OMAP44XX_IRQ_GIC_START
},
531 { .name
= "2", .irq
= 14 + OMAP44XX_IRQ_GIC_START
},
532 { .name
= "3", .irq
= 15 + OMAP44XX_IRQ_GIC_START
},
536 static struct omap_hwmod omap44xx_dma_system_hwmod
= {
537 .name
= "dma_system",
538 .class = &omap44xx_dma_hwmod_class
,
539 .clkdm_name
= "l3_dma_clkdm",
540 .mpu_irqs
= omap44xx_dma_system_irqs
,
541 .main_clk
= "l3_div_ck",
544 .clkctrl_offs
= OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET
,
545 .context_offs
= OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET
,
548 .dev_attr
= &dma_dev_attr
,
553 * digital microphone controller
556 static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc
= {
559 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
560 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
561 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
563 .sysc_fields
= &omap_hwmod_sysc_type2
,
566 static struct omap_hwmod_class omap44xx_dmic_hwmod_class
= {
568 .sysc
= &omap44xx_dmic_sysc
,
572 static struct omap_hwmod_irq_info omap44xx_dmic_irqs
[] = {
573 { .irq
= 114 + OMAP44XX_IRQ_GIC_START
},
577 static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs
[] = {
578 { .dma_req
= 66 + OMAP44XX_DMA_REQ_START
},
582 static struct omap_hwmod omap44xx_dmic_hwmod
= {
584 .class = &omap44xx_dmic_hwmod_class
,
585 .clkdm_name
= "abe_clkdm",
586 .mpu_irqs
= omap44xx_dmic_irqs
,
587 .sdma_reqs
= omap44xx_dmic_sdma_reqs
,
588 .main_clk
= "dmic_fck",
591 .clkctrl_offs
= OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET
,
592 .context_offs
= OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET
,
593 .modulemode
= MODULEMODE_SWCTRL
,
603 static struct omap_hwmod_class omap44xx_dsp_hwmod_class
= {
608 static struct omap_hwmod_irq_info omap44xx_dsp_irqs
[] = {
609 { .irq
= 28 + OMAP44XX_IRQ_GIC_START
},
613 static struct omap_hwmod_rst_info omap44xx_dsp_resets
[] = {
614 { .name
= "dsp", .rst_shift
= 0 },
615 { .name
= "mmu_cache", .rst_shift
= 1 },
618 static struct omap_hwmod omap44xx_dsp_hwmod
= {
620 .class = &omap44xx_dsp_hwmod_class
,
621 .clkdm_name
= "tesla_clkdm",
622 .mpu_irqs
= omap44xx_dsp_irqs
,
623 .rst_lines
= omap44xx_dsp_resets
,
624 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_dsp_resets
),
625 .main_clk
= "dsp_fck",
628 .clkctrl_offs
= OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET
,
629 .rstctrl_offs
= OMAP4_RM_TESLA_RSTCTRL_OFFSET
,
630 .context_offs
= OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET
,
631 .modulemode
= MODULEMODE_HWCTRL
,
641 static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc
= {
644 .sysc_flags
= SYSS_HAS_RESET_STATUS
,
647 static struct omap_hwmod_class omap44xx_dss_hwmod_class
= {
649 .sysc
= &omap44xx_dss_sysc
,
650 .reset
= omap_dss_reset
,
654 static struct omap_hwmod_opt_clk dss_opt_clks
[] = {
655 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
656 { .role
= "tv_clk", .clk
= "dss_tv_clk" },
657 { .role
= "hdmi_clk", .clk
= "dss_48mhz_clk" },
660 static struct omap_hwmod omap44xx_dss_hwmod
= {
662 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
663 .class = &omap44xx_dss_hwmod_class
,
664 .clkdm_name
= "l3_dss_clkdm",
665 .main_clk
= "dss_dss_clk",
668 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
669 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
672 .opt_clks
= dss_opt_clks
,
673 .opt_clks_cnt
= ARRAY_SIZE(dss_opt_clks
),
681 static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc
= {
685 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
686 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_MIDLEMODE
|
687 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
688 SYSS_HAS_RESET_STATUS
),
689 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
690 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
691 .sysc_fields
= &omap_hwmod_sysc_type1
,
694 static struct omap_hwmod_class omap44xx_dispc_hwmod_class
= {
696 .sysc
= &omap44xx_dispc_sysc
,
700 static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs
[] = {
701 { .irq
= 25 + OMAP44XX_IRQ_GIC_START
},
705 static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs
[] = {
706 { .dma_req
= 5 + OMAP44XX_DMA_REQ_START
},
710 static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr
= {
712 .has_framedonetv_irq
= 1
715 static struct omap_hwmod omap44xx_dss_dispc_hwmod
= {
717 .class = &omap44xx_dispc_hwmod_class
,
718 .clkdm_name
= "l3_dss_clkdm",
719 .mpu_irqs
= omap44xx_dss_dispc_irqs
,
720 .sdma_reqs
= omap44xx_dss_dispc_sdma_reqs
,
721 .main_clk
= "dss_dss_clk",
724 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
725 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
728 .dev_attr
= &omap44xx_dss_dispc_dev_attr
733 * display serial interface controller
736 static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc
= {
740 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
741 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
742 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
743 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
744 .sysc_fields
= &omap_hwmod_sysc_type1
,
747 static struct omap_hwmod_class omap44xx_dsi_hwmod_class
= {
749 .sysc
= &omap44xx_dsi_sysc
,
753 static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs
[] = {
754 { .irq
= 53 + OMAP44XX_IRQ_GIC_START
},
758 static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs
[] = {
759 { .dma_req
= 74 + OMAP44XX_DMA_REQ_START
},
763 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks
[] = {
764 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
767 static struct omap_hwmod omap44xx_dss_dsi1_hwmod
= {
769 .class = &omap44xx_dsi_hwmod_class
,
770 .clkdm_name
= "l3_dss_clkdm",
771 .mpu_irqs
= omap44xx_dss_dsi1_irqs
,
772 .sdma_reqs
= omap44xx_dss_dsi1_sdma_reqs
,
773 .main_clk
= "dss_dss_clk",
776 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
777 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
780 .opt_clks
= dss_dsi1_opt_clks
,
781 .opt_clks_cnt
= ARRAY_SIZE(dss_dsi1_opt_clks
),
785 static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs
[] = {
786 { .irq
= 84 + OMAP44XX_IRQ_GIC_START
},
790 static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs
[] = {
791 { .dma_req
= 83 + OMAP44XX_DMA_REQ_START
},
795 static struct omap_hwmod_opt_clk dss_dsi2_opt_clks
[] = {
796 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
799 static struct omap_hwmod omap44xx_dss_dsi2_hwmod
= {
801 .class = &omap44xx_dsi_hwmod_class
,
802 .clkdm_name
= "l3_dss_clkdm",
803 .mpu_irqs
= omap44xx_dss_dsi2_irqs
,
804 .sdma_reqs
= omap44xx_dss_dsi2_sdma_reqs
,
805 .main_clk
= "dss_dss_clk",
808 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
809 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
812 .opt_clks
= dss_dsi2_opt_clks
,
813 .opt_clks_cnt
= ARRAY_SIZE(dss_dsi2_opt_clks
),
821 static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc
= {
824 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
826 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
828 .sysc_fields
= &omap_hwmod_sysc_type2
,
831 static struct omap_hwmod_class omap44xx_hdmi_hwmod_class
= {
833 .sysc
= &omap44xx_hdmi_sysc
,
837 static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs
[] = {
838 { .irq
= 101 + OMAP44XX_IRQ_GIC_START
},
842 static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs
[] = {
843 { .dma_req
= 75 + OMAP44XX_DMA_REQ_START
},
847 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks
[] = {
848 { .role
= "sys_clk", .clk
= "dss_sys_clk" },
851 static struct omap_hwmod omap44xx_dss_hdmi_hwmod
= {
853 .class = &omap44xx_hdmi_hwmod_class
,
854 .clkdm_name
= "l3_dss_clkdm",
856 * HDMI audio requires to use no-idle mode. Hence,
857 * set idle mode by software.
859 .flags
= HWMOD_SWSUP_SIDLE
,
860 .mpu_irqs
= omap44xx_dss_hdmi_irqs
,
861 .sdma_reqs
= omap44xx_dss_hdmi_sdma_reqs
,
862 .main_clk
= "dss_48mhz_clk",
865 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
866 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
869 .opt_clks
= dss_hdmi_opt_clks
,
870 .opt_clks_cnt
= ARRAY_SIZE(dss_hdmi_opt_clks
),
875 * remote frame buffer interface
878 static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc
= {
882 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
883 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
884 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
885 .sysc_fields
= &omap_hwmod_sysc_type1
,
888 static struct omap_hwmod_class omap44xx_rfbi_hwmod_class
= {
890 .sysc
= &omap44xx_rfbi_sysc
,
894 static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs
[] = {
895 { .dma_req
= 13 + OMAP44XX_DMA_REQ_START
},
899 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks
[] = {
900 { .role
= "ick", .clk
= "dss_fck" },
903 static struct omap_hwmod omap44xx_dss_rfbi_hwmod
= {
905 .class = &omap44xx_rfbi_hwmod_class
,
906 .clkdm_name
= "l3_dss_clkdm",
907 .sdma_reqs
= omap44xx_dss_rfbi_sdma_reqs
,
908 .main_clk
= "dss_dss_clk",
911 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
912 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
915 .opt_clks
= dss_rfbi_opt_clks
,
916 .opt_clks_cnt
= ARRAY_SIZE(dss_rfbi_opt_clks
),
924 static struct omap_hwmod_class omap44xx_venc_hwmod_class
= {
929 static struct omap_hwmod omap44xx_dss_venc_hwmod
= {
931 .class = &omap44xx_venc_hwmod_class
,
932 .clkdm_name
= "l3_dss_clkdm",
933 .main_clk
= "dss_tv_clk",
936 .clkctrl_offs
= OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET
,
937 .context_offs
= OMAP4_RM_DSS_DSS_CONTEXT_OFFSET
,
944 * bch error location module
947 static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc
= {
951 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
952 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
953 SYSS_HAS_RESET_STATUS
),
954 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
955 .sysc_fields
= &omap_hwmod_sysc_type1
,
958 static struct omap_hwmod_class omap44xx_elm_hwmod_class
= {
960 .sysc
= &omap44xx_elm_sysc
,
964 static struct omap_hwmod_irq_info omap44xx_elm_irqs
[] = {
965 { .irq
= 4 + OMAP44XX_IRQ_GIC_START
},
969 static struct omap_hwmod omap44xx_elm_hwmod
= {
971 .class = &omap44xx_elm_hwmod_class
,
972 .clkdm_name
= "l4_per_clkdm",
973 .mpu_irqs
= omap44xx_elm_irqs
,
976 .clkctrl_offs
= OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET
,
977 .context_offs
= OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET
,
984 * external memory interface no1
987 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc
= {
991 static struct omap_hwmod_class omap44xx_emif_hwmod_class
= {
993 .sysc
= &omap44xx_emif_sysc
,
997 static struct omap_hwmod_irq_info omap44xx_emif1_irqs
[] = {
998 { .irq
= 110 + OMAP44XX_IRQ_GIC_START
},
1002 static struct omap_hwmod omap44xx_emif1_hwmod
= {
1004 .class = &omap44xx_emif_hwmod_class
,
1005 .clkdm_name
= "l3_emif_clkdm",
1006 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1007 .mpu_irqs
= omap44xx_emif1_irqs
,
1008 .main_clk
= "ddrphy_ck",
1011 .clkctrl_offs
= OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET
,
1012 .context_offs
= OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET
,
1013 .modulemode
= MODULEMODE_HWCTRL
,
1019 static struct omap_hwmod_irq_info omap44xx_emif2_irqs
[] = {
1020 { .irq
= 111 + OMAP44XX_IRQ_GIC_START
},
1024 static struct omap_hwmod omap44xx_emif2_hwmod
= {
1026 .class = &omap44xx_emif_hwmod_class
,
1027 .clkdm_name
= "l3_emif_clkdm",
1028 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1029 .mpu_irqs
= omap44xx_emif2_irqs
,
1030 .main_clk
= "ddrphy_ck",
1033 .clkctrl_offs
= OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET
,
1034 .context_offs
= OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET
,
1035 .modulemode
= MODULEMODE_HWCTRL
,
1042 * face detection hw accelerator module
1045 static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc
= {
1047 .sysc_offs
= 0x0010,
1049 * FDIF needs 100 OCP clk cycles delay after a softreset before
1050 * accessing sysconfig again.
1051 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1052 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1054 * TODO: Indicate errata when available.
1057 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_RESET_STATUS
|
1058 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1059 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1060 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
1061 .sysc_fields
= &omap_hwmod_sysc_type2
,
1064 static struct omap_hwmod_class omap44xx_fdif_hwmod_class
= {
1066 .sysc
= &omap44xx_fdif_sysc
,
1070 static struct omap_hwmod_irq_info omap44xx_fdif_irqs
[] = {
1071 { .irq
= 69 + OMAP44XX_IRQ_GIC_START
},
1075 static struct omap_hwmod omap44xx_fdif_hwmod
= {
1077 .class = &omap44xx_fdif_hwmod_class
,
1078 .clkdm_name
= "iss_clkdm",
1079 .mpu_irqs
= omap44xx_fdif_irqs
,
1080 .main_clk
= "fdif_fck",
1083 .clkctrl_offs
= OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET
,
1084 .context_offs
= OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET
,
1085 .modulemode
= MODULEMODE_SWCTRL
,
1092 * general purpose io module
1095 static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc
= {
1097 .sysc_offs
= 0x0010,
1098 .syss_offs
= 0x0114,
1099 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
1100 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1101 SYSS_HAS_RESET_STATUS
),
1102 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1104 .sysc_fields
= &omap_hwmod_sysc_type1
,
1107 static struct omap_hwmod_class omap44xx_gpio_hwmod_class
= {
1109 .sysc
= &omap44xx_gpio_sysc
,
1114 static struct omap_gpio_dev_attr gpio_dev_attr
= {
1120 static struct omap_hwmod_irq_info omap44xx_gpio1_irqs
[] = {
1121 { .irq
= 29 + OMAP44XX_IRQ_GIC_START
},
1125 static struct omap_hwmod_opt_clk gpio1_opt_clks
[] = {
1126 { .role
= "dbclk", .clk
= "gpio1_dbclk" },
1129 static struct omap_hwmod omap44xx_gpio1_hwmod
= {
1131 .class = &omap44xx_gpio_hwmod_class
,
1132 .clkdm_name
= "l4_wkup_clkdm",
1133 .mpu_irqs
= omap44xx_gpio1_irqs
,
1134 .main_clk
= "gpio1_ick",
1137 .clkctrl_offs
= OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET
,
1138 .context_offs
= OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET
,
1139 .modulemode
= MODULEMODE_HWCTRL
,
1142 .opt_clks
= gpio1_opt_clks
,
1143 .opt_clks_cnt
= ARRAY_SIZE(gpio1_opt_clks
),
1144 .dev_attr
= &gpio_dev_attr
,
1148 static struct omap_hwmod_irq_info omap44xx_gpio2_irqs
[] = {
1149 { .irq
= 30 + OMAP44XX_IRQ_GIC_START
},
1153 static struct omap_hwmod_opt_clk gpio2_opt_clks
[] = {
1154 { .role
= "dbclk", .clk
= "gpio2_dbclk" },
1157 static struct omap_hwmod omap44xx_gpio2_hwmod
= {
1159 .class = &omap44xx_gpio_hwmod_class
,
1160 .clkdm_name
= "l4_per_clkdm",
1161 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1162 .mpu_irqs
= omap44xx_gpio2_irqs
,
1163 .main_clk
= "gpio2_ick",
1166 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET
,
1167 .context_offs
= OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET
,
1168 .modulemode
= MODULEMODE_HWCTRL
,
1171 .opt_clks
= gpio2_opt_clks
,
1172 .opt_clks_cnt
= ARRAY_SIZE(gpio2_opt_clks
),
1173 .dev_attr
= &gpio_dev_attr
,
1177 static struct omap_hwmod_irq_info omap44xx_gpio3_irqs
[] = {
1178 { .irq
= 31 + OMAP44XX_IRQ_GIC_START
},
1182 static struct omap_hwmod_opt_clk gpio3_opt_clks
[] = {
1183 { .role
= "dbclk", .clk
= "gpio3_dbclk" },
1186 static struct omap_hwmod omap44xx_gpio3_hwmod
= {
1188 .class = &omap44xx_gpio_hwmod_class
,
1189 .clkdm_name
= "l4_per_clkdm",
1190 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1191 .mpu_irqs
= omap44xx_gpio3_irqs
,
1192 .main_clk
= "gpio3_ick",
1195 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET
,
1196 .context_offs
= OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET
,
1197 .modulemode
= MODULEMODE_HWCTRL
,
1200 .opt_clks
= gpio3_opt_clks
,
1201 .opt_clks_cnt
= ARRAY_SIZE(gpio3_opt_clks
),
1202 .dev_attr
= &gpio_dev_attr
,
1206 static struct omap_hwmod_irq_info omap44xx_gpio4_irqs
[] = {
1207 { .irq
= 32 + OMAP44XX_IRQ_GIC_START
},
1211 static struct omap_hwmod_opt_clk gpio4_opt_clks
[] = {
1212 { .role
= "dbclk", .clk
= "gpio4_dbclk" },
1215 static struct omap_hwmod omap44xx_gpio4_hwmod
= {
1217 .class = &omap44xx_gpio_hwmod_class
,
1218 .clkdm_name
= "l4_per_clkdm",
1219 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1220 .mpu_irqs
= omap44xx_gpio4_irqs
,
1221 .main_clk
= "gpio4_ick",
1224 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET
,
1225 .context_offs
= OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET
,
1226 .modulemode
= MODULEMODE_HWCTRL
,
1229 .opt_clks
= gpio4_opt_clks
,
1230 .opt_clks_cnt
= ARRAY_SIZE(gpio4_opt_clks
),
1231 .dev_attr
= &gpio_dev_attr
,
1235 static struct omap_hwmod_irq_info omap44xx_gpio5_irqs
[] = {
1236 { .irq
= 33 + OMAP44XX_IRQ_GIC_START
},
1240 static struct omap_hwmod_opt_clk gpio5_opt_clks
[] = {
1241 { .role
= "dbclk", .clk
= "gpio5_dbclk" },
1244 static struct omap_hwmod omap44xx_gpio5_hwmod
= {
1246 .class = &omap44xx_gpio_hwmod_class
,
1247 .clkdm_name
= "l4_per_clkdm",
1248 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1249 .mpu_irqs
= omap44xx_gpio5_irqs
,
1250 .main_clk
= "gpio5_ick",
1253 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET
,
1254 .context_offs
= OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET
,
1255 .modulemode
= MODULEMODE_HWCTRL
,
1258 .opt_clks
= gpio5_opt_clks
,
1259 .opt_clks_cnt
= ARRAY_SIZE(gpio5_opt_clks
),
1260 .dev_attr
= &gpio_dev_attr
,
1264 static struct omap_hwmod_irq_info omap44xx_gpio6_irqs
[] = {
1265 { .irq
= 34 + OMAP44XX_IRQ_GIC_START
},
1269 static struct omap_hwmod_opt_clk gpio6_opt_clks
[] = {
1270 { .role
= "dbclk", .clk
= "gpio6_dbclk" },
1273 static struct omap_hwmod omap44xx_gpio6_hwmod
= {
1275 .class = &omap44xx_gpio_hwmod_class
,
1276 .clkdm_name
= "l4_per_clkdm",
1277 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
1278 .mpu_irqs
= omap44xx_gpio6_irqs
,
1279 .main_clk
= "gpio6_ick",
1282 .clkctrl_offs
= OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET
,
1283 .context_offs
= OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET
,
1284 .modulemode
= MODULEMODE_HWCTRL
,
1287 .opt_clks
= gpio6_opt_clks
,
1288 .opt_clks_cnt
= ARRAY_SIZE(gpio6_opt_clks
),
1289 .dev_attr
= &gpio_dev_attr
,
1294 * general purpose memory controller
1297 static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc
= {
1299 .sysc_offs
= 0x0010,
1300 .syss_offs
= 0x0014,
1301 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
1302 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1303 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1304 .sysc_fields
= &omap_hwmod_sysc_type1
,
1307 static struct omap_hwmod_class omap44xx_gpmc_hwmod_class
= {
1309 .sysc
= &omap44xx_gpmc_sysc
,
1313 static struct omap_hwmod_irq_info omap44xx_gpmc_irqs
[] = {
1314 { .irq
= 20 + OMAP44XX_IRQ_GIC_START
},
1318 static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs
[] = {
1319 { .dma_req
= 3 + OMAP44XX_DMA_REQ_START
},
1323 static struct omap_hwmod omap44xx_gpmc_hwmod
= {
1325 .class = &omap44xx_gpmc_hwmod_class
,
1326 .clkdm_name
= "l3_2_clkdm",
1327 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1328 .mpu_irqs
= omap44xx_gpmc_irqs
,
1329 .sdma_reqs
= omap44xx_gpmc_sdma_reqs
,
1332 .clkctrl_offs
= OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET
,
1333 .context_offs
= OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET
,
1334 .modulemode
= MODULEMODE_HWCTRL
,
1341 * 2d/3d graphics accelerator
1344 static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc
= {
1345 .rev_offs
= 0x1fc00,
1346 .sysc_offs
= 0x1fc10,
1347 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
),
1348 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1349 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1350 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1351 .sysc_fields
= &omap_hwmod_sysc_type2
,
1354 static struct omap_hwmod_class omap44xx_gpu_hwmod_class
= {
1356 .sysc
= &omap44xx_gpu_sysc
,
1360 static struct omap_hwmod_irq_info omap44xx_gpu_irqs
[] = {
1361 { .irq
= 21 + OMAP44XX_IRQ_GIC_START
},
1365 static struct omap_hwmod omap44xx_gpu_hwmod
= {
1367 .class = &omap44xx_gpu_hwmod_class
,
1368 .clkdm_name
= "l3_gfx_clkdm",
1369 .mpu_irqs
= omap44xx_gpu_irqs
,
1370 .main_clk
= "gpu_fck",
1373 .clkctrl_offs
= OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET
,
1374 .context_offs
= OMAP4_RM_GFX_GFX_CONTEXT_OFFSET
,
1375 .modulemode
= MODULEMODE_SWCTRL
,
1382 * hdq / 1-wire serial interface controller
1385 static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc
= {
1387 .sysc_offs
= 0x0014,
1388 .syss_offs
= 0x0018,
1389 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SOFTRESET
|
1390 SYSS_HAS_RESET_STATUS
),
1391 .sysc_fields
= &omap_hwmod_sysc_type1
,
1394 static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class
= {
1396 .sysc
= &omap44xx_hdq1w_sysc
,
1400 static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs
[] = {
1401 { .irq
= 58 + OMAP44XX_IRQ_GIC_START
},
1405 static struct omap_hwmod omap44xx_hdq1w_hwmod
= {
1407 .class = &omap44xx_hdq1w_hwmod_class
,
1408 .clkdm_name
= "l4_per_clkdm",
1409 .flags
= HWMOD_INIT_NO_RESET
, /* XXX temporary */
1410 .mpu_irqs
= omap44xx_hdq1w_irqs
,
1411 .main_clk
= "hdq1w_fck",
1414 .clkctrl_offs
= OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET
,
1415 .context_offs
= OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET
,
1416 .modulemode
= MODULEMODE_SWCTRL
,
1423 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1427 static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc
= {
1429 .sysc_offs
= 0x0010,
1430 .syss_offs
= 0x0014,
1431 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_EMUFREE
|
1432 SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
1433 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1434 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1435 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1436 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1437 .sysc_fields
= &omap_hwmod_sysc_type1
,
1440 static struct omap_hwmod_class omap44xx_hsi_hwmod_class
= {
1442 .sysc
= &omap44xx_hsi_sysc
,
1446 static struct omap_hwmod_irq_info omap44xx_hsi_irqs
[] = {
1447 { .name
= "mpu_p1", .irq
= 67 + OMAP44XX_IRQ_GIC_START
},
1448 { .name
= "mpu_p2", .irq
= 68 + OMAP44XX_IRQ_GIC_START
},
1449 { .name
= "mpu_dma", .irq
= 71 + OMAP44XX_IRQ_GIC_START
},
1453 static struct omap_hwmod omap44xx_hsi_hwmod
= {
1455 .class = &omap44xx_hsi_hwmod_class
,
1456 .clkdm_name
= "l3_init_clkdm",
1457 .mpu_irqs
= omap44xx_hsi_irqs
,
1458 .main_clk
= "hsi_fck",
1461 .clkctrl_offs
= OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET
,
1462 .context_offs
= OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET
,
1463 .modulemode
= MODULEMODE_HWCTRL
,
1470 * multimaster high-speed i2c controller
1473 static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc
= {
1474 .sysc_offs
= 0x0010,
1475 .syss_offs
= 0x0090,
1476 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
1477 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
1478 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1479 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1481 .clockact
= CLOCKACT_TEST_ICLK
,
1482 .sysc_fields
= &omap_hwmod_sysc_type1
,
1485 static struct omap_hwmod_class omap44xx_i2c_hwmod_class
= {
1487 .sysc
= &omap44xx_i2c_sysc
,
1488 .rev
= OMAP_I2C_IP_VERSION_2
,
1489 .reset
= &omap_i2c_reset
,
1492 static struct omap_i2c_dev_attr i2c_dev_attr
= {
1493 .flags
= OMAP_I2C_FLAG_BUS_SHIFT_NONE
|
1494 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE
,
1498 static struct omap_hwmod_irq_info omap44xx_i2c1_irqs
[] = {
1499 { .irq
= 56 + OMAP44XX_IRQ_GIC_START
},
1503 static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs
[] = {
1504 { .name
= "tx", .dma_req
= 26 + OMAP44XX_DMA_REQ_START
},
1505 { .name
= "rx", .dma_req
= 27 + OMAP44XX_DMA_REQ_START
},
1509 static struct omap_hwmod omap44xx_i2c1_hwmod
= {
1511 .class = &omap44xx_i2c_hwmod_class
,
1512 .clkdm_name
= "l4_per_clkdm",
1513 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1514 .mpu_irqs
= omap44xx_i2c1_irqs
,
1515 .sdma_reqs
= omap44xx_i2c1_sdma_reqs
,
1516 .main_clk
= "i2c1_fck",
1519 .clkctrl_offs
= OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET
,
1520 .context_offs
= OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET
,
1521 .modulemode
= MODULEMODE_SWCTRL
,
1524 .dev_attr
= &i2c_dev_attr
,
1528 static struct omap_hwmod_irq_info omap44xx_i2c2_irqs
[] = {
1529 { .irq
= 57 + OMAP44XX_IRQ_GIC_START
},
1533 static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs
[] = {
1534 { .name
= "tx", .dma_req
= 28 + OMAP44XX_DMA_REQ_START
},
1535 { .name
= "rx", .dma_req
= 29 + OMAP44XX_DMA_REQ_START
},
1539 static struct omap_hwmod omap44xx_i2c2_hwmod
= {
1541 .class = &omap44xx_i2c_hwmod_class
,
1542 .clkdm_name
= "l4_per_clkdm",
1543 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1544 .mpu_irqs
= omap44xx_i2c2_irqs
,
1545 .sdma_reqs
= omap44xx_i2c2_sdma_reqs
,
1546 .main_clk
= "i2c2_fck",
1549 .clkctrl_offs
= OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET
,
1550 .context_offs
= OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET
,
1551 .modulemode
= MODULEMODE_SWCTRL
,
1554 .dev_attr
= &i2c_dev_attr
,
1558 static struct omap_hwmod_irq_info omap44xx_i2c3_irqs
[] = {
1559 { .irq
= 61 + OMAP44XX_IRQ_GIC_START
},
1563 static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs
[] = {
1564 { .name
= "tx", .dma_req
= 24 + OMAP44XX_DMA_REQ_START
},
1565 { .name
= "rx", .dma_req
= 25 + OMAP44XX_DMA_REQ_START
},
1569 static struct omap_hwmod omap44xx_i2c3_hwmod
= {
1571 .class = &omap44xx_i2c_hwmod_class
,
1572 .clkdm_name
= "l4_per_clkdm",
1573 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1574 .mpu_irqs
= omap44xx_i2c3_irqs
,
1575 .sdma_reqs
= omap44xx_i2c3_sdma_reqs
,
1576 .main_clk
= "i2c3_fck",
1579 .clkctrl_offs
= OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET
,
1580 .context_offs
= OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET
,
1581 .modulemode
= MODULEMODE_SWCTRL
,
1584 .dev_attr
= &i2c_dev_attr
,
1588 static struct omap_hwmod_irq_info omap44xx_i2c4_irqs
[] = {
1589 { .irq
= 62 + OMAP44XX_IRQ_GIC_START
},
1593 static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs
[] = {
1594 { .name
= "tx", .dma_req
= 123 + OMAP44XX_DMA_REQ_START
},
1595 { .name
= "rx", .dma_req
= 124 + OMAP44XX_DMA_REQ_START
},
1599 static struct omap_hwmod omap44xx_i2c4_hwmod
= {
1601 .class = &omap44xx_i2c_hwmod_class
,
1602 .clkdm_name
= "l4_per_clkdm",
1603 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
1604 .mpu_irqs
= omap44xx_i2c4_irqs
,
1605 .sdma_reqs
= omap44xx_i2c4_sdma_reqs
,
1606 .main_clk
= "i2c4_fck",
1609 .clkctrl_offs
= OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET
,
1610 .context_offs
= OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET
,
1611 .modulemode
= MODULEMODE_SWCTRL
,
1614 .dev_attr
= &i2c_dev_attr
,
1619 * imaging processor unit
1622 static struct omap_hwmod_class omap44xx_ipu_hwmod_class
= {
1627 static struct omap_hwmod_irq_info omap44xx_ipu_irqs
[] = {
1628 { .irq
= 100 + OMAP44XX_IRQ_GIC_START
},
1632 static struct omap_hwmod_rst_info omap44xx_ipu_resets
[] = {
1633 { .name
= "cpu0", .rst_shift
= 0 },
1634 { .name
= "cpu1", .rst_shift
= 1 },
1635 { .name
= "mmu_cache", .rst_shift
= 2 },
1638 static struct omap_hwmod omap44xx_ipu_hwmod
= {
1640 .class = &omap44xx_ipu_hwmod_class
,
1641 .clkdm_name
= "ducati_clkdm",
1642 .mpu_irqs
= omap44xx_ipu_irqs
,
1643 .rst_lines
= omap44xx_ipu_resets
,
1644 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_ipu_resets
),
1645 .main_clk
= "ipu_fck",
1648 .clkctrl_offs
= OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET
,
1649 .rstctrl_offs
= OMAP4_RM_DUCATI_RSTCTRL_OFFSET
,
1650 .context_offs
= OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET
,
1651 .modulemode
= MODULEMODE_HWCTRL
,
1658 * external images sensor pixel data processor
1661 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc
= {
1663 .sysc_offs
= 0x0010,
1665 * ISS needs 100 OCP clk cycles delay after a softreset before
1666 * accessing sysconfig again.
1667 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1668 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1670 * TODO: Indicate errata when available.
1673 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_RESET_STATUS
|
1674 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1675 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1676 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1677 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1678 .sysc_fields
= &omap_hwmod_sysc_type2
,
1681 static struct omap_hwmod_class omap44xx_iss_hwmod_class
= {
1683 .sysc
= &omap44xx_iss_sysc
,
1687 static struct omap_hwmod_irq_info omap44xx_iss_irqs
[] = {
1688 { .irq
= 24 + OMAP44XX_IRQ_GIC_START
},
1692 static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs
[] = {
1693 { .name
= "1", .dma_req
= 8 + OMAP44XX_DMA_REQ_START
},
1694 { .name
= "2", .dma_req
= 9 + OMAP44XX_DMA_REQ_START
},
1695 { .name
= "3", .dma_req
= 11 + OMAP44XX_DMA_REQ_START
},
1696 { .name
= "4", .dma_req
= 12 + OMAP44XX_DMA_REQ_START
},
1700 static struct omap_hwmod_opt_clk iss_opt_clks
[] = {
1701 { .role
= "ctrlclk", .clk
= "iss_ctrlclk" },
1704 static struct omap_hwmod omap44xx_iss_hwmod
= {
1706 .class = &omap44xx_iss_hwmod_class
,
1707 .clkdm_name
= "iss_clkdm",
1708 .mpu_irqs
= omap44xx_iss_irqs
,
1709 .sdma_reqs
= omap44xx_iss_sdma_reqs
,
1710 .main_clk
= "iss_fck",
1713 .clkctrl_offs
= OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET
,
1714 .context_offs
= OMAP4_RM_CAM_ISS_CONTEXT_OFFSET
,
1715 .modulemode
= MODULEMODE_SWCTRL
,
1718 .opt_clks
= iss_opt_clks
,
1719 .opt_clks_cnt
= ARRAY_SIZE(iss_opt_clks
),
1724 * multi-standard video encoder/decoder hardware accelerator
1727 static struct omap_hwmod_class omap44xx_iva_hwmod_class
= {
1732 static struct omap_hwmod_irq_info omap44xx_iva_irqs
[] = {
1733 { .name
= "sync_1", .irq
= 103 + OMAP44XX_IRQ_GIC_START
},
1734 { .name
= "sync_0", .irq
= 104 + OMAP44XX_IRQ_GIC_START
},
1735 { .name
= "mailbox_0", .irq
= 107 + OMAP44XX_IRQ_GIC_START
},
1739 static struct omap_hwmod_rst_info omap44xx_iva_resets
[] = {
1740 { .name
= "seq0", .rst_shift
= 0 },
1741 { .name
= "seq1", .rst_shift
= 1 },
1742 { .name
= "logic", .rst_shift
= 2 },
1745 static struct omap_hwmod omap44xx_iva_hwmod
= {
1747 .class = &omap44xx_iva_hwmod_class
,
1748 .clkdm_name
= "ivahd_clkdm",
1749 .mpu_irqs
= omap44xx_iva_irqs
,
1750 .rst_lines
= omap44xx_iva_resets
,
1751 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_iva_resets
),
1752 .main_clk
= "iva_fck",
1755 .clkctrl_offs
= OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET
,
1756 .rstctrl_offs
= OMAP4_RM_IVAHD_RSTCTRL_OFFSET
,
1757 .context_offs
= OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET
,
1758 .modulemode
= MODULEMODE_HWCTRL
,
1765 * keyboard controller
1768 static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc
= {
1770 .sysc_offs
= 0x0010,
1771 .syss_offs
= 0x0014,
1772 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
1773 SYSC_HAS_EMUFREE
| SYSC_HAS_ENAWAKEUP
|
1774 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1775 SYSS_HAS_RESET_STATUS
),
1776 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1777 .sysc_fields
= &omap_hwmod_sysc_type1
,
1780 static struct omap_hwmod_class omap44xx_kbd_hwmod_class
= {
1782 .sysc
= &omap44xx_kbd_sysc
,
1786 static struct omap_hwmod_irq_info omap44xx_kbd_irqs
[] = {
1787 { .irq
= 120 + OMAP44XX_IRQ_GIC_START
},
1791 static struct omap_hwmod omap44xx_kbd_hwmod
= {
1793 .class = &omap44xx_kbd_hwmod_class
,
1794 .clkdm_name
= "l4_wkup_clkdm",
1795 .mpu_irqs
= omap44xx_kbd_irqs
,
1796 .main_clk
= "kbd_fck",
1799 .clkctrl_offs
= OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET
,
1800 .context_offs
= OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET
,
1801 .modulemode
= MODULEMODE_SWCTRL
,
1808 * mailbox module allowing communication between the on-chip processors using a
1809 * queued mailbox-interrupt mechanism.
1812 static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc
= {
1814 .sysc_offs
= 0x0010,
1815 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
1816 SYSC_HAS_SOFTRESET
),
1817 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1818 .sysc_fields
= &omap_hwmod_sysc_type2
,
1821 static struct omap_hwmod_class omap44xx_mailbox_hwmod_class
= {
1823 .sysc
= &omap44xx_mailbox_sysc
,
1827 static struct omap_hwmod_irq_info omap44xx_mailbox_irqs
[] = {
1828 { .irq
= 26 + OMAP44XX_IRQ_GIC_START
},
1832 static struct omap_hwmod omap44xx_mailbox_hwmod
= {
1834 .class = &omap44xx_mailbox_hwmod_class
,
1835 .clkdm_name
= "l4_cfg_clkdm",
1836 .mpu_irqs
= omap44xx_mailbox_irqs
,
1839 .clkctrl_offs
= OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET
,
1840 .context_offs
= OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET
,
1847 * multi-channel audio serial port controller
1850 /* The IP is not compliant to type1 / type2 scheme */
1851 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_mcasp
= {
1855 static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc
= {
1856 .sysc_offs
= 0x0004,
1857 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
1858 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1860 .sysc_fields
= &omap_hwmod_sysc_type_mcasp
,
1863 static struct omap_hwmod_class omap44xx_mcasp_hwmod_class
= {
1865 .sysc
= &omap44xx_mcasp_sysc
,
1869 static struct omap_hwmod_irq_info omap44xx_mcasp_irqs
[] = {
1870 { .name
= "arevt", .irq
= 108 + OMAP44XX_IRQ_GIC_START
},
1871 { .name
= "axevt", .irq
= 109 + OMAP44XX_IRQ_GIC_START
},
1875 static struct omap_hwmod_dma_info omap44xx_mcasp_sdma_reqs
[] = {
1876 { .name
= "axevt", .dma_req
= 7 + OMAP44XX_DMA_REQ_START
},
1877 { .name
= "arevt", .dma_req
= 10 + OMAP44XX_DMA_REQ_START
},
1881 static struct omap_hwmod omap44xx_mcasp_hwmod
= {
1883 .class = &omap44xx_mcasp_hwmod_class
,
1884 .clkdm_name
= "abe_clkdm",
1885 .mpu_irqs
= omap44xx_mcasp_irqs
,
1886 .sdma_reqs
= omap44xx_mcasp_sdma_reqs
,
1887 .main_clk
= "mcasp_fck",
1890 .clkctrl_offs
= OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET
,
1891 .context_offs
= OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET
,
1892 .modulemode
= MODULEMODE_SWCTRL
,
1899 * multi channel buffered serial port controller
1902 static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc
= {
1903 .sysc_offs
= 0x008c,
1904 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_ENAWAKEUP
|
1905 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1906 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1907 .sysc_fields
= &omap_hwmod_sysc_type1
,
1910 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class
= {
1912 .sysc
= &omap44xx_mcbsp_sysc
,
1913 .rev
= MCBSP_CONFIG_TYPE4
,
1917 static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs
[] = {
1918 { .name
= "common", .irq
= 17 + OMAP44XX_IRQ_GIC_START
},
1922 static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs
[] = {
1923 { .name
= "tx", .dma_req
= 32 + OMAP44XX_DMA_REQ_START
},
1924 { .name
= "rx", .dma_req
= 33 + OMAP44XX_DMA_REQ_START
},
1928 static struct omap_hwmod_opt_clk mcbsp1_opt_clks
[] = {
1929 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
1930 { .role
= "prcm_fck", .clk
= "mcbsp1_sync_mux_ck" },
1933 static struct omap_hwmod omap44xx_mcbsp1_hwmod
= {
1935 .class = &omap44xx_mcbsp_hwmod_class
,
1936 .clkdm_name
= "abe_clkdm",
1937 .mpu_irqs
= omap44xx_mcbsp1_irqs
,
1938 .sdma_reqs
= omap44xx_mcbsp1_sdma_reqs
,
1939 .main_clk
= "mcbsp1_fck",
1942 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET
,
1943 .context_offs
= OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET
,
1944 .modulemode
= MODULEMODE_SWCTRL
,
1947 .opt_clks
= mcbsp1_opt_clks
,
1948 .opt_clks_cnt
= ARRAY_SIZE(mcbsp1_opt_clks
),
1952 static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs
[] = {
1953 { .name
= "common", .irq
= 22 + OMAP44XX_IRQ_GIC_START
},
1957 static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs
[] = {
1958 { .name
= "tx", .dma_req
= 16 + OMAP44XX_DMA_REQ_START
},
1959 { .name
= "rx", .dma_req
= 17 + OMAP44XX_DMA_REQ_START
},
1963 static struct omap_hwmod_opt_clk mcbsp2_opt_clks
[] = {
1964 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
1965 { .role
= "prcm_fck", .clk
= "mcbsp2_sync_mux_ck" },
1968 static struct omap_hwmod omap44xx_mcbsp2_hwmod
= {
1970 .class = &omap44xx_mcbsp_hwmod_class
,
1971 .clkdm_name
= "abe_clkdm",
1972 .mpu_irqs
= omap44xx_mcbsp2_irqs
,
1973 .sdma_reqs
= omap44xx_mcbsp2_sdma_reqs
,
1974 .main_clk
= "mcbsp2_fck",
1977 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET
,
1978 .context_offs
= OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET
,
1979 .modulemode
= MODULEMODE_SWCTRL
,
1982 .opt_clks
= mcbsp2_opt_clks
,
1983 .opt_clks_cnt
= ARRAY_SIZE(mcbsp2_opt_clks
),
1987 static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs
[] = {
1988 { .name
= "common", .irq
= 23 + OMAP44XX_IRQ_GIC_START
},
1992 static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs
[] = {
1993 { .name
= "tx", .dma_req
= 18 + OMAP44XX_DMA_REQ_START
},
1994 { .name
= "rx", .dma_req
= 19 + OMAP44XX_DMA_REQ_START
},
1998 static struct omap_hwmod_opt_clk mcbsp3_opt_clks
[] = {
1999 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
2000 { .role
= "prcm_fck", .clk
= "mcbsp3_sync_mux_ck" },
2003 static struct omap_hwmod omap44xx_mcbsp3_hwmod
= {
2005 .class = &omap44xx_mcbsp_hwmod_class
,
2006 .clkdm_name
= "abe_clkdm",
2007 .mpu_irqs
= omap44xx_mcbsp3_irqs
,
2008 .sdma_reqs
= omap44xx_mcbsp3_sdma_reqs
,
2009 .main_clk
= "mcbsp3_fck",
2012 .clkctrl_offs
= OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET
,
2013 .context_offs
= OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET
,
2014 .modulemode
= MODULEMODE_SWCTRL
,
2017 .opt_clks
= mcbsp3_opt_clks
,
2018 .opt_clks_cnt
= ARRAY_SIZE(mcbsp3_opt_clks
),
2022 static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs
[] = {
2023 { .name
= "common", .irq
= 16 + OMAP44XX_IRQ_GIC_START
},
2027 static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs
[] = {
2028 { .name
= "tx", .dma_req
= 30 + OMAP44XX_DMA_REQ_START
},
2029 { .name
= "rx", .dma_req
= 31 + OMAP44XX_DMA_REQ_START
},
2033 static struct omap_hwmod_opt_clk mcbsp4_opt_clks
[] = {
2034 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
2035 { .role
= "prcm_fck", .clk
= "mcbsp4_sync_mux_ck" },
2038 static struct omap_hwmod omap44xx_mcbsp4_hwmod
= {
2040 .class = &omap44xx_mcbsp_hwmod_class
,
2041 .clkdm_name
= "l4_per_clkdm",
2042 .mpu_irqs
= omap44xx_mcbsp4_irqs
,
2043 .sdma_reqs
= omap44xx_mcbsp4_sdma_reqs
,
2044 .main_clk
= "mcbsp4_fck",
2047 .clkctrl_offs
= OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET
,
2048 .context_offs
= OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET
,
2049 .modulemode
= MODULEMODE_SWCTRL
,
2052 .opt_clks
= mcbsp4_opt_clks
,
2053 .opt_clks_cnt
= ARRAY_SIZE(mcbsp4_opt_clks
),
2058 * multi channel pdm controller (proprietary interface with phoenix power
2062 static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc
= {
2064 .sysc_offs
= 0x0010,
2065 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
2066 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
2067 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2069 .sysc_fields
= &omap_hwmod_sysc_type2
,
2072 static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class
= {
2074 .sysc
= &omap44xx_mcpdm_sysc
,
2078 static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs
[] = {
2079 { .irq
= 112 + OMAP44XX_IRQ_GIC_START
},
2083 static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs
[] = {
2084 { .name
= "up_link", .dma_req
= 64 + OMAP44XX_DMA_REQ_START
},
2085 { .name
= "dn_link", .dma_req
= 65 + OMAP44XX_DMA_REQ_START
},
2089 static struct omap_hwmod omap44xx_mcpdm_hwmod
= {
2091 .class = &omap44xx_mcpdm_hwmod_class
,
2092 .clkdm_name
= "abe_clkdm",
2093 .mpu_irqs
= omap44xx_mcpdm_irqs
,
2094 .sdma_reqs
= omap44xx_mcpdm_sdma_reqs
,
2095 .main_clk
= "mcpdm_fck",
2098 .clkctrl_offs
= OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET
,
2099 .context_offs
= OMAP4_RM_ABE_PDM_CONTEXT_OFFSET
,
2100 .modulemode
= MODULEMODE_SWCTRL
,
2107 * multichannel serial port interface (mcspi) / master/slave synchronous serial
2111 static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc
= {
2113 .sysc_offs
= 0x0010,
2114 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
2115 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
2116 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2118 .sysc_fields
= &omap_hwmod_sysc_type2
,
2121 static struct omap_hwmod_class omap44xx_mcspi_hwmod_class
= {
2123 .sysc
= &omap44xx_mcspi_sysc
,
2124 .rev
= OMAP4_MCSPI_REV
,
2128 static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs
[] = {
2129 { .irq
= 65 + OMAP44XX_IRQ_GIC_START
},
2133 static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs
[] = {
2134 { .name
= "tx0", .dma_req
= 34 + OMAP44XX_DMA_REQ_START
},
2135 { .name
= "rx0", .dma_req
= 35 + OMAP44XX_DMA_REQ_START
},
2136 { .name
= "tx1", .dma_req
= 36 + OMAP44XX_DMA_REQ_START
},
2137 { .name
= "rx1", .dma_req
= 37 + OMAP44XX_DMA_REQ_START
},
2138 { .name
= "tx2", .dma_req
= 38 + OMAP44XX_DMA_REQ_START
},
2139 { .name
= "rx2", .dma_req
= 39 + OMAP44XX_DMA_REQ_START
},
2140 { .name
= "tx3", .dma_req
= 40 + OMAP44XX_DMA_REQ_START
},
2141 { .name
= "rx3", .dma_req
= 41 + OMAP44XX_DMA_REQ_START
},
2145 /* mcspi1 dev_attr */
2146 static struct omap2_mcspi_dev_attr mcspi1_dev_attr
= {
2147 .num_chipselect
= 4,
2150 static struct omap_hwmod omap44xx_mcspi1_hwmod
= {
2152 .class = &omap44xx_mcspi_hwmod_class
,
2153 .clkdm_name
= "l4_per_clkdm",
2154 .mpu_irqs
= omap44xx_mcspi1_irqs
,
2155 .sdma_reqs
= omap44xx_mcspi1_sdma_reqs
,
2156 .main_clk
= "mcspi1_fck",
2159 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET
,
2160 .context_offs
= OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET
,
2161 .modulemode
= MODULEMODE_SWCTRL
,
2164 .dev_attr
= &mcspi1_dev_attr
,
2168 static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs
[] = {
2169 { .irq
= 66 + OMAP44XX_IRQ_GIC_START
},
2173 static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs
[] = {
2174 { .name
= "tx0", .dma_req
= 42 + OMAP44XX_DMA_REQ_START
},
2175 { .name
= "rx0", .dma_req
= 43 + OMAP44XX_DMA_REQ_START
},
2176 { .name
= "tx1", .dma_req
= 44 + OMAP44XX_DMA_REQ_START
},
2177 { .name
= "rx1", .dma_req
= 45 + OMAP44XX_DMA_REQ_START
},
2181 /* mcspi2 dev_attr */
2182 static struct omap2_mcspi_dev_attr mcspi2_dev_attr
= {
2183 .num_chipselect
= 2,
2186 static struct omap_hwmod omap44xx_mcspi2_hwmod
= {
2188 .class = &omap44xx_mcspi_hwmod_class
,
2189 .clkdm_name
= "l4_per_clkdm",
2190 .mpu_irqs
= omap44xx_mcspi2_irqs
,
2191 .sdma_reqs
= omap44xx_mcspi2_sdma_reqs
,
2192 .main_clk
= "mcspi2_fck",
2195 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET
,
2196 .context_offs
= OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET
,
2197 .modulemode
= MODULEMODE_SWCTRL
,
2200 .dev_attr
= &mcspi2_dev_attr
,
2204 static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs
[] = {
2205 { .irq
= 91 + OMAP44XX_IRQ_GIC_START
},
2209 static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs
[] = {
2210 { .name
= "tx0", .dma_req
= 14 + OMAP44XX_DMA_REQ_START
},
2211 { .name
= "rx0", .dma_req
= 15 + OMAP44XX_DMA_REQ_START
},
2212 { .name
= "tx1", .dma_req
= 22 + OMAP44XX_DMA_REQ_START
},
2213 { .name
= "rx1", .dma_req
= 23 + OMAP44XX_DMA_REQ_START
},
2217 /* mcspi3 dev_attr */
2218 static struct omap2_mcspi_dev_attr mcspi3_dev_attr
= {
2219 .num_chipselect
= 2,
2222 static struct omap_hwmod omap44xx_mcspi3_hwmod
= {
2224 .class = &omap44xx_mcspi_hwmod_class
,
2225 .clkdm_name
= "l4_per_clkdm",
2226 .mpu_irqs
= omap44xx_mcspi3_irqs
,
2227 .sdma_reqs
= omap44xx_mcspi3_sdma_reqs
,
2228 .main_clk
= "mcspi3_fck",
2231 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET
,
2232 .context_offs
= OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET
,
2233 .modulemode
= MODULEMODE_SWCTRL
,
2236 .dev_attr
= &mcspi3_dev_attr
,
2240 static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs
[] = {
2241 { .irq
= 48 + OMAP44XX_IRQ_GIC_START
},
2245 static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs
[] = {
2246 { .name
= "tx0", .dma_req
= 69 + OMAP44XX_DMA_REQ_START
},
2247 { .name
= "rx0", .dma_req
= 70 + OMAP44XX_DMA_REQ_START
},
2251 /* mcspi4 dev_attr */
2252 static struct omap2_mcspi_dev_attr mcspi4_dev_attr
= {
2253 .num_chipselect
= 1,
2256 static struct omap_hwmod omap44xx_mcspi4_hwmod
= {
2258 .class = &omap44xx_mcspi_hwmod_class
,
2259 .clkdm_name
= "l4_per_clkdm",
2260 .mpu_irqs
= omap44xx_mcspi4_irqs
,
2261 .sdma_reqs
= omap44xx_mcspi4_sdma_reqs
,
2262 .main_clk
= "mcspi4_fck",
2265 .clkctrl_offs
= OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET
,
2266 .context_offs
= OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET
,
2267 .modulemode
= MODULEMODE_SWCTRL
,
2270 .dev_attr
= &mcspi4_dev_attr
,
2275 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
2278 static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc
= {
2280 .sysc_offs
= 0x0010,
2281 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
2282 SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
2283 SYSC_HAS_SOFTRESET
),
2284 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2285 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
2286 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
2287 .sysc_fields
= &omap_hwmod_sysc_type2
,
2290 static struct omap_hwmod_class omap44xx_mmc_hwmod_class
= {
2292 .sysc
= &omap44xx_mmc_sysc
,
2296 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs
[] = {
2297 { .irq
= 83 + OMAP44XX_IRQ_GIC_START
},
2301 static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs
[] = {
2302 { .name
= "tx", .dma_req
= 60 + OMAP44XX_DMA_REQ_START
},
2303 { .name
= "rx", .dma_req
= 61 + OMAP44XX_DMA_REQ_START
},
2308 static struct omap_mmc_dev_attr mmc1_dev_attr
= {
2309 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
2312 static struct omap_hwmod omap44xx_mmc1_hwmod
= {
2314 .class = &omap44xx_mmc_hwmod_class
,
2315 .clkdm_name
= "l3_init_clkdm",
2316 .mpu_irqs
= omap44xx_mmc1_irqs
,
2317 .sdma_reqs
= omap44xx_mmc1_sdma_reqs
,
2318 .main_clk
= "mmc1_fck",
2321 .clkctrl_offs
= OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET
,
2322 .context_offs
= OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET
,
2323 .modulemode
= MODULEMODE_SWCTRL
,
2326 .dev_attr
= &mmc1_dev_attr
,
2330 static struct omap_hwmod_irq_info omap44xx_mmc2_irqs
[] = {
2331 { .irq
= 86 + OMAP44XX_IRQ_GIC_START
},
2335 static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs
[] = {
2336 { .name
= "tx", .dma_req
= 46 + OMAP44XX_DMA_REQ_START
},
2337 { .name
= "rx", .dma_req
= 47 + OMAP44XX_DMA_REQ_START
},
2341 static struct omap_hwmod omap44xx_mmc2_hwmod
= {
2343 .class = &omap44xx_mmc_hwmod_class
,
2344 .clkdm_name
= "l3_init_clkdm",
2345 .mpu_irqs
= omap44xx_mmc2_irqs
,
2346 .sdma_reqs
= omap44xx_mmc2_sdma_reqs
,
2347 .main_clk
= "mmc2_fck",
2350 .clkctrl_offs
= OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET
,
2351 .context_offs
= OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET
,
2352 .modulemode
= MODULEMODE_SWCTRL
,
2358 static struct omap_hwmod_irq_info omap44xx_mmc3_irqs
[] = {
2359 { .irq
= 94 + OMAP44XX_IRQ_GIC_START
},
2363 static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs
[] = {
2364 { .name
= "tx", .dma_req
= 76 + OMAP44XX_DMA_REQ_START
},
2365 { .name
= "rx", .dma_req
= 77 + OMAP44XX_DMA_REQ_START
},
2369 static struct omap_hwmod omap44xx_mmc3_hwmod
= {
2371 .class = &omap44xx_mmc_hwmod_class
,
2372 .clkdm_name
= "l4_per_clkdm",
2373 .mpu_irqs
= omap44xx_mmc3_irqs
,
2374 .sdma_reqs
= omap44xx_mmc3_sdma_reqs
,
2375 .main_clk
= "mmc3_fck",
2378 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET
,
2379 .context_offs
= OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET
,
2380 .modulemode
= MODULEMODE_SWCTRL
,
2386 static struct omap_hwmod_irq_info omap44xx_mmc4_irqs
[] = {
2387 { .irq
= 96 + OMAP44XX_IRQ_GIC_START
},
2391 static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs
[] = {
2392 { .name
= "tx", .dma_req
= 56 + OMAP44XX_DMA_REQ_START
},
2393 { .name
= "rx", .dma_req
= 57 + OMAP44XX_DMA_REQ_START
},
2397 static struct omap_hwmod omap44xx_mmc4_hwmod
= {
2399 .class = &omap44xx_mmc_hwmod_class
,
2400 .clkdm_name
= "l4_per_clkdm",
2401 .mpu_irqs
= omap44xx_mmc4_irqs
,
2402 .sdma_reqs
= omap44xx_mmc4_sdma_reqs
,
2403 .main_clk
= "mmc4_fck",
2406 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET
,
2407 .context_offs
= OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET
,
2408 .modulemode
= MODULEMODE_SWCTRL
,
2414 static struct omap_hwmod_irq_info omap44xx_mmc5_irqs
[] = {
2415 { .irq
= 59 + OMAP44XX_IRQ_GIC_START
},
2419 static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs
[] = {
2420 { .name
= "tx", .dma_req
= 58 + OMAP44XX_DMA_REQ_START
},
2421 { .name
= "rx", .dma_req
= 59 + OMAP44XX_DMA_REQ_START
},
2425 static struct omap_hwmod omap44xx_mmc5_hwmod
= {
2427 .class = &omap44xx_mmc_hwmod_class
,
2428 .clkdm_name
= "l4_per_clkdm",
2429 .mpu_irqs
= omap44xx_mmc5_irqs
,
2430 .sdma_reqs
= omap44xx_mmc5_sdma_reqs
,
2431 .main_clk
= "mmc5_fck",
2434 .clkctrl_offs
= OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET
,
2435 .context_offs
= OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET
,
2436 .modulemode
= MODULEMODE_SWCTRL
,
2446 static struct omap_hwmod_class omap44xx_mpu_hwmod_class
= {
2451 static struct omap_hwmod_irq_info omap44xx_mpu_irqs
[] = {
2452 { .name
= "pl310", .irq
= 0 + OMAP44XX_IRQ_GIC_START
},
2453 { .name
= "cti0", .irq
= 1 + OMAP44XX_IRQ_GIC_START
},
2454 { .name
= "cti1", .irq
= 2 + OMAP44XX_IRQ_GIC_START
},
2458 static struct omap_hwmod omap44xx_mpu_hwmod
= {
2460 .class = &omap44xx_mpu_hwmod_class
,
2461 .clkdm_name
= "mpuss_clkdm",
2462 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
2463 .mpu_irqs
= omap44xx_mpu_irqs
,
2464 .main_clk
= "dpll_mpu_m2_ck",
2467 .clkctrl_offs
= OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET
,
2468 .context_offs
= OMAP4_RM_MPU_MPU_CONTEXT_OFFSET
,
2475 * top-level core on-chip ram
2478 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class
= {
2483 static struct omap_hwmod omap44xx_ocmc_ram_hwmod
= {
2485 .class = &omap44xx_ocmc_ram_hwmod_class
,
2486 .clkdm_name
= "l3_2_clkdm",
2489 .clkctrl_offs
= OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET
,
2490 .context_offs
= OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET
,
2497 * bridge to transform ocp interface protocol to scp (serial control port)
2501 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class
= {
2505 /* ocp2scp_usb_phy */
2506 static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks
[] = {
2507 { .role
= "phy_48m", .clk
= "ocp2scp_usb_phy_phy_48m" },
2510 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod
= {
2511 .name
= "ocp2scp_usb_phy",
2512 .class = &omap44xx_ocp2scp_hwmod_class
,
2513 .clkdm_name
= "l3_init_clkdm",
2516 .clkctrl_offs
= OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET
,
2517 .context_offs
= OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET
,
2518 .modulemode
= MODULEMODE_HWCTRL
,
2521 .opt_clks
= ocp2scp_usb_phy_opt_clks
,
2522 .opt_clks_cnt
= ARRAY_SIZE(ocp2scp_usb_phy_opt_clks
),
2527 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2528 * + clock manager 1 (in always on power domain) + local prm in mpu
2531 static struct omap_hwmod_class omap44xx_prcm_hwmod_class
= {
2536 static struct omap_hwmod omap44xx_prcm_mpu_hwmod
= {
2538 .class = &omap44xx_prcm_hwmod_class
,
2539 .clkdm_name
= "l4_wkup_clkdm",
2543 static struct omap_hwmod omap44xx_cm_core_aon_hwmod
= {
2544 .name
= "cm_core_aon",
2545 .class = &omap44xx_prcm_hwmod_class
,
2549 static struct omap_hwmod omap44xx_cm_core_hwmod
= {
2551 .class = &omap44xx_prcm_hwmod_class
,
2555 static struct omap_hwmod_irq_info omap44xx_prm_irqs
[] = {
2556 { .irq
= 11 + OMAP44XX_IRQ_GIC_START
},
2560 static struct omap_hwmod_rst_info omap44xx_prm_resets
[] = {
2561 { .name
= "rst_global_warm_sw", .rst_shift
= 0 },
2562 { .name
= "rst_global_cold_sw", .rst_shift
= 1 },
2565 static struct omap_hwmod omap44xx_prm_hwmod
= {
2567 .class = &omap44xx_prcm_hwmod_class
,
2568 .mpu_irqs
= omap44xx_prm_irqs
,
2569 .rst_lines
= omap44xx_prm_resets
,
2570 .rst_lines_cnt
= ARRAY_SIZE(omap44xx_prm_resets
),
2575 * system clock and reset manager
2578 static struct omap_hwmod_class omap44xx_scrm_hwmod_class
= {
2583 static struct omap_hwmod omap44xx_scrm_hwmod
= {
2585 .class = &omap44xx_scrm_hwmod_class
,
2586 .clkdm_name
= "l4_wkup_clkdm",
2591 * shared level 2 memory interface
2594 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class
= {
2599 static struct omap_hwmod omap44xx_sl2if_hwmod
= {
2601 .class = &omap44xx_sl2if_hwmod_class
,
2602 .clkdm_name
= "ivahd_clkdm",
2605 .clkctrl_offs
= OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET
,
2606 .context_offs
= OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET
,
2607 .modulemode
= MODULEMODE_HWCTRL
,
2614 * bidirectional, multi-drop, multi-channel two-line serial interface between
2615 * the device and external components
2618 static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc
= {
2620 .sysc_offs
= 0x0010,
2621 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
2622 SYSC_HAS_SOFTRESET
),
2623 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2625 .sysc_fields
= &omap_hwmod_sysc_type2
,
2628 static struct omap_hwmod_class omap44xx_slimbus_hwmod_class
= {
2630 .sysc
= &omap44xx_slimbus_sysc
,
2634 static struct omap_hwmod_irq_info omap44xx_slimbus1_irqs
[] = {
2635 { .irq
= 97 + OMAP44XX_IRQ_GIC_START
},
2639 static struct omap_hwmod_dma_info omap44xx_slimbus1_sdma_reqs
[] = {
2640 { .name
= "tx0", .dma_req
= 84 + OMAP44XX_DMA_REQ_START
},
2641 { .name
= "tx1", .dma_req
= 85 + OMAP44XX_DMA_REQ_START
},
2642 { .name
= "tx2", .dma_req
= 86 + OMAP44XX_DMA_REQ_START
},
2643 { .name
= "tx3", .dma_req
= 87 + OMAP44XX_DMA_REQ_START
},
2644 { .name
= "rx0", .dma_req
= 88 + OMAP44XX_DMA_REQ_START
},
2645 { .name
= "rx1", .dma_req
= 89 + OMAP44XX_DMA_REQ_START
},
2646 { .name
= "rx2", .dma_req
= 90 + OMAP44XX_DMA_REQ_START
},
2647 { .name
= "rx3", .dma_req
= 91 + OMAP44XX_DMA_REQ_START
},
2651 static struct omap_hwmod_opt_clk slimbus1_opt_clks
[] = {
2652 { .role
= "fclk_1", .clk
= "slimbus1_fclk_1" },
2653 { .role
= "fclk_0", .clk
= "slimbus1_fclk_0" },
2654 { .role
= "fclk_2", .clk
= "slimbus1_fclk_2" },
2655 { .role
= "slimbus_clk", .clk
= "slimbus1_slimbus_clk" },
2658 static struct omap_hwmod omap44xx_slimbus1_hwmod
= {
2660 .class = &omap44xx_slimbus_hwmod_class
,
2661 .clkdm_name
= "abe_clkdm",
2662 .mpu_irqs
= omap44xx_slimbus1_irqs
,
2663 .sdma_reqs
= omap44xx_slimbus1_sdma_reqs
,
2666 .clkctrl_offs
= OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET
,
2667 .context_offs
= OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET
,
2668 .modulemode
= MODULEMODE_SWCTRL
,
2671 .opt_clks
= slimbus1_opt_clks
,
2672 .opt_clks_cnt
= ARRAY_SIZE(slimbus1_opt_clks
),
2676 static struct omap_hwmod_irq_info omap44xx_slimbus2_irqs
[] = {
2677 { .irq
= 98 + OMAP44XX_IRQ_GIC_START
},
2681 static struct omap_hwmod_dma_info omap44xx_slimbus2_sdma_reqs
[] = {
2682 { .name
= "tx0", .dma_req
= 92 + OMAP44XX_DMA_REQ_START
},
2683 { .name
= "tx1", .dma_req
= 93 + OMAP44XX_DMA_REQ_START
},
2684 { .name
= "tx2", .dma_req
= 94 + OMAP44XX_DMA_REQ_START
},
2685 { .name
= "tx3", .dma_req
= 95 + OMAP44XX_DMA_REQ_START
},
2686 { .name
= "rx0", .dma_req
= 96 + OMAP44XX_DMA_REQ_START
},
2687 { .name
= "rx1", .dma_req
= 97 + OMAP44XX_DMA_REQ_START
},
2688 { .name
= "rx2", .dma_req
= 98 + OMAP44XX_DMA_REQ_START
},
2689 { .name
= "rx3", .dma_req
= 99 + OMAP44XX_DMA_REQ_START
},
2693 static struct omap_hwmod_opt_clk slimbus2_opt_clks
[] = {
2694 { .role
= "fclk_1", .clk
= "slimbus2_fclk_1" },
2695 { .role
= "fclk_0", .clk
= "slimbus2_fclk_0" },
2696 { .role
= "slimbus_clk", .clk
= "slimbus2_slimbus_clk" },
2699 static struct omap_hwmod omap44xx_slimbus2_hwmod
= {
2701 .class = &omap44xx_slimbus_hwmod_class
,
2702 .clkdm_name
= "l4_per_clkdm",
2703 .mpu_irqs
= omap44xx_slimbus2_irqs
,
2704 .sdma_reqs
= omap44xx_slimbus2_sdma_reqs
,
2707 .clkctrl_offs
= OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET
,
2708 .context_offs
= OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET
,
2709 .modulemode
= MODULEMODE_SWCTRL
,
2712 .opt_clks
= slimbus2_opt_clks
,
2713 .opt_clks_cnt
= ARRAY_SIZE(slimbus2_opt_clks
),
2717 * 'smartreflex' class
2718 * smartreflex module (monitor silicon performance and outputs a measure of
2719 * performance error)
2722 /* The IP is not compliant to type1 / type2 scheme */
2723 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex
= {
2728 static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc
= {
2729 .sysc_offs
= 0x0038,
2730 .sysc_flags
= (SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
),
2731 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2733 .sysc_fields
= &omap_hwmod_sysc_type_smartreflex
,
2736 static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class
= {
2737 .name
= "smartreflex",
2738 .sysc
= &omap44xx_smartreflex_sysc
,
2742 /* smartreflex_core */
2743 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr
= {
2744 .sensor_voltdm_name
= "core",
2747 static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs
[] = {
2748 { .irq
= 19 + OMAP44XX_IRQ_GIC_START
},
2752 static struct omap_hwmod omap44xx_smartreflex_core_hwmod
= {
2753 .name
= "smartreflex_core",
2754 .class = &omap44xx_smartreflex_hwmod_class
,
2755 .clkdm_name
= "l4_ao_clkdm",
2756 .mpu_irqs
= omap44xx_smartreflex_core_irqs
,
2758 .main_clk
= "smartreflex_core_fck",
2761 .clkctrl_offs
= OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET
,
2762 .context_offs
= OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET
,
2763 .modulemode
= MODULEMODE_SWCTRL
,
2766 .dev_attr
= &smartreflex_core_dev_attr
,
2769 /* smartreflex_iva */
2770 static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr
= {
2771 .sensor_voltdm_name
= "iva",
2774 static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs
[] = {
2775 { .irq
= 102 + OMAP44XX_IRQ_GIC_START
},
2779 static struct omap_hwmod omap44xx_smartreflex_iva_hwmod
= {
2780 .name
= "smartreflex_iva",
2781 .class = &omap44xx_smartreflex_hwmod_class
,
2782 .clkdm_name
= "l4_ao_clkdm",
2783 .mpu_irqs
= omap44xx_smartreflex_iva_irqs
,
2784 .main_clk
= "smartreflex_iva_fck",
2787 .clkctrl_offs
= OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET
,
2788 .context_offs
= OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET
,
2789 .modulemode
= MODULEMODE_SWCTRL
,
2792 .dev_attr
= &smartreflex_iva_dev_attr
,
2795 /* smartreflex_mpu */
2796 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr
= {
2797 .sensor_voltdm_name
= "mpu",
2800 static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs
[] = {
2801 { .irq
= 18 + OMAP44XX_IRQ_GIC_START
},
2805 static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod
= {
2806 .name
= "smartreflex_mpu",
2807 .class = &omap44xx_smartreflex_hwmod_class
,
2808 .clkdm_name
= "l4_ao_clkdm",
2809 .mpu_irqs
= omap44xx_smartreflex_mpu_irqs
,
2810 .main_clk
= "smartreflex_mpu_fck",
2813 .clkctrl_offs
= OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET
,
2814 .context_offs
= OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET
,
2815 .modulemode
= MODULEMODE_SWCTRL
,
2818 .dev_attr
= &smartreflex_mpu_dev_attr
,
2823 * spinlock provides hardware assistance for synchronizing the processes
2824 * running on multiple processors
2827 static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc
= {
2829 .sysc_offs
= 0x0010,
2830 .syss_offs
= 0x0014,
2831 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
2832 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
2833 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
2834 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2836 .sysc_fields
= &omap_hwmod_sysc_type1
,
2839 static struct omap_hwmod_class omap44xx_spinlock_hwmod_class
= {
2841 .sysc
= &omap44xx_spinlock_sysc
,
2845 static struct omap_hwmod omap44xx_spinlock_hwmod
= {
2847 .class = &omap44xx_spinlock_hwmod_class
,
2848 .clkdm_name
= "l4_cfg_clkdm",
2851 .clkctrl_offs
= OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET
,
2852 .context_offs
= OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET
,
2859 * general purpose timer module with accurate 1ms tick
2860 * This class contains several variants: ['timer_1ms', 'timer']
2863 static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc
= {
2865 .sysc_offs
= 0x0010,
2866 .syss_offs
= 0x0014,
2867 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
2868 SYSC_HAS_EMUFREE
| SYSC_HAS_ENAWAKEUP
|
2869 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
2870 SYSS_HAS_RESET_STATUS
),
2871 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
2872 .sysc_fields
= &omap_hwmod_sysc_type1
,
2875 static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class
= {
2877 .sysc
= &omap44xx_timer_1ms_sysc
,
2880 static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc
= {
2882 .sysc_offs
= 0x0010,
2883 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
2884 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
2885 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
2887 .sysc_fields
= &omap_hwmod_sysc_type2
,
2890 static struct omap_hwmod_class omap44xx_timer_hwmod_class
= {
2892 .sysc
= &omap44xx_timer_sysc
,
2895 /* always-on timers dev attribute */
2896 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr
= {
2897 .timer_capability
= OMAP_TIMER_ALWON
,
2900 /* pwm timers dev attribute */
2901 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr
= {
2902 .timer_capability
= OMAP_TIMER_HAS_PWM
,
2906 static struct omap_hwmod_irq_info omap44xx_timer1_irqs
[] = {
2907 { .irq
= 37 + OMAP44XX_IRQ_GIC_START
},
2911 static struct omap_hwmod omap44xx_timer1_hwmod
= {
2913 .class = &omap44xx_timer_1ms_hwmod_class
,
2914 .clkdm_name
= "l4_wkup_clkdm",
2915 .mpu_irqs
= omap44xx_timer1_irqs
,
2916 .main_clk
= "timer1_fck",
2919 .clkctrl_offs
= OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET
,
2920 .context_offs
= OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET
,
2921 .modulemode
= MODULEMODE_SWCTRL
,
2924 .dev_attr
= &capability_alwon_dev_attr
,
2928 static struct omap_hwmod_irq_info omap44xx_timer2_irqs
[] = {
2929 { .irq
= 38 + OMAP44XX_IRQ_GIC_START
},
2933 static struct omap_hwmod omap44xx_timer2_hwmod
= {
2935 .class = &omap44xx_timer_1ms_hwmod_class
,
2936 .clkdm_name
= "l4_per_clkdm",
2937 .mpu_irqs
= omap44xx_timer2_irqs
,
2938 .main_clk
= "timer2_fck",
2941 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET
,
2942 .context_offs
= OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET
,
2943 .modulemode
= MODULEMODE_SWCTRL
,
2949 static struct omap_hwmod_irq_info omap44xx_timer3_irqs
[] = {
2950 { .irq
= 39 + OMAP44XX_IRQ_GIC_START
},
2954 static struct omap_hwmod omap44xx_timer3_hwmod
= {
2956 .class = &omap44xx_timer_hwmod_class
,
2957 .clkdm_name
= "l4_per_clkdm",
2958 .mpu_irqs
= omap44xx_timer3_irqs
,
2959 .main_clk
= "timer3_fck",
2962 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET
,
2963 .context_offs
= OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET
,
2964 .modulemode
= MODULEMODE_SWCTRL
,
2970 static struct omap_hwmod_irq_info omap44xx_timer4_irqs
[] = {
2971 { .irq
= 40 + OMAP44XX_IRQ_GIC_START
},
2975 static struct omap_hwmod omap44xx_timer4_hwmod
= {
2977 .class = &omap44xx_timer_hwmod_class
,
2978 .clkdm_name
= "l4_per_clkdm",
2979 .mpu_irqs
= omap44xx_timer4_irqs
,
2980 .main_clk
= "timer4_fck",
2983 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET
,
2984 .context_offs
= OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET
,
2985 .modulemode
= MODULEMODE_SWCTRL
,
2991 static struct omap_hwmod_irq_info omap44xx_timer5_irqs
[] = {
2992 { .irq
= 41 + OMAP44XX_IRQ_GIC_START
},
2996 static struct omap_hwmod omap44xx_timer5_hwmod
= {
2998 .class = &omap44xx_timer_hwmod_class
,
2999 .clkdm_name
= "abe_clkdm",
3000 .mpu_irqs
= omap44xx_timer5_irqs
,
3001 .main_clk
= "timer5_fck",
3004 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET
,
3005 .context_offs
= OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET
,
3006 .modulemode
= MODULEMODE_SWCTRL
,
3012 static struct omap_hwmod_irq_info omap44xx_timer6_irqs
[] = {
3013 { .irq
= 42 + OMAP44XX_IRQ_GIC_START
},
3017 static struct omap_hwmod omap44xx_timer6_hwmod
= {
3019 .class = &omap44xx_timer_hwmod_class
,
3020 .clkdm_name
= "abe_clkdm",
3021 .mpu_irqs
= omap44xx_timer6_irqs
,
3023 .main_clk
= "timer6_fck",
3026 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET
,
3027 .context_offs
= OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET
,
3028 .modulemode
= MODULEMODE_SWCTRL
,
3034 static struct omap_hwmod_irq_info omap44xx_timer7_irqs
[] = {
3035 { .irq
= 43 + OMAP44XX_IRQ_GIC_START
},
3039 static struct omap_hwmod omap44xx_timer7_hwmod
= {
3041 .class = &omap44xx_timer_hwmod_class
,
3042 .clkdm_name
= "abe_clkdm",
3043 .mpu_irqs
= omap44xx_timer7_irqs
,
3044 .main_clk
= "timer7_fck",
3047 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET
,
3048 .context_offs
= OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET
,
3049 .modulemode
= MODULEMODE_SWCTRL
,
3055 static struct omap_hwmod_irq_info omap44xx_timer8_irqs
[] = {
3056 { .irq
= 44 + OMAP44XX_IRQ_GIC_START
},
3060 static struct omap_hwmod omap44xx_timer8_hwmod
= {
3062 .class = &omap44xx_timer_hwmod_class
,
3063 .clkdm_name
= "abe_clkdm",
3064 .mpu_irqs
= omap44xx_timer8_irqs
,
3065 .main_clk
= "timer8_fck",
3068 .clkctrl_offs
= OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET
,
3069 .context_offs
= OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET
,
3070 .modulemode
= MODULEMODE_SWCTRL
,
3073 .dev_attr
= &capability_pwm_dev_attr
,
3077 static struct omap_hwmod_irq_info omap44xx_timer9_irqs
[] = {
3078 { .irq
= 45 + OMAP44XX_IRQ_GIC_START
},
3082 static struct omap_hwmod omap44xx_timer9_hwmod
= {
3084 .class = &omap44xx_timer_hwmod_class
,
3085 .clkdm_name
= "l4_per_clkdm",
3086 .mpu_irqs
= omap44xx_timer9_irqs
,
3087 .main_clk
= "timer9_fck",
3090 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET
,
3091 .context_offs
= OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET
,
3092 .modulemode
= MODULEMODE_SWCTRL
,
3095 .dev_attr
= &capability_pwm_dev_attr
,
3099 static struct omap_hwmod_irq_info omap44xx_timer10_irqs
[] = {
3100 { .irq
= 46 + OMAP44XX_IRQ_GIC_START
},
3104 static struct omap_hwmod omap44xx_timer10_hwmod
= {
3106 .class = &omap44xx_timer_1ms_hwmod_class
,
3107 .clkdm_name
= "l4_per_clkdm",
3108 .mpu_irqs
= omap44xx_timer10_irqs
,
3109 .main_clk
= "timer10_fck",
3112 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET
,
3113 .context_offs
= OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET
,
3114 .modulemode
= MODULEMODE_SWCTRL
,
3117 .dev_attr
= &capability_pwm_dev_attr
,
3121 static struct omap_hwmod_irq_info omap44xx_timer11_irqs
[] = {
3122 { .irq
= 47 + OMAP44XX_IRQ_GIC_START
},
3126 static struct omap_hwmod omap44xx_timer11_hwmod
= {
3128 .class = &omap44xx_timer_hwmod_class
,
3129 .clkdm_name
= "l4_per_clkdm",
3130 .mpu_irqs
= omap44xx_timer11_irqs
,
3131 .main_clk
= "timer11_fck",
3134 .clkctrl_offs
= OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET
,
3135 .context_offs
= OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET
,
3136 .modulemode
= MODULEMODE_SWCTRL
,
3139 .dev_attr
= &capability_pwm_dev_attr
,
3144 * universal asynchronous receiver/transmitter (uart)
3147 static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc
= {
3149 .sysc_offs
= 0x0054,
3150 .syss_offs
= 0x0058,
3151 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
3152 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
3153 SYSS_HAS_RESET_STATUS
),
3154 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3156 .sysc_fields
= &omap_hwmod_sysc_type1
,
3159 static struct omap_hwmod_class omap44xx_uart_hwmod_class
= {
3161 .sysc
= &omap44xx_uart_sysc
,
3165 static struct omap_hwmod_irq_info omap44xx_uart1_irqs
[] = {
3166 { .irq
= 72 + OMAP44XX_IRQ_GIC_START
},
3170 static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs
[] = {
3171 { .name
= "tx", .dma_req
= 48 + OMAP44XX_DMA_REQ_START
},
3172 { .name
= "rx", .dma_req
= 49 + OMAP44XX_DMA_REQ_START
},
3176 static struct omap_hwmod omap44xx_uart1_hwmod
= {
3178 .class = &omap44xx_uart_hwmod_class
,
3179 .clkdm_name
= "l4_per_clkdm",
3180 .mpu_irqs
= omap44xx_uart1_irqs
,
3181 .sdma_reqs
= omap44xx_uart1_sdma_reqs
,
3182 .main_clk
= "uart1_fck",
3185 .clkctrl_offs
= OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET
,
3186 .context_offs
= OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET
,
3187 .modulemode
= MODULEMODE_SWCTRL
,
3193 static struct omap_hwmod_irq_info omap44xx_uart2_irqs
[] = {
3194 { .irq
= 73 + OMAP44XX_IRQ_GIC_START
},
3198 static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs
[] = {
3199 { .name
= "tx", .dma_req
= 50 + OMAP44XX_DMA_REQ_START
},
3200 { .name
= "rx", .dma_req
= 51 + OMAP44XX_DMA_REQ_START
},
3204 static struct omap_hwmod omap44xx_uart2_hwmod
= {
3206 .class = &omap44xx_uart_hwmod_class
,
3207 .clkdm_name
= "l4_per_clkdm",
3208 .mpu_irqs
= omap44xx_uart2_irqs
,
3209 .sdma_reqs
= omap44xx_uart2_sdma_reqs
,
3210 .main_clk
= "uart2_fck",
3213 .clkctrl_offs
= OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET
,
3214 .context_offs
= OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET
,
3215 .modulemode
= MODULEMODE_SWCTRL
,
3221 static struct omap_hwmod_irq_info omap44xx_uart3_irqs
[] = {
3222 { .irq
= 74 + OMAP44XX_IRQ_GIC_START
},
3226 static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs
[] = {
3227 { .name
= "tx", .dma_req
= 52 + OMAP44XX_DMA_REQ_START
},
3228 { .name
= "rx", .dma_req
= 53 + OMAP44XX_DMA_REQ_START
},
3232 static struct omap_hwmod omap44xx_uart3_hwmod
= {
3234 .class = &omap44xx_uart_hwmod_class
,
3235 .clkdm_name
= "l4_per_clkdm",
3236 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
3237 .mpu_irqs
= omap44xx_uart3_irqs
,
3238 .sdma_reqs
= omap44xx_uart3_sdma_reqs
,
3239 .main_clk
= "uart3_fck",
3242 .clkctrl_offs
= OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET
,
3243 .context_offs
= OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET
,
3244 .modulemode
= MODULEMODE_SWCTRL
,
3250 static struct omap_hwmod_irq_info omap44xx_uart4_irqs
[] = {
3251 { .irq
= 70 + OMAP44XX_IRQ_GIC_START
},
3255 static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs
[] = {
3256 { .name
= "tx", .dma_req
= 54 + OMAP44XX_DMA_REQ_START
},
3257 { .name
= "rx", .dma_req
= 55 + OMAP44XX_DMA_REQ_START
},
3261 static struct omap_hwmod omap44xx_uart4_hwmod
= {
3263 .class = &omap44xx_uart_hwmod_class
,
3264 .clkdm_name
= "l4_per_clkdm",
3265 .mpu_irqs
= omap44xx_uart4_irqs
,
3266 .sdma_reqs
= omap44xx_uart4_sdma_reqs
,
3267 .main_clk
= "uart4_fck",
3270 .clkctrl_offs
= OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET
,
3271 .context_offs
= OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET
,
3272 .modulemode
= MODULEMODE_SWCTRL
,
3278 * 'usb_host_fs' class
3279 * full-speed usb host controller
3282 /* The IP is not compliant to type1 / type2 scheme */
3283 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_usb_host_fs
= {
3289 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc
= {
3291 .sysc_offs
= 0x0210,
3292 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
3293 SYSC_HAS_SOFTRESET
),
3294 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3296 .sysc_fields
= &omap_hwmod_sysc_type_usb_host_fs
,
3299 static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class
= {
3300 .name
= "usb_host_fs",
3301 .sysc
= &omap44xx_usb_host_fs_sysc
,
3305 static struct omap_hwmod_irq_info omap44xx_usb_host_fs_irqs
[] = {
3306 { .name
= "std", .irq
= 89 + OMAP44XX_IRQ_GIC_START
},
3307 { .name
= "smi", .irq
= 90 + OMAP44XX_IRQ_GIC_START
},
3311 static struct omap_hwmod omap44xx_usb_host_fs_hwmod
= {
3312 .name
= "usb_host_fs",
3313 .class = &omap44xx_usb_host_fs_hwmod_class
,
3314 .clkdm_name
= "l3_init_clkdm",
3315 .mpu_irqs
= omap44xx_usb_host_fs_irqs
,
3316 .main_clk
= "usb_host_fs_fck",
3319 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET
,
3320 .context_offs
= OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET
,
3321 .modulemode
= MODULEMODE_SWCTRL
,
3327 * 'usb_host_hs' class
3328 * high-speed multi-port usb host controller
3331 static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc
= {
3333 .sysc_offs
= 0x0010,
3334 .syss_offs
= 0x0014,
3335 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
3336 SYSC_HAS_SOFTRESET
),
3337 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3338 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
3339 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
3340 .sysc_fields
= &omap_hwmod_sysc_type2
,
3343 static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class
= {
3344 .name
= "usb_host_hs",
3345 .sysc
= &omap44xx_usb_host_hs_sysc
,
3349 static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs
[] = {
3350 { .name
= "ohci-irq", .irq
= 76 + OMAP44XX_IRQ_GIC_START
},
3351 { .name
= "ehci-irq", .irq
= 77 + OMAP44XX_IRQ_GIC_START
},
3355 static struct omap_hwmod omap44xx_usb_host_hs_hwmod
= {
3356 .name
= "usb_host_hs",
3357 .class = &omap44xx_usb_host_hs_hwmod_class
,
3358 .clkdm_name
= "l3_init_clkdm",
3359 .main_clk
= "usb_host_hs_fck",
3362 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET
,
3363 .context_offs
= OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET
,
3364 .modulemode
= MODULEMODE_SWCTRL
,
3367 .mpu_irqs
= omap44xx_usb_host_hs_irqs
,
3370 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
3374 * In the following configuration :
3375 * - USBHOST module is set to smart-idle mode
3376 * - PRCM asserts idle_req to the USBHOST module ( This typically
3377 * happens when the system is going to a low power mode : all ports
3378 * have been suspended, the master part of the USBHOST module has
3379 * entered the standby state, and SW has cut the functional clocks)
3380 * - an USBHOST interrupt occurs before the module is able to answer
3381 * idle_ack, typically a remote wakeup IRQ.
3382 * Then the USB HOST module will enter a deadlock situation where it
3383 * is no more accessible nor functional.
3386 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
3390 * Errata: USB host EHCI may stall when entering smart-standby mode
3394 * When the USBHOST module is set to smart-standby mode, and when it is
3395 * ready to enter the standby state (i.e. all ports are suspended and
3396 * all attached devices are in suspend mode), then it can wrongly assert
3397 * the Mstandby signal too early while there are still some residual OCP
3398 * transactions ongoing. If this condition occurs, the internal state
3399 * machine may go to an undefined state and the USB link may be stuck
3400 * upon the next resume.
3403 * Don't use smart standby; use only force standby,
3404 * hence HWMOD_SWSUP_MSTANDBY
3408 * During system boot; If the hwmod framework resets the module
3409 * the module will have smart idle settings; which can lead to deadlock
3410 * (above Errata Id:i660); so, dont reset the module during boot;
3411 * Use HWMOD_INIT_NO_RESET.
3414 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
|
3415 HWMOD_INIT_NO_RESET
,
3419 * 'usb_otg_hs' class
3420 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
3423 static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc
= {
3425 .sysc_offs
= 0x0404,
3426 .syss_offs
= 0x0408,
3427 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
3428 SYSC_HAS_MIDLEMODE
| SYSC_HAS_SIDLEMODE
|
3429 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
3430 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3431 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
3433 .sysc_fields
= &omap_hwmod_sysc_type1
,
3436 static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class
= {
3437 .name
= "usb_otg_hs",
3438 .sysc
= &omap44xx_usb_otg_hs_sysc
,
3442 static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs
[] = {
3443 { .name
= "mc", .irq
= 92 + OMAP44XX_IRQ_GIC_START
},
3444 { .name
= "dma", .irq
= 93 + OMAP44XX_IRQ_GIC_START
},
3448 static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks
[] = {
3449 { .role
= "xclk", .clk
= "usb_otg_hs_xclk" },
3452 static struct omap_hwmod omap44xx_usb_otg_hs_hwmod
= {
3453 .name
= "usb_otg_hs",
3454 .class = &omap44xx_usb_otg_hs_hwmod_class
,
3455 .clkdm_name
= "l3_init_clkdm",
3456 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
,
3457 .mpu_irqs
= omap44xx_usb_otg_hs_irqs
,
3458 .main_clk
= "usb_otg_hs_ick",
3461 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET
,
3462 .context_offs
= OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET
,
3463 .modulemode
= MODULEMODE_HWCTRL
,
3466 .opt_clks
= usb_otg_hs_opt_clks
,
3467 .opt_clks_cnt
= ARRAY_SIZE(usb_otg_hs_opt_clks
),
3471 * 'usb_tll_hs' class
3472 * usb_tll_hs module is the adapter on the usb_host_hs ports
3475 static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc
= {
3477 .sysc_offs
= 0x0010,
3478 .syss_offs
= 0x0014,
3479 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_SIDLEMODE
|
3480 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SOFTRESET
|
3482 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
3483 .sysc_fields
= &omap_hwmod_sysc_type1
,
3486 static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class
= {
3487 .name
= "usb_tll_hs",
3488 .sysc
= &omap44xx_usb_tll_hs_sysc
,
3491 static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs
[] = {
3492 { .name
= "tll-irq", .irq
= 78 + OMAP44XX_IRQ_GIC_START
},
3496 static struct omap_hwmod omap44xx_usb_tll_hs_hwmod
= {
3497 .name
= "usb_tll_hs",
3498 .class = &omap44xx_usb_tll_hs_hwmod_class
,
3499 .clkdm_name
= "l3_init_clkdm",
3500 .mpu_irqs
= omap44xx_usb_tll_hs_irqs
,
3501 .main_clk
= "usb_tll_hs_ick",
3504 .clkctrl_offs
= OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET
,
3505 .context_offs
= OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET
,
3506 .modulemode
= MODULEMODE_HWCTRL
,
3513 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
3514 * overflow condition
3517 static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc
= {
3519 .sysc_offs
= 0x0010,
3520 .syss_offs
= 0x0014,
3521 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_SIDLEMODE
|
3522 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
3523 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
3525 .sysc_fields
= &omap_hwmod_sysc_type1
,
3528 static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class
= {
3530 .sysc
= &omap44xx_wd_timer_sysc
,
3531 .pre_shutdown
= &omap2_wd_timer_disable
,
3532 .reset
= &omap2_wd_timer_reset
,
3536 static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs
[] = {
3537 { .irq
= 80 + OMAP44XX_IRQ_GIC_START
},
3541 static struct omap_hwmod omap44xx_wd_timer2_hwmod
= {
3542 .name
= "wd_timer2",
3543 .class = &omap44xx_wd_timer_hwmod_class
,
3544 .clkdm_name
= "l4_wkup_clkdm",
3545 .mpu_irqs
= omap44xx_wd_timer2_irqs
,
3546 .main_clk
= "wd_timer2_fck",
3549 .clkctrl_offs
= OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET
,
3550 .context_offs
= OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET
,
3551 .modulemode
= MODULEMODE_SWCTRL
,
3557 static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs
[] = {
3558 { .irq
= 36 + OMAP44XX_IRQ_GIC_START
},
3562 static struct omap_hwmod omap44xx_wd_timer3_hwmod
= {
3563 .name
= "wd_timer3",
3564 .class = &omap44xx_wd_timer_hwmod_class
,
3565 .clkdm_name
= "abe_clkdm",
3566 .mpu_irqs
= omap44xx_wd_timer3_irqs
,
3567 .main_clk
= "wd_timer3_fck",
3570 .clkctrl_offs
= OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET
,
3571 .context_offs
= OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET
,
3572 .modulemode
= MODULEMODE_SWCTRL
,
3582 static struct omap_hwmod_addr_space omap44xx_c2c_target_fw_addrs
[] = {
3584 .pa_start
= 0x4a204000,
3585 .pa_end
= 0x4a2040ff,
3586 .flags
= ADDR_TYPE_RT
3591 /* c2c -> c2c_target_fw */
3592 static struct omap_hwmod_ocp_if omap44xx_c2c__c2c_target_fw
= {
3593 .master
= &omap44xx_c2c_hwmod
,
3594 .slave
= &omap44xx_c2c_target_fw_hwmod
,
3595 .clk
= "div_core_ck",
3596 .addr
= omap44xx_c2c_target_fw_addrs
,
3597 .user
= OCP_USER_MPU
,
3600 /* l4_cfg -> c2c_target_fw */
3601 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__c2c_target_fw
= {
3602 .master
= &omap44xx_l4_cfg_hwmod
,
3603 .slave
= &omap44xx_c2c_target_fw_hwmod
,
3605 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3608 /* l3_main_1 -> dmm */
3609 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm
= {
3610 .master
= &omap44xx_l3_main_1_hwmod
,
3611 .slave
= &omap44xx_dmm_hwmod
,
3613 .user
= OCP_USER_SDMA
,
3616 static struct omap_hwmod_addr_space omap44xx_dmm_addrs
[] = {
3618 .pa_start
= 0x4e000000,
3619 .pa_end
= 0x4e0007ff,
3620 .flags
= ADDR_TYPE_RT
3626 static struct omap_hwmod_ocp_if omap44xx_mpu__dmm
= {
3627 .master
= &omap44xx_mpu_hwmod
,
3628 .slave
= &omap44xx_dmm_hwmod
,
3630 .addr
= omap44xx_dmm_addrs
,
3631 .user
= OCP_USER_MPU
,
3634 /* c2c -> emif_fw */
3635 static struct omap_hwmod_ocp_if omap44xx_c2c__emif_fw
= {
3636 .master
= &omap44xx_c2c_hwmod
,
3637 .slave
= &omap44xx_emif_fw_hwmod
,
3638 .clk
= "div_core_ck",
3639 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3642 /* dmm -> emif_fw */
3643 static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw
= {
3644 .master
= &omap44xx_dmm_hwmod
,
3645 .slave
= &omap44xx_emif_fw_hwmod
,
3647 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3650 static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs
[] = {
3652 .pa_start
= 0x4a20c000,
3653 .pa_end
= 0x4a20c0ff,
3654 .flags
= ADDR_TYPE_RT
3659 /* l4_cfg -> emif_fw */
3660 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw
= {
3661 .master
= &omap44xx_l4_cfg_hwmod
,
3662 .slave
= &omap44xx_emif_fw_hwmod
,
3664 .addr
= omap44xx_emif_fw_addrs
,
3665 .user
= OCP_USER_MPU
,
3668 /* iva -> l3_instr */
3669 static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr
= {
3670 .master
= &omap44xx_iva_hwmod
,
3671 .slave
= &omap44xx_l3_instr_hwmod
,
3673 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3676 /* l3_main_3 -> l3_instr */
3677 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr
= {
3678 .master
= &omap44xx_l3_main_3_hwmod
,
3679 .slave
= &omap44xx_l3_instr_hwmod
,
3681 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3684 /* ocp_wp_noc -> l3_instr */
3685 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr
= {
3686 .master
= &omap44xx_ocp_wp_noc_hwmod
,
3687 .slave
= &omap44xx_l3_instr_hwmod
,
3689 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3692 /* dsp -> l3_main_1 */
3693 static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1
= {
3694 .master
= &omap44xx_dsp_hwmod
,
3695 .slave
= &omap44xx_l3_main_1_hwmod
,
3697 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3700 /* dss -> l3_main_1 */
3701 static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1
= {
3702 .master
= &omap44xx_dss_hwmod
,
3703 .slave
= &omap44xx_l3_main_1_hwmod
,
3705 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3708 /* l3_main_2 -> l3_main_1 */
3709 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1
= {
3710 .master
= &omap44xx_l3_main_2_hwmod
,
3711 .slave
= &omap44xx_l3_main_1_hwmod
,
3713 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3716 /* l4_cfg -> l3_main_1 */
3717 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1
= {
3718 .master
= &omap44xx_l4_cfg_hwmod
,
3719 .slave
= &omap44xx_l3_main_1_hwmod
,
3721 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3724 /* mmc1 -> l3_main_1 */
3725 static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1
= {
3726 .master
= &omap44xx_mmc1_hwmod
,
3727 .slave
= &omap44xx_l3_main_1_hwmod
,
3729 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3732 /* mmc2 -> l3_main_1 */
3733 static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1
= {
3734 .master
= &omap44xx_mmc2_hwmod
,
3735 .slave
= &omap44xx_l3_main_1_hwmod
,
3737 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3740 static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs
[] = {
3742 .pa_start
= 0x44000000,
3743 .pa_end
= 0x44000fff,
3744 .flags
= ADDR_TYPE_RT
3749 /* mpu -> l3_main_1 */
3750 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1
= {
3751 .master
= &omap44xx_mpu_hwmod
,
3752 .slave
= &omap44xx_l3_main_1_hwmod
,
3754 .addr
= omap44xx_l3_main_1_addrs
,
3755 .user
= OCP_USER_MPU
,
3758 /* c2c_target_fw -> l3_main_2 */
3759 static struct omap_hwmod_ocp_if omap44xx_c2c_target_fw__l3_main_2
= {
3760 .master
= &omap44xx_c2c_target_fw_hwmod
,
3761 .slave
= &omap44xx_l3_main_2_hwmod
,
3763 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3766 /* debugss -> l3_main_2 */
3767 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2
= {
3768 .master
= &omap44xx_debugss_hwmod
,
3769 .slave
= &omap44xx_l3_main_2_hwmod
,
3770 .clk
= "dbgclk_mux_ck",
3771 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3774 /* dma_system -> l3_main_2 */
3775 static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2
= {
3776 .master
= &omap44xx_dma_system_hwmod
,
3777 .slave
= &omap44xx_l3_main_2_hwmod
,
3779 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3782 /* fdif -> l3_main_2 */
3783 static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2
= {
3784 .master
= &omap44xx_fdif_hwmod
,
3785 .slave
= &omap44xx_l3_main_2_hwmod
,
3787 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3790 /* gpu -> l3_main_2 */
3791 static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2
= {
3792 .master
= &omap44xx_gpu_hwmod
,
3793 .slave
= &omap44xx_l3_main_2_hwmod
,
3795 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3798 /* hsi -> l3_main_2 */
3799 static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2
= {
3800 .master
= &omap44xx_hsi_hwmod
,
3801 .slave
= &omap44xx_l3_main_2_hwmod
,
3803 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3806 /* ipu -> l3_main_2 */
3807 static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2
= {
3808 .master
= &omap44xx_ipu_hwmod
,
3809 .slave
= &omap44xx_l3_main_2_hwmod
,
3811 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3814 /* iss -> l3_main_2 */
3815 static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2
= {
3816 .master
= &omap44xx_iss_hwmod
,
3817 .slave
= &omap44xx_l3_main_2_hwmod
,
3819 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3822 /* iva -> l3_main_2 */
3823 static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2
= {
3824 .master
= &omap44xx_iva_hwmod
,
3825 .slave
= &omap44xx_l3_main_2_hwmod
,
3827 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3830 static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs
[] = {
3832 .pa_start
= 0x44800000,
3833 .pa_end
= 0x44801fff,
3834 .flags
= ADDR_TYPE_RT
3839 /* l3_main_1 -> l3_main_2 */
3840 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2
= {
3841 .master
= &omap44xx_l3_main_1_hwmod
,
3842 .slave
= &omap44xx_l3_main_2_hwmod
,
3844 .addr
= omap44xx_l3_main_2_addrs
,
3845 .user
= OCP_USER_MPU
,
3848 /* l4_cfg -> l3_main_2 */
3849 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2
= {
3850 .master
= &omap44xx_l4_cfg_hwmod
,
3851 .slave
= &omap44xx_l3_main_2_hwmod
,
3853 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3856 /* usb_host_fs -> l3_main_2 */
3857 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2
= {
3858 .master
= &omap44xx_usb_host_fs_hwmod
,
3859 .slave
= &omap44xx_l3_main_2_hwmod
,
3861 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3864 /* usb_host_hs -> l3_main_2 */
3865 static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2
= {
3866 .master
= &omap44xx_usb_host_hs_hwmod
,
3867 .slave
= &omap44xx_l3_main_2_hwmod
,
3869 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3872 /* usb_otg_hs -> l3_main_2 */
3873 static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2
= {
3874 .master
= &omap44xx_usb_otg_hs_hwmod
,
3875 .slave
= &omap44xx_l3_main_2_hwmod
,
3877 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3880 static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs
[] = {
3882 .pa_start
= 0x45000000,
3883 .pa_end
= 0x45000fff,
3884 .flags
= ADDR_TYPE_RT
3889 /* l3_main_1 -> l3_main_3 */
3890 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3
= {
3891 .master
= &omap44xx_l3_main_1_hwmod
,
3892 .slave
= &omap44xx_l3_main_3_hwmod
,
3894 .addr
= omap44xx_l3_main_3_addrs
,
3895 .user
= OCP_USER_MPU
,
3898 /* l3_main_2 -> l3_main_3 */
3899 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3
= {
3900 .master
= &omap44xx_l3_main_2_hwmod
,
3901 .slave
= &omap44xx_l3_main_3_hwmod
,
3903 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3906 /* l4_cfg -> l3_main_3 */
3907 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3
= {
3908 .master
= &omap44xx_l4_cfg_hwmod
,
3909 .slave
= &omap44xx_l3_main_3_hwmod
,
3911 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3914 /* aess -> l4_abe */
3915 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe
= {
3916 .master
= &omap44xx_aess_hwmod
,
3917 .slave
= &omap44xx_l4_abe_hwmod
,
3918 .clk
= "ocp_abe_iclk",
3919 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3923 static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe
= {
3924 .master
= &omap44xx_dsp_hwmod
,
3925 .slave
= &omap44xx_l4_abe_hwmod
,
3926 .clk
= "ocp_abe_iclk",
3927 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3930 /* l3_main_1 -> l4_abe */
3931 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe
= {
3932 .master
= &omap44xx_l3_main_1_hwmod
,
3933 .slave
= &omap44xx_l4_abe_hwmod
,
3935 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3939 static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe
= {
3940 .master
= &omap44xx_mpu_hwmod
,
3941 .slave
= &omap44xx_l4_abe_hwmod
,
3942 .clk
= "ocp_abe_iclk",
3943 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3946 /* l3_main_1 -> l4_cfg */
3947 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg
= {
3948 .master
= &omap44xx_l3_main_1_hwmod
,
3949 .slave
= &omap44xx_l4_cfg_hwmod
,
3951 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3954 /* l3_main_2 -> l4_per */
3955 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per
= {
3956 .master
= &omap44xx_l3_main_2_hwmod
,
3957 .slave
= &omap44xx_l4_per_hwmod
,
3959 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3962 /* l4_cfg -> l4_wkup */
3963 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup
= {
3964 .master
= &omap44xx_l4_cfg_hwmod
,
3965 .slave
= &omap44xx_l4_wkup_hwmod
,
3967 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3970 /* mpu -> mpu_private */
3971 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private
= {
3972 .master
= &omap44xx_mpu_hwmod
,
3973 .slave
= &omap44xx_mpu_private_hwmod
,
3975 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3978 static struct omap_hwmod_addr_space omap44xx_ocp_wp_noc_addrs
[] = {
3980 .pa_start
= 0x4a102000,
3981 .pa_end
= 0x4a10207f,
3982 .flags
= ADDR_TYPE_RT
3987 /* l4_cfg -> ocp_wp_noc */
3988 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc
= {
3989 .master
= &omap44xx_l4_cfg_hwmod
,
3990 .slave
= &omap44xx_ocp_wp_noc_hwmod
,
3992 .addr
= omap44xx_ocp_wp_noc_addrs
,
3993 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
3996 static struct omap_hwmod_addr_space omap44xx_aess_addrs
[] = {
3998 .pa_start
= 0x401f1000,
3999 .pa_end
= 0x401f13ff,
4000 .flags
= ADDR_TYPE_RT
4005 /* l4_abe -> aess */
4006 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess
= {
4007 .master
= &omap44xx_l4_abe_hwmod
,
4008 .slave
= &omap44xx_aess_hwmod
,
4009 .clk
= "ocp_abe_iclk",
4010 .addr
= omap44xx_aess_addrs
,
4011 .user
= OCP_USER_MPU
,
4014 static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs
[] = {
4016 .pa_start
= 0x490f1000,
4017 .pa_end
= 0x490f13ff,
4018 .flags
= ADDR_TYPE_RT
4023 /* l4_abe -> aess (dma) */
4024 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma
= {
4025 .master
= &omap44xx_l4_abe_hwmod
,
4026 .slave
= &omap44xx_aess_hwmod
,
4027 .clk
= "ocp_abe_iclk",
4028 .addr
= omap44xx_aess_dma_addrs
,
4029 .user
= OCP_USER_SDMA
,
4032 /* l3_main_2 -> c2c */
4033 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c
= {
4034 .master
= &omap44xx_l3_main_2_hwmod
,
4035 .slave
= &omap44xx_c2c_hwmod
,
4037 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4040 static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs
[] = {
4042 .pa_start
= 0x4a304000,
4043 .pa_end
= 0x4a30401f,
4044 .flags
= ADDR_TYPE_RT
4049 /* l4_wkup -> counter_32k */
4050 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k
= {
4051 .master
= &omap44xx_l4_wkup_hwmod
,
4052 .slave
= &omap44xx_counter_32k_hwmod
,
4053 .clk
= "l4_wkup_clk_mux_ck",
4054 .addr
= omap44xx_counter_32k_addrs
,
4055 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4058 static struct omap_hwmod_addr_space omap44xx_ctrl_module_core_addrs
[] = {
4060 .pa_start
= 0x4a002000,
4061 .pa_end
= 0x4a0027ff,
4062 .flags
= ADDR_TYPE_RT
4067 /* l4_cfg -> ctrl_module_core */
4068 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core
= {
4069 .master
= &omap44xx_l4_cfg_hwmod
,
4070 .slave
= &omap44xx_ctrl_module_core_hwmod
,
4072 .addr
= omap44xx_ctrl_module_core_addrs
,
4073 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4076 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_core_addrs
[] = {
4078 .pa_start
= 0x4a100000,
4079 .pa_end
= 0x4a1007ff,
4080 .flags
= ADDR_TYPE_RT
4085 /* l4_cfg -> ctrl_module_pad_core */
4086 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core
= {
4087 .master
= &omap44xx_l4_cfg_hwmod
,
4088 .slave
= &omap44xx_ctrl_module_pad_core_hwmod
,
4090 .addr
= omap44xx_ctrl_module_pad_core_addrs
,
4091 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4094 static struct omap_hwmod_addr_space omap44xx_ctrl_module_wkup_addrs
[] = {
4096 .pa_start
= 0x4a30c000,
4097 .pa_end
= 0x4a30c7ff,
4098 .flags
= ADDR_TYPE_RT
4103 /* l4_wkup -> ctrl_module_wkup */
4104 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup
= {
4105 .master
= &omap44xx_l4_wkup_hwmod
,
4106 .slave
= &omap44xx_ctrl_module_wkup_hwmod
,
4107 .clk
= "l4_wkup_clk_mux_ck",
4108 .addr
= omap44xx_ctrl_module_wkup_addrs
,
4109 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4112 static struct omap_hwmod_addr_space omap44xx_ctrl_module_pad_wkup_addrs
[] = {
4114 .pa_start
= 0x4a31e000,
4115 .pa_end
= 0x4a31e7ff,
4116 .flags
= ADDR_TYPE_RT
4121 /* l4_wkup -> ctrl_module_pad_wkup */
4122 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup
= {
4123 .master
= &omap44xx_l4_wkup_hwmod
,
4124 .slave
= &omap44xx_ctrl_module_pad_wkup_hwmod
,
4125 .clk
= "l4_wkup_clk_mux_ck",
4126 .addr
= omap44xx_ctrl_module_pad_wkup_addrs
,
4127 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4130 static struct omap_hwmod_addr_space omap44xx_debugss_addrs
[] = {
4132 .pa_start
= 0x54160000,
4133 .pa_end
= 0x54167fff,
4134 .flags
= ADDR_TYPE_RT
4139 /* l3_instr -> debugss */
4140 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss
= {
4141 .master
= &omap44xx_l3_instr_hwmod
,
4142 .slave
= &omap44xx_debugss_hwmod
,
4144 .addr
= omap44xx_debugss_addrs
,
4145 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4148 static struct omap_hwmod_addr_space omap44xx_dma_system_addrs
[] = {
4150 .pa_start
= 0x4a056000,
4151 .pa_end
= 0x4a056fff,
4152 .flags
= ADDR_TYPE_RT
4157 /* l4_cfg -> dma_system */
4158 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system
= {
4159 .master
= &omap44xx_l4_cfg_hwmod
,
4160 .slave
= &omap44xx_dma_system_hwmod
,
4162 .addr
= omap44xx_dma_system_addrs
,
4163 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4166 static struct omap_hwmod_addr_space omap44xx_dmic_addrs
[] = {
4169 .pa_start
= 0x4012e000,
4170 .pa_end
= 0x4012e07f,
4171 .flags
= ADDR_TYPE_RT
4176 /* l4_abe -> dmic */
4177 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic
= {
4178 .master
= &omap44xx_l4_abe_hwmod
,
4179 .slave
= &omap44xx_dmic_hwmod
,
4180 .clk
= "ocp_abe_iclk",
4181 .addr
= omap44xx_dmic_addrs
,
4182 .user
= OCP_USER_MPU
,
4185 static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs
[] = {
4188 .pa_start
= 0x4902e000,
4189 .pa_end
= 0x4902e07f,
4190 .flags
= ADDR_TYPE_RT
4195 /* l4_abe -> dmic (dma) */
4196 static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma
= {
4197 .master
= &omap44xx_l4_abe_hwmod
,
4198 .slave
= &omap44xx_dmic_hwmod
,
4199 .clk
= "ocp_abe_iclk",
4200 .addr
= omap44xx_dmic_dma_addrs
,
4201 .user
= OCP_USER_SDMA
,
4205 static struct omap_hwmod_ocp_if omap44xx_dsp__iva
= {
4206 .master
= &omap44xx_dsp_hwmod
,
4207 .slave
= &omap44xx_iva_hwmod
,
4208 .clk
= "dpll_iva_m5x2_ck",
4209 .user
= OCP_USER_DSP
,
4213 static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if
= {
4214 .master
= &omap44xx_dsp_hwmod
,
4215 .slave
= &omap44xx_sl2if_hwmod
,
4216 .clk
= "dpll_iva_m5x2_ck",
4217 .user
= OCP_USER_DSP
,
4221 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp
= {
4222 .master
= &omap44xx_l4_cfg_hwmod
,
4223 .slave
= &omap44xx_dsp_hwmod
,
4225 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4228 static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs
[] = {
4230 .pa_start
= 0x58000000,
4231 .pa_end
= 0x5800007f,
4232 .flags
= ADDR_TYPE_RT
4237 /* l3_main_2 -> dss */
4238 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss
= {
4239 .master
= &omap44xx_l3_main_2_hwmod
,
4240 .slave
= &omap44xx_dss_hwmod
,
4242 .addr
= omap44xx_dss_dma_addrs
,
4243 .user
= OCP_USER_SDMA
,
4246 static struct omap_hwmod_addr_space omap44xx_dss_addrs
[] = {
4248 .pa_start
= 0x48040000,
4249 .pa_end
= 0x4804007f,
4250 .flags
= ADDR_TYPE_RT
4256 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss
= {
4257 .master
= &omap44xx_l4_per_hwmod
,
4258 .slave
= &omap44xx_dss_hwmod
,
4260 .addr
= omap44xx_dss_addrs
,
4261 .user
= OCP_USER_MPU
,
4264 static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs
[] = {
4266 .pa_start
= 0x58001000,
4267 .pa_end
= 0x58001fff,
4268 .flags
= ADDR_TYPE_RT
4273 /* l3_main_2 -> dss_dispc */
4274 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc
= {
4275 .master
= &omap44xx_l3_main_2_hwmod
,
4276 .slave
= &omap44xx_dss_dispc_hwmod
,
4278 .addr
= omap44xx_dss_dispc_dma_addrs
,
4279 .user
= OCP_USER_SDMA
,
4282 static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs
[] = {
4284 .pa_start
= 0x48041000,
4285 .pa_end
= 0x48041fff,
4286 .flags
= ADDR_TYPE_RT
4291 /* l4_per -> dss_dispc */
4292 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc
= {
4293 .master
= &omap44xx_l4_per_hwmod
,
4294 .slave
= &omap44xx_dss_dispc_hwmod
,
4296 .addr
= omap44xx_dss_dispc_addrs
,
4297 .user
= OCP_USER_MPU
,
4300 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs
[] = {
4302 .pa_start
= 0x58004000,
4303 .pa_end
= 0x580041ff,
4304 .flags
= ADDR_TYPE_RT
4309 /* l3_main_2 -> dss_dsi1 */
4310 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1
= {
4311 .master
= &omap44xx_l3_main_2_hwmod
,
4312 .slave
= &omap44xx_dss_dsi1_hwmod
,
4314 .addr
= omap44xx_dss_dsi1_dma_addrs
,
4315 .user
= OCP_USER_SDMA
,
4318 static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs
[] = {
4320 .pa_start
= 0x48044000,
4321 .pa_end
= 0x480441ff,
4322 .flags
= ADDR_TYPE_RT
4327 /* l4_per -> dss_dsi1 */
4328 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1
= {
4329 .master
= &omap44xx_l4_per_hwmod
,
4330 .slave
= &omap44xx_dss_dsi1_hwmod
,
4332 .addr
= omap44xx_dss_dsi1_addrs
,
4333 .user
= OCP_USER_MPU
,
4336 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs
[] = {
4338 .pa_start
= 0x58005000,
4339 .pa_end
= 0x580051ff,
4340 .flags
= ADDR_TYPE_RT
4345 /* l3_main_2 -> dss_dsi2 */
4346 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2
= {
4347 .master
= &omap44xx_l3_main_2_hwmod
,
4348 .slave
= &omap44xx_dss_dsi2_hwmod
,
4350 .addr
= omap44xx_dss_dsi2_dma_addrs
,
4351 .user
= OCP_USER_SDMA
,
4354 static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs
[] = {
4356 .pa_start
= 0x48045000,
4357 .pa_end
= 0x480451ff,
4358 .flags
= ADDR_TYPE_RT
4363 /* l4_per -> dss_dsi2 */
4364 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2
= {
4365 .master
= &omap44xx_l4_per_hwmod
,
4366 .slave
= &omap44xx_dss_dsi2_hwmod
,
4368 .addr
= omap44xx_dss_dsi2_addrs
,
4369 .user
= OCP_USER_MPU
,
4372 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs
[] = {
4374 .pa_start
= 0x58006000,
4375 .pa_end
= 0x58006fff,
4376 .flags
= ADDR_TYPE_RT
4381 /* l3_main_2 -> dss_hdmi */
4382 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi
= {
4383 .master
= &omap44xx_l3_main_2_hwmod
,
4384 .slave
= &omap44xx_dss_hdmi_hwmod
,
4386 .addr
= omap44xx_dss_hdmi_dma_addrs
,
4387 .user
= OCP_USER_SDMA
,
4390 static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs
[] = {
4392 .pa_start
= 0x48046000,
4393 .pa_end
= 0x48046fff,
4394 .flags
= ADDR_TYPE_RT
4399 /* l4_per -> dss_hdmi */
4400 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi
= {
4401 .master
= &omap44xx_l4_per_hwmod
,
4402 .slave
= &omap44xx_dss_hdmi_hwmod
,
4404 .addr
= omap44xx_dss_hdmi_addrs
,
4405 .user
= OCP_USER_MPU
,
4408 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs
[] = {
4410 .pa_start
= 0x58002000,
4411 .pa_end
= 0x580020ff,
4412 .flags
= ADDR_TYPE_RT
4417 /* l3_main_2 -> dss_rfbi */
4418 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi
= {
4419 .master
= &omap44xx_l3_main_2_hwmod
,
4420 .slave
= &omap44xx_dss_rfbi_hwmod
,
4422 .addr
= omap44xx_dss_rfbi_dma_addrs
,
4423 .user
= OCP_USER_SDMA
,
4426 static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs
[] = {
4428 .pa_start
= 0x48042000,
4429 .pa_end
= 0x480420ff,
4430 .flags
= ADDR_TYPE_RT
4435 /* l4_per -> dss_rfbi */
4436 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi
= {
4437 .master
= &omap44xx_l4_per_hwmod
,
4438 .slave
= &omap44xx_dss_rfbi_hwmod
,
4440 .addr
= omap44xx_dss_rfbi_addrs
,
4441 .user
= OCP_USER_MPU
,
4444 static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs
[] = {
4446 .pa_start
= 0x58003000,
4447 .pa_end
= 0x580030ff,
4448 .flags
= ADDR_TYPE_RT
4453 /* l3_main_2 -> dss_venc */
4454 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc
= {
4455 .master
= &omap44xx_l3_main_2_hwmod
,
4456 .slave
= &omap44xx_dss_venc_hwmod
,
4458 .addr
= omap44xx_dss_venc_dma_addrs
,
4459 .user
= OCP_USER_SDMA
,
4462 static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs
[] = {
4464 .pa_start
= 0x48043000,
4465 .pa_end
= 0x480430ff,
4466 .flags
= ADDR_TYPE_RT
4471 /* l4_per -> dss_venc */
4472 static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc
= {
4473 .master
= &omap44xx_l4_per_hwmod
,
4474 .slave
= &omap44xx_dss_venc_hwmod
,
4476 .addr
= omap44xx_dss_venc_addrs
,
4477 .user
= OCP_USER_MPU
,
4480 static struct omap_hwmod_addr_space omap44xx_elm_addrs
[] = {
4482 .pa_start
= 0x48078000,
4483 .pa_end
= 0x48078fff,
4484 .flags
= ADDR_TYPE_RT
4490 static struct omap_hwmod_ocp_if omap44xx_l4_per__elm
= {
4491 .master
= &omap44xx_l4_per_hwmod
,
4492 .slave
= &omap44xx_elm_hwmod
,
4494 .addr
= omap44xx_elm_addrs
,
4495 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4498 static struct omap_hwmod_addr_space omap44xx_emif1_addrs
[] = {
4500 .pa_start
= 0x4c000000,
4501 .pa_end
= 0x4c0000ff,
4502 .flags
= ADDR_TYPE_RT
4507 /* emif_fw -> emif1 */
4508 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1
= {
4509 .master
= &omap44xx_emif_fw_hwmod
,
4510 .slave
= &omap44xx_emif1_hwmod
,
4512 .addr
= omap44xx_emif1_addrs
,
4513 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4516 static struct omap_hwmod_addr_space omap44xx_emif2_addrs
[] = {
4518 .pa_start
= 0x4d000000,
4519 .pa_end
= 0x4d0000ff,
4520 .flags
= ADDR_TYPE_RT
4525 /* emif_fw -> emif2 */
4526 static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2
= {
4527 .master
= &omap44xx_emif_fw_hwmod
,
4528 .slave
= &omap44xx_emif2_hwmod
,
4530 .addr
= omap44xx_emif2_addrs
,
4531 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4534 static struct omap_hwmod_addr_space omap44xx_fdif_addrs
[] = {
4536 .pa_start
= 0x4a10a000,
4537 .pa_end
= 0x4a10a1ff,
4538 .flags
= ADDR_TYPE_RT
4543 /* l4_cfg -> fdif */
4544 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif
= {
4545 .master
= &omap44xx_l4_cfg_hwmod
,
4546 .slave
= &omap44xx_fdif_hwmod
,
4548 .addr
= omap44xx_fdif_addrs
,
4549 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4552 static struct omap_hwmod_addr_space omap44xx_gpio1_addrs
[] = {
4554 .pa_start
= 0x4a310000,
4555 .pa_end
= 0x4a3101ff,
4556 .flags
= ADDR_TYPE_RT
4561 /* l4_wkup -> gpio1 */
4562 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1
= {
4563 .master
= &omap44xx_l4_wkup_hwmod
,
4564 .slave
= &omap44xx_gpio1_hwmod
,
4565 .clk
= "l4_wkup_clk_mux_ck",
4566 .addr
= omap44xx_gpio1_addrs
,
4567 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4570 static struct omap_hwmod_addr_space omap44xx_gpio2_addrs
[] = {
4572 .pa_start
= 0x48055000,
4573 .pa_end
= 0x480551ff,
4574 .flags
= ADDR_TYPE_RT
4579 /* l4_per -> gpio2 */
4580 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2
= {
4581 .master
= &omap44xx_l4_per_hwmod
,
4582 .slave
= &omap44xx_gpio2_hwmod
,
4584 .addr
= omap44xx_gpio2_addrs
,
4585 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4588 static struct omap_hwmod_addr_space omap44xx_gpio3_addrs
[] = {
4590 .pa_start
= 0x48057000,
4591 .pa_end
= 0x480571ff,
4592 .flags
= ADDR_TYPE_RT
4597 /* l4_per -> gpio3 */
4598 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3
= {
4599 .master
= &omap44xx_l4_per_hwmod
,
4600 .slave
= &omap44xx_gpio3_hwmod
,
4602 .addr
= omap44xx_gpio3_addrs
,
4603 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4606 static struct omap_hwmod_addr_space omap44xx_gpio4_addrs
[] = {
4608 .pa_start
= 0x48059000,
4609 .pa_end
= 0x480591ff,
4610 .flags
= ADDR_TYPE_RT
4615 /* l4_per -> gpio4 */
4616 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4
= {
4617 .master
= &omap44xx_l4_per_hwmod
,
4618 .slave
= &omap44xx_gpio4_hwmod
,
4620 .addr
= omap44xx_gpio4_addrs
,
4621 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4624 static struct omap_hwmod_addr_space omap44xx_gpio5_addrs
[] = {
4626 .pa_start
= 0x4805b000,
4627 .pa_end
= 0x4805b1ff,
4628 .flags
= ADDR_TYPE_RT
4633 /* l4_per -> gpio5 */
4634 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5
= {
4635 .master
= &omap44xx_l4_per_hwmod
,
4636 .slave
= &omap44xx_gpio5_hwmod
,
4638 .addr
= omap44xx_gpio5_addrs
,
4639 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4642 static struct omap_hwmod_addr_space omap44xx_gpio6_addrs
[] = {
4644 .pa_start
= 0x4805d000,
4645 .pa_end
= 0x4805d1ff,
4646 .flags
= ADDR_TYPE_RT
4651 /* l4_per -> gpio6 */
4652 static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6
= {
4653 .master
= &omap44xx_l4_per_hwmod
,
4654 .slave
= &omap44xx_gpio6_hwmod
,
4656 .addr
= omap44xx_gpio6_addrs
,
4657 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4660 static struct omap_hwmod_addr_space omap44xx_gpmc_addrs
[] = {
4662 .pa_start
= 0x50000000,
4663 .pa_end
= 0x500003ff,
4664 .flags
= ADDR_TYPE_RT
4669 /* l3_main_2 -> gpmc */
4670 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc
= {
4671 .master
= &omap44xx_l3_main_2_hwmod
,
4672 .slave
= &omap44xx_gpmc_hwmod
,
4674 .addr
= omap44xx_gpmc_addrs
,
4675 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4678 static struct omap_hwmod_addr_space omap44xx_gpu_addrs
[] = {
4680 .pa_start
= 0x56000000,
4681 .pa_end
= 0x5600ffff,
4682 .flags
= ADDR_TYPE_RT
4687 /* l3_main_2 -> gpu */
4688 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu
= {
4689 .master
= &omap44xx_l3_main_2_hwmod
,
4690 .slave
= &omap44xx_gpu_hwmod
,
4692 .addr
= omap44xx_gpu_addrs
,
4693 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4696 static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs
[] = {
4698 .pa_start
= 0x480b2000,
4699 .pa_end
= 0x480b201f,
4700 .flags
= ADDR_TYPE_RT
4705 /* l4_per -> hdq1w */
4706 static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w
= {
4707 .master
= &omap44xx_l4_per_hwmod
,
4708 .slave
= &omap44xx_hdq1w_hwmod
,
4710 .addr
= omap44xx_hdq1w_addrs
,
4711 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4714 static struct omap_hwmod_addr_space omap44xx_hsi_addrs
[] = {
4716 .pa_start
= 0x4a058000,
4717 .pa_end
= 0x4a05bfff,
4718 .flags
= ADDR_TYPE_RT
4724 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi
= {
4725 .master
= &omap44xx_l4_cfg_hwmod
,
4726 .slave
= &omap44xx_hsi_hwmod
,
4728 .addr
= omap44xx_hsi_addrs
,
4729 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4732 static struct omap_hwmod_addr_space omap44xx_i2c1_addrs
[] = {
4734 .pa_start
= 0x48070000,
4735 .pa_end
= 0x480700ff,
4736 .flags
= ADDR_TYPE_RT
4741 /* l4_per -> i2c1 */
4742 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1
= {
4743 .master
= &omap44xx_l4_per_hwmod
,
4744 .slave
= &omap44xx_i2c1_hwmod
,
4746 .addr
= omap44xx_i2c1_addrs
,
4747 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4750 static struct omap_hwmod_addr_space omap44xx_i2c2_addrs
[] = {
4752 .pa_start
= 0x48072000,
4753 .pa_end
= 0x480720ff,
4754 .flags
= ADDR_TYPE_RT
4759 /* l4_per -> i2c2 */
4760 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2
= {
4761 .master
= &omap44xx_l4_per_hwmod
,
4762 .slave
= &omap44xx_i2c2_hwmod
,
4764 .addr
= omap44xx_i2c2_addrs
,
4765 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4768 static struct omap_hwmod_addr_space omap44xx_i2c3_addrs
[] = {
4770 .pa_start
= 0x48060000,
4771 .pa_end
= 0x480600ff,
4772 .flags
= ADDR_TYPE_RT
4777 /* l4_per -> i2c3 */
4778 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3
= {
4779 .master
= &omap44xx_l4_per_hwmod
,
4780 .slave
= &omap44xx_i2c3_hwmod
,
4782 .addr
= omap44xx_i2c3_addrs
,
4783 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4786 static struct omap_hwmod_addr_space omap44xx_i2c4_addrs
[] = {
4788 .pa_start
= 0x48350000,
4789 .pa_end
= 0x483500ff,
4790 .flags
= ADDR_TYPE_RT
4795 /* l4_per -> i2c4 */
4796 static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4
= {
4797 .master
= &omap44xx_l4_per_hwmod
,
4798 .slave
= &omap44xx_i2c4_hwmod
,
4800 .addr
= omap44xx_i2c4_addrs
,
4801 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4804 /* l3_main_2 -> ipu */
4805 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu
= {
4806 .master
= &omap44xx_l3_main_2_hwmod
,
4807 .slave
= &omap44xx_ipu_hwmod
,
4809 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4812 static struct omap_hwmod_addr_space omap44xx_iss_addrs
[] = {
4814 .pa_start
= 0x52000000,
4815 .pa_end
= 0x520000ff,
4816 .flags
= ADDR_TYPE_RT
4821 /* l3_main_2 -> iss */
4822 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss
= {
4823 .master
= &omap44xx_l3_main_2_hwmod
,
4824 .slave
= &omap44xx_iss_hwmod
,
4826 .addr
= omap44xx_iss_addrs
,
4827 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4831 static struct omap_hwmod_ocp_if omap44xx_iva__sl2if
= {
4832 .master
= &omap44xx_iva_hwmod
,
4833 .slave
= &omap44xx_sl2if_hwmod
,
4834 .clk
= "dpll_iva_m5x2_ck",
4835 .user
= OCP_USER_IVA
,
4838 static struct omap_hwmod_addr_space omap44xx_iva_addrs
[] = {
4840 .pa_start
= 0x5a000000,
4841 .pa_end
= 0x5a07ffff,
4842 .flags
= ADDR_TYPE_RT
4847 /* l3_main_2 -> iva */
4848 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva
= {
4849 .master
= &omap44xx_l3_main_2_hwmod
,
4850 .slave
= &omap44xx_iva_hwmod
,
4852 .addr
= omap44xx_iva_addrs
,
4853 .user
= OCP_USER_MPU
,
4856 static struct omap_hwmod_addr_space omap44xx_kbd_addrs
[] = {
4858 .pa_start
= 0x4a31c000,
4859 .pa_end
= 0x4a31c07f,
4860 .flags
= ADDR_TYPE_RT
4865 /* l4_wkup -> kbd */
4866 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd
= {
4867 .master
= &omap44xx_l4_wkup_hwmod
,
4868 .slave
= &omap44xx_kbd_hwmod
,
4869 .clk
= "l4_wkup_clk_mux_ck",
4870 .addr
= omap44xx_kbd_addrs
,
4871 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4874 static struct omap_hwmod_addr_space omap44xx_mailbox_addrs
[] = {
4876 .pa_start
= 0x4a0f4000,
4877 .pa_end
= 0x4a0f41ff,
4878 .flags
= ADDR_TYPE_RT
4883 /* l4_cfg -> mailbox */
4884 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox
= {
4885 .master
= &omap44xx_l4_cfg_hwmod
,
4886 .slave
= &omap44xx_mailbox_hwmod
,
4888 .addr
= omap44xx_mailbox_addrs
,
4889 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
4892 static struct omap_hwmod_addr_space omap44xx_mcasp_addrs
[] = {
4894 .pa_start
= 0x40128000,
4895 .pa_end
= 0x401283ff,
4896 .flags
= ADDR_TYPE_RT
4901 /* l4_abe -> mcasp */
4902 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp
= {
4903 .master
= &omap44xx_l4_abe_hwmod
,
4904 .slave
= &omap44xx_mcasp_hwmod
,
4905 .clk
= "ocp_abe_iclk",
4906 .addr
= omap44xx_mcasp_addrs
,
4907 .user
= OCP_USER_MPU
,
4910 static struct omap_hwmod_addr_space omap44xx_mcasp_dma_addrs
[] = {
4912 .pa_start
= 0x49028000,
4913 .pa_end
= 0x490283ff,
4914 .flags
= ADDR_TYPE_RT
4919 /* l4_abe -> mcasp (dma) */
4920 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma
= {
4921 .master
= &omap44xx_l4_abe_hwmod
,
4922 .slave
= &omap44xx_mcasp_hwmod
,
4923 .clk
= "ocp_abe_iclk",
4924 .addr
= omap44xx_mcasp_dma_addrs
,
4925 .user
= OCP_USER_SDMA
,
4928 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs
[] = {
4931 .pa_start
= 0x40122000,
4932 .pa_end
= 0x401220ff,
4933 .flags
= ADDR_TYPE_RT
4938 /* l4_abe -> mcbsp1 */
4939 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1
= {
4940 .master
= &omap44xx_l4_abe_hwmod
,
4941 .slave
= &omap44xx_mcbsp1_hwmod
,
4942 .clk
= "ocp_abe_iclk",
4943 .addr
= omap44xx_mcbsp1_addrs
,
4944 .user
= OCP_USER_MPU
,
4947 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs
[] = {
4950 .pa_start
= 0x49022000,
4951 .pa_end
= 0x490220ff,
4952 .flags
= ADDR_TYPE_RT
4957 /* l4_abe -> mcbsp1 (dma) */
4958 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma
= {
4959 .master
= &omap44xx_l4_abe_hwmod
,
4960 .slave
= &omap44xx_mcbsp1_hwmod
,
4961 .clk
= "ocp_abe_iclk",
4962 .addr
= omap44xx_mcbsp1_dma_addrs
,
4963 .user
= OCP_USER_SDMA
,
4966 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs
[] = {
4969 .pa_start
= 0x40124000,
4970 .pa_end
= 0x401240ff,
4971 .flags
= ADDR_TYPE_RT
4976 /* l4_abe -> mcbsp2 */
4977 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2
= {
4978 .master
= &omap44xx_l4_abe_hwmod
,
4979 .slave
= &omap44xx_mcbsp2_hwmod
,
4980 .clk
= "ocp_abe_iclk",
4981 .addr
= omap44xx_mcbsp2_addrs
,
4982 .user
= OCP_USER_MPU
,
4985 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs
[] = {
4988 .pa_start
= 0x49024000,
4989 .pa_end
= 0x490240ff,
4990 .flags
= ADDR_TYPE_RT
4995 /* l4_abe -> mcbsp2 (dma) */
4996 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma
= {
4997 .master
= &omap44xx_l4_abe_hwmod
,
4998 .slave
= &omap44xx_mcbsp2_hwmod
,
4999 .clk
= "ocp_abe_iclk",
5000 .addr
= omap44xx_mcbsp2_dma_addrs
,
5001 .user
= OCP_USER_SDMA
,
5004 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs
[] = {
5007 .pa_start
= 0x40126000,
5008 .pa_end
= 0x401260ff,
5009 .flags
= ADDR_TYPE_RT
5014 /* l4_abe -> mcbsp3 */
5015 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3
= {
5016 .master
= &omap44xx_l4_abe_hwmod
,
5017 .slave
= &omap44xx_mcbsp3_hwmod
,
5018 .clk
= "ocp_abe_iclk",
5019 .addr
= omap44xx_mcbsp3_addrs
,
5020 .user
= OCP_USER_MPU
,
5023 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs
[] = {
5026 .pa_start
= 0x49026000,
5027 .pa_end
= 0x490260ff,
5028 .flags
= ADDR_TYPE_RT
5033 /* l4_abe -> mcbsp3 (dma) */
5034 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma
= {
5035 .master
= &omap44xx_l4_abe_hwmod
,
5036 .slave
= &omap44xx_mcbsp3_hwmod
,
5037 .clk
= "ocp_abe_iclk",
5038 .addr
= omap44xx_mcbsp3_dma_addrs
,
5039 .user
= OCP_USER_SDMA
,
5042 static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs
[] = {
5044 .pa_start
= 0x48096000,
5045 .pa_end
= 0x480960ff,
5046 .flags
= ADDR_TYPE_RT
5051 /* l4_per -> mcbsp4 */
5052 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4
= {
5053 .master
= &omap44xx_l4_per_hwmod
,
5054 .slave
= &omap44xx_mcbsp4_hwmod
,
5056 .addr
= omap44xx_mcbsp4_addrs
,
5057 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5060 static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs
[] = {
5062 .pa_start
= 0x40132000,
5063 .pa_end
= 0x4013207f,
5064 .flags
= ADDR_TYPE_RT
5069 /* l4_abe -> mcpdm */
5070 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm
= {
5071 .master
= &omap44xx_l4_abe_hwmod
,
5072 .slave
= &omap44xx_mcpdm_hwmod
,
5073 .clk
= "ocp_abe_iclk",
5074 .addr
= omap44xx_mcpdm_addrs
,
5075 .user
= OCP_USER_MPU
,
5078 static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs
[] = {
5080 .pa_start
= 0x49032000,
5081 .pa_end
= 0x4903207f,
5082 .flags
= ADDR_TYPE_RT
5087 /* l4_abe -> mcpdm (dma) */
5088 static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma
= {
5089 .master
= &omap44xx_l4_abe_hwmod
,
5090 .slave
= &omap44xx_mcpdm_hwmod
,
5091 .clk
= "ocp_abe_iclk",
5092 .addr
= omap44xx_mcpdm_dma_addrs
,
5093 .user
= OCP_USER_SDMA
,
5096 static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs
[] = {
5098 .pa_start
= 0x48098000,
5099 .pa_end
= 0x480981ff,
5100 .flags
= ADDR_TYPE_RT
5105 /* l4_per -> mcspi1 */
5106 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1
= {
5107 .master
= &omap44xx_l4_per_hwmod
,
5108 .slave
= &omap44xx_mcspi1_hwmod
,
5110 .addr
= omap44xx_mcspi1_addrs
,
5111 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5114 static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs
[] = {
5116 .pa_start
= 0x4809a000,
5117 .pa_end
= 0x4809a1ff,
5118 .flags
= ADDR_TYPE_RT
5123 /* l4_per -> mcspi2 */
5124 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2
= {
5125 .master
= &omap44xx_l4_per_hwmod
,
5126 .slave
= &omap44xx_mcspi2_hwmod
,
5128 .addr
= omap44xx_mcspi2_addrs
,
5129 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5132 static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs
[] = {
5134 .pa_start
= 0x480b8000,
5135 .pa_end
= 0x480b81ff,
5136 .flags
= ADDR_TYPE_RT
5141 /* l4_per -> mcspi3 */
5142 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3
= {
5143 .master
= &omap44xx_l4_per_hwmod
,
5144 .slave
= &omap44xx_mcspi3_hwmod
,
5146 .addr
= omap44xx_mcspi3_addrs
,
5147 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5150 static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs
[] = {
5152 .pa_start
= 0x480ba000,
5153 .pa_end
= 0x480ba1ff,
5154 .flags
= ADDR_TYPE_RT
5159 /* l4_per -> mcspi4 */
5160 static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4
= {
5161 .master
= &omap44xx_l4_per_hwmod
,
5162 .slave
= &omap44xx_mcspi4_hwmod
,
5164 .addr
= omap44xx_mcspi4_addrs
,
5165 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5168 static struct omap_hwmod_addr_space omap44xx_mmc1_addrs
[] = {
5170 .pa_start
= 0x4809c000,
5171 .pa_end
= 0x4809c3ff,
5172 .flags
= ADDR_TYPE_RT
5177 /* l4_per -> mmc1 */
5178 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1
= {
5179 .master
= &omap44xx_l4_per_hwmod
,
5180 .slave
= &omap44xx_mmc1_hwmod
,
5182 .addr
= omap44xx_mmc1_addrs
,
5183 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5186 static struct omap_hwmod_addr_space omap44xx_mmc2_addrs
[] = {
5188 .pa_start
= 0x480b4000,
5189 .pa_end
= 0x480b43ff,
5190 .flags
= ADDR_TYPE_RT
5195 /* l4_per -> mmc2 */
5196 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2
= {
5197 .master
= &omap44xx_l4_per_hwmod
,
5198 .slave
= &omap44xx_mmc2_hwmod
,
5200 .addr
= omap44xx_mmc2_addrs
,
5201 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5204 static struct omap_hwmod_addr_space omap44xx_mmc3_addrs
[] = {
5206 .pa_start
= 0x480ad000,
5207 .pa_end
= 0x480ad3ff,
5208 .flags
= ADDR_TYPE_RT
5213 /* l4_per -> mmc3 */
5214 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3
= {
5215 .master
= &omap44xx_l4_per_hwmod
,
5216 .slave
= &omap44xx_mmc3_hwmod
,
5218 .addr
= omap44xx_mmc3_addrs
,
5219 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5222 static struct omap_hwmod_addr_space omap44xx_mmc4_addrs
[] = {
5224 .pa_start
= 0x480d1000,
5225 .pa_end
= 0x480d13ff,
5226 .flags
= ADDR_TYPE_RT
5231 /* l4_per -> mmc4 */
5232 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4
= {
5233 .master
= &omap44xx_l4_per_hwmod
,
5234 .slave
= &omap44xx_mmc4_hwmod
,
5236 .addr
= omap44xx_mmc4_addrs
,
5237 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5240 static struct omap_hwmod_addr_space omap44xx_mmc5_addrs
[] = {
5242 .pa_start
= 0x480d5000,
5243 .pa_end
= 0x480d53ff,
5244 .flags
= ADDR_TYPE_RT
5249 /* l4_per -> mmc5 */
5250 static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5
= {
5251 .master
= &omap44xx_l4_per_hwmod
,
5252 .slave
= &omap44xx_mmc5_hwmod
,
5254 .addr
= omap44xx_mmc5_addrs
,
5255 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5258 /* l3_main_2 -> ocmc_ram */
5259 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram
= {
5260 .master
= &omap44xx_l3_main_2_hwmod
,
5261 .slave
= &omap44xx_ocmc_ram_hwmod
,
5263 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5266 /* l4_cfg -> ocp2scp_usb_phy */
5267 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy
= {
5268 .master
= &omap44xx_l4_cfg_hwmod
,
5269 .slave
= &omap44xx_ocp2scp_usb_phy_hwmod
,
5271 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5274 static struct omap_hwmod_addr_space omap44xx_prcm_mpu_addrs
[] = {
5276 .pa_start
= 0x48243000,
5277 .pa_end
= 0x48243fff,
5278 .flags
= ADDR_TYPE_RT
5283 /* mpu_private -> prcm_mpu */
5284 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu
= {
5285 .master
= &omap44xx_mpu_private_hwmod
,
5286 .slave
= &omap44xx_prcm_mpu_hwmod
,
5288 .addr
= omap44xx_prcm_mpu_addrs
,
5289 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5292 static struct omap_hwmod_addr_space omap44xx_cm_core_aon_addrs
[] = {
5294 .pa_start
= 0x4a004000,
5295 .pa_end
= 0x4a004fff,
5296 .flags
= ADDR_TYPE_RT
5301 /* l4_wkup -> cm_core_aon */
5302 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon
= {
5303 .master
= &omap44xx_l4_wkup_hwmod
,
5304 .slave
= &omap44xx_cm_core_aon_hwmod
,
5305 .clk
= "l4_wkup_clk_mux_ck",
5306 .addr
= omap44xx_cm_core_aon_addrs
,
5307 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5310 static struct omap_hwmod_addr_space omap44xx_cm_core_addrs
[] = {
5312 .pa_start
= 0x4a008000,
5313 .pa_end
= 0x4a009fff,
5314 .flags
= ADDR_TYPE_RT
5319 /* l4_cfg -> cm_core */
5320 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core
= {
5321 .master
= &omap44xx_l4_cfg_hwmod
,
5322 .slave
= &omap44xx_cm_core_hwmod
,
5324 .addr
= omap44xx_cm_core_addrs
,
5325 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5328 static struct omap_hwmod_addr_space omap44xx_prm_addrs
[] = {
5330 .pa_start
= 0x4a306000,
5331 .pa_end
= 0x4a307fff,
5332 .flags
= ADDR_TYPE_RT
5337 /* l4_wkup -> prm */
5338 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm
= {
5339 .master
= &omap44xx_l4_wkup_hwmod
,
5340 .slave
= &omap44xx_prm_hwmod
,
5341 .clk
= "l4_wkup_clk_mux_ck",
5342 .addr
= omap44xx_prm_addrs
,
5343 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5346 static struct omap_hwmod_addr_space omap44xx_scrm_addrs
[] = {
5348 .pa_start
= 0x4a30a000,
5349 .pa_end
= 0x4a30a7ff,
5350 .flags
= ADDR_TYPE_RT
5355 /* l4_wkup -> scrm */
5356 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm
= {
5357 .master
= &omap44xx_l4_wkup_hwmod
,
5358 .slave
= &omap44xx_scrm_hwmod
,
5359 .clk
= "l4_wkup_clk_mux_ck",
5360 .addr
= omap44xx_scrm_addrs
,
5361 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5364 /* l3_main_2 -> sl2if */
5365 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if
= {
5366 .master
= &omap44xx_l3_main_2_hwmod
,
5367 .slave
= &omap44xx_sl2if_hwmod
,
5369 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5372 static struct omap_hwmod_addr_space omap44xx_slimbus1_addrs
[] = {
5374 .pa_start
= 0x4012c000,
5375 .pa_end
= 0x4012c3ff,
5376 .flags
= ADDR_TYPE_RT
5381 /* l4_abe -> slimbus1 */
5382 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1
= {
5383 .master
= &omap44xx_l4_abe_hwmod
,
5384 .slave
= &omap44xx_slimbus1_hwmod
,
5385 .clk
= "ocp_abe_iclk",
5386 .addr
= omap44xx_slimbus1_addrs
,
5387 .user
= OCP_USER_MPU
,
5390 static struct omap_hwmod_addr_space omap44xx_slimbus1_dma_addrs
[] = {
5392 .pa_start
= 0x4902c000,
5393 .pa_end
= 0x4902c3ff,
5394 .flags
= ADDR_TYPE_RT
5399 /* l4_abe -> slimbus1 (dma) */
5400 static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma
= {
5401 .master
= &omap44xx_l4_abe_hwmod
,
5402 .slave
= &omap44xx_slimbus1_hwmod
,
5403 .clk
= "ocp_abe_iclk",
5404 .addr
= omap44xx_slimbus1_dma_addrs
,
5405 .user
= OCP_USER_SDMA
,
5408 static struct omap_hwmod_addr_space omap44xx_slimbus2_addrs
[] = {
5410 .pa_start
= 0x48076000,
5411 .pa_end
= 0x480763ff,
5412 .flags
= ADDR_TYPE_RT
5417 /* l4_per -> slimbus2 */
5418 static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2
= {
5419 .master
= &omap44xx_l4_per_hwmod
,
5420 .slave
= &omap44xx_slimbus2_hwmod
,
5422 .addr
= omap44xx_slimbus2_addrs
,
5423 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5426 static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs
[] = {
5428 .pa_start
= 0x4a0dd000,
5429 .pa_end
= 0x4a0dd03f,
5430 .flags
= ADDR_TYPE_RT
5435 /* l4_cfg -> smartreflex_core */
5436 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core
= {
5437 .master
= &omap44xx_l4_cfg_hwmod
,
5438 .slave
= &omap44xx_smartreflex_core_hwmod
,
5440 .addr
= omap44xx_smartreflex_core_addrs
,
5441 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5444 static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs
[] = {
5446 .pa_start
= 0x4a0db000,
5447 .pa_end
= 0x4a0db03f,
5448 .flags
= ADDR_TYPE_RT
5453 /* l4_cfg -> smartreflex_iva */
5454 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva
= {
5455 .master
= &omap44xx_l4_cfg_hwmod
,
5456 .slave
= &omap44xx_smartreflex_iva_hwmod
,
5458 .addr
= omap44xx_smartreflex_iva_addrs
,
5459 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5462 static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs
[] = {
5464 .pa_start
= 0x4a0d9000,
5465 .pa_end
= 0x4a0d903f,
5466 .flags
= ADDR_TYPE_RT
5471 /* l4_cfg -> smartreflex_mpu */
5472 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu
= {
5473 .master
= &omap44xx_l4_cfg_hwmod
,
5474 .slave
= &omap44xx_smartreflex_mpu_hwmod
,
5476 .addr
= omap44xx_smartreflex_mpu_addrs
,
5477 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5480 static struct omap_hwmod_addr_space omap44xx_spinlock_addrs
[] = {
5482 .pa_start
= 0x4a0f6000,
5483 .pa_end
= 0x4a0f6fff,
5484 .flags
= ADDR_TYPE_RT
5489 /* l4_cfg -> spinlock */
5490 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock
= {
5491 .master
= &omap44xx_l4_cfg_hwmod
,
5492 .slave
= &omap44xx_spinlock_hwmod
,
5494 .addr
= omap44xx_spinlock_addrs
,
5495 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5498 static struct omap_hwmod_addr_space omap44xx_timer1_addrs
[] = {
5500 .pa_start
= 0x4a318000,
5501 .pa_end
= 0x4a31807f,
5502 .flags
= ADDR_TYPE_RT
5507 /* l4_wkup -> timer1 */
5508 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1
= {
5509 .master
= &omap44xx_l4_wkup_hwmod
,
5510 .slave
= &omap44xx_timer1_hwmod
,
5511 .clk
= "l4_wkup_clk_mux_ck",
5512 .addr
= omap44xx_timer1_addrs
,
5513 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5516 static struct omap_hwmod_addr_space omap44xx_timer2_addrs
[] = {
5518 .pa_start
= 0x48032000,
5519 .pa_end
= 0x4803207f,
5520 .flags
= ADDR_TYPE_RT
5525 /* l4_per -> timer2 */
5526 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2
= {
5527 .master
= &omap44xx_l4_per_hwmod
,
5528 .slave
= &omap44xx_timer2_hwmod
,
5530 .addr
= omap44xx_timer2_addrs
,
5531 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5534 static struct omap_hwmod_addr_space omap44xx_timer3_addrs
[] = {
5536 .pa_start
= 0x48034000,
5537 .pa_end
= 0x4803407f,
5538 .flags
= ADDR_TYPE_RT
5543 /* l4_per -> timer3 */
5544 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3
= {
5545 .master
= &omap44xx_l4_per_hwmod
,
5546 .slave
= &omap44xx_timer3_hwmod
,
5548 .addr
= omap44xx_timer3_addrs
,
5549 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5552 static struct omap_hwmod_addr_space omap44xx_timer4_addrs
[] = {
5554 .pa_start
= 0x48036000,
5555 .pa_end
= 0x4803607f,
5556 .flags
= ADDR_TYPE_RT
5561 /* l4_per -> timer4 */
5562 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4
= {
5563 .master
= &omap44xx_l4_per_hwmod
,
5564 .slave
= &omap44xx_timer4_hwmod
,
5566 .addr
= omap44xx_timer4_addrs
,
5567 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5570 static struct omap_hwmod_addr_space omap44xx_timer5_addrs
[] = {
5572 .pa_start
= 0x40138000,
5573 .pa_end
= 0x4013807f,
5574 .flags
= ADDR_TYPE_RT
5579 /* l4_abe -> timer5 */
5580 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5
= {
5581 .master
= &omap44xx_l4_abe_hwmod
,
5582 .slave
= &omap44xx_timer5_hwmod
,
5583 .clk
= "ocp_abe_iclk",
5584 .addr
= omap44xx_timer5_addrs
,
5585 .user
= OCP_USER_MPU
,
5588 static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs
[] = {
5590 .pa_start
= 0x49038000,
5591 .pa_end
= 0x4903807f,
5592 .flags
= ADDR_TYPE_RT
5597 /* l4_abe -> timer5 (dma) */
5598 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma
= {
5599 .master
= &omap44xx_l4_abe_hwmod
,
5600 .slave
= &omap44xx_timer5_hwmod
,
5601 .clk
= "ocp_abe_iclk",
5602 .addr
= omap44xx_timer5_dma_addrs
,
5603 .user
= OCP_USER_SDMA
,
5606 static struct omap_hwmod_addr_space omap44xx_timer6_addrs
[] = {
5608 .pa_start
= 0x4013a000,
5609 .pa_end
= 0x4013a07f,
5610 .flags
= ADDR_TYPE_RT
5615 /* l4_abe -> timer6 */
5616 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6
= {
5617 .master
= &omap44xx_l4_abe_hwmod
,
5618 .slave
= &omap44xx_timer6_hwmod
,
5619 .clk
= "ocp_abe_iclk",
5620 .addr
= omap44xx_timer6_addrs
,
5621 .user
= OCP_USER_MPU
,
5624 static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs
[] = {
5626 .pa_start
= 0x4903a000,
5627 .pa_end
= 0x4903a07f,
5628 .flags
= ADDR_TYPE_RT
5633 /* l4_abe -> timer6 (dma) */
5634 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma
= {
5635 .master
= &omap44xx_l4_abe_hwmod
,
5636 .slave
= &omap44xx_timer6_hwmod
,
5637 .clk
= "ocp_abe_iclk",
5638 .addr
= omap44xx_timer6_dma_addrs
,
5639 .user
= OCP_USER_SDMA
,
5642 static struct omap_hwmod_addr_space omap44xx_timer7_addrs
[] = {
5644 .pa_start
= 0x4013c000,
5645 .pa_end
= 0x4013c07f,
5646 .flags
= ADDR_TYPE_RT
5651 /* l4_abe -> timer7 */
5652 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7
= {
5653 .master
= &omap44xx_l4_abe_hwmod
,
5654 .slave
= &omap44xx_timer7_hwmod
,
5655 .clk
= "ocp_abe_iclk",
5656 .addr
= omap44xx_timer7_addrs
,
5657 .user
= OCP_USER_MPU
,
5660 static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs
[] = {
5662 .pa_start
= 0x4903c000,
5663 .pa_end
= 0x4903c07f,
5664 .flags
= ADDR_TYPE_RT
5669 /* l4_abe -> timer7 (dma) */
5670 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma
= {
5671 .master
= &omap44xx_l4_abe_hwmod
,
5672 .slave
= &omap44xx_timer7_hwmod
,
5673 .clk
= "ocp_abe_iclk",
5674 .addr
= omap44xx_timer7_dma_addrs
,
5675 .user
= OCP_USER_SDMA
,
5678 static struct omap_hwmod_addr_space omap44xx_timer8_addrs
[] = {
5680 .pa_start
= 0x4013e000,
5681 .pa_end
= 0x4013e07f,
5682 .flags
= ADDR_TYPE_RT
5687 /* l4_abe -> timer8 */
5688 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8
= {
5689 .master
= &omap44xx_l4_abe_hwmod
,
5690 .slave
= &omap44xx_timer8_hwmod
,
5691 .clk
= "ocp_abe_iclk",
5692 .addr
= omap44xx_timer8_addrs
,
5693 .user
= OCP_USER_MPU
,
5696 static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs
[] = {
5698 .pa_start
= 0x4903e000,
5699 .pa_end
= 0x4903e07f,
5700 .flags
= ADDR_TYPE_RT
5705 /* l4_abe -> timer8 (dma) */
5706 static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma
= {
5707 .master
= &omap44xx_l4_abe_hwmod
,
5708 .slave
= &omap44xx_timer8_hwmod
,
5709 .clk
= "ocp_abe_iclk",
5710 .addr
= omap44xx_timer8_dma_addrs
,
5711 .user
= OCP_USER_SDMA
,
5714 static struct omap_hwmod_addr_space omap44xx_timer9_addrs
[] = {
5716 .pa_start
= 0x4803e000,
5717 .pa_end
= 0x4803e07f,
5718 .flags
= ADDR_TYPE_RT
5723 /* l4_per -> timer9 */
5724 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9
= {
5725 .master
= &omap44xx_l4_per_hwmod
,
5726 .slave
= &omap44xx_timer9_hwmod
,
5728 .addr
= omap44xx_timer9_addrs
,
5729 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5732 static struct omap_hwmod_addr_space omap44xx_timer10_addrs
[] = {
5734 .pa_start
= 0x48086000,
5735 .pa_end
= 0x4808607f,
5736 .flags
= ADDR_TYPE_RT
5741 /* l4_per -> timer10 */
5742 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10
= {
5743 .master
= &omap44xx_l4_per_hwmod
,
5744 .slave
= &omap44xx_timer10_hwmod
,
5746 .addr
= omap44xx_timer10_addrs
,
5747 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5750 static struct omap_hwmod_addr_space omap44xx_timer11_addrs
[] = {
5752 .pa_start
= 0x48088000,
5753 .pa_end
= 0x4808807f,
5754 .flags
= ADDR_TYPE_RT
5759 /* l4_per -> timer11 */
5760 static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11
= {
5761 .master
= &omap44xx_l4_per_hwmod
,
5762 .slave
= &omap44xx_timer11_hwmod
,
5764 .addr
= omap44xx_timer11_addrs
,
5765 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5768 static struct omap_hwmod_addr_space omap44xx_uart1_addrs
[] = {
5770 .pa_start
= 0x4806a000,
5771 .pa_end
= 0x4806a0ff,
5772 .flags
= ADDR_TYPE_RT
5777 /* l4_per -> uart1 */
5778 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1
= {
5779 .master
= &omap44xx_l4_per_hwmod
,
5780 .slave
= &omap44xx_uart1_hwmod
,
5782 .addr
= omap44xx_uart1_addrs
,
5783 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5786 static struct omap_hwmod_addr_space omap44xx_uart2_addrs
[] = {
5788 .pa_start
= 0x4806c000,
5789 .pa_end
= 0x4806c0ff,
5790 .flags
= ADDR_TYPE_RT
5795 /* l4_per -> uart2 */
5796 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2
= {
5797 .master
= &omap44xx_l4_per_hwmod
,
5798 .slave
= &omap44xx_uart2_hwmod
,
5800 .addr
= omap44xx_uart2_addrs
,
5801 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5804 static struct omap_hwmod_addr_space omap44xx_uart3_addrs
[] = {
5806 .pa_start
= 0x48020000,
5807 .pa_end
= 0x480200ff,
5808 .flags
= ADDR_TYPE_RT
5813 /* l4_per -> uart3 */
5814 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3
= {
5815 .master
= &omap44xx_l4_per_hwmod
,
5816 .slave
= &omap44xx_uart3_hwmod
,
5818 .addr
= omap44xx_uart3_addrs
,
5819 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5822 static struct omap_hwmod_addr_space omap44xx_uart4_addrs
[] = {
5824 .pa_start
= 0x4806e000,
5825 .pa_end
= 0x4806e0ff,
5826 .flags
= ADDR_TYPE_RT
5831 /* l4_per -> uart4 */
5832 static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4
= {
5833 .master
= &omap44xx_l4_per_hwmod
,
5834 .slave
= &omap44xx_uart4_hwmod
,
5836 .addr
= omap44xx_uart4_addrs
,
5837 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5840 static struct omap_hwmod_addr_space omap44xx_usb_host_fs_addrs
[] = {
5842 .pa_start
= 0x4a0a9000,
5843 .pa_end
= 0x4a0a93ff,
5844 .flags
= ADDR_TYPE_RT
5849 /* l4_cfg -> usb_host_fs */
5850 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs
= {
5851 .master
= &omap44xx_l4_cfg_hwmod
,
5852 .slave
= &omap44xx_usb_host_fs_hwmod
,
5854 .addr
= omap44xx_usb_host_fs_addrs
,
5855 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5858 static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs
[] = {
5861 .pa_start
= 0x4a064000,
5862 .pa_end
= 0x4a0647ff,
5863 .flags
= ADDR_TYPE_RT
5867 .pa_start
= 0x4a064800,
5868 .pa_end
= 0x4a064bff,
5872 .pa_start
= 0x4a064c00,
5873 .pa_end
= 0x4a064fff,
5878 /* l4_cfg -> usb_host_hs */
5879 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs
= {
5880 .master
= &omap44xx_l4_cfg_hwmod
,
5881 .slave
= &omap44xx_usb_host_hs_hwmod
,
5883 .addr
= omap44xx_usb_host_hs_addrs
,
5884 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5887 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs
[] = {
5889 .pa_start
= 0x4a0ab000,
5890 .pa_end
= 0x4a0ab003,
5891 .flags
= ADDR_TYPE_RT
5896 /* l4_cfg -> usb_otg_hs */
5897 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs
= {
5898 .master
= &omap44xx_l4_cfg_hwmod
,
5899 .slave
= &omap44xx_usb_otg_hs_hwmod
,
5901 .addr
= omap44xx_usb_otg_hs_addrs
,
5902 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5905 static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs
[] = {
5908 .pa_start
= 0x4a062000,
5909 .pa_end
= 0x4a063fff,
5910 .flags
= ADDR_TYPE_RT
5915 /* l4_cfg -> usb_tll_hs */
5916 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs
= {
5917 .master
= &omap44xx_l4_cfg_hwmod
,
5918 .slave
= &omap44xx_usb_tll_hs_hwmod
,
5920 .addr
= omap44xx_usb_tll_hs_addrs
,
5921 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5924 static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs
[] = {
5926 .pa_start
= 0x4a314000,
5927 .pa_end
= 0x4a31407f,
5928 .flags
= ADDR_TYPE_RT
5933 /* l4_wkup -> wd_timer2 */
5934 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2
= {
5935 .master
= &omap44xx_l4_wkup_hwmod
,
5936 .slave
= &omap44xx_wd_timer2_hwmod
,
5937 .clk
= "l4_wkup_clk_mux_ck",
5938 .addr
= omap44xx_wd_timer2_addrs
,
5939 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
5942 static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs
[] = {
5944 .pa_start
= 0x40130000,
5945 .pa_end
= 0x4013007f,
5946 .flags
= ADDR_TYPE_RT
5951 /* l4_abe -> wd_timer3 */
5952 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3
= {
5953 .master
= &omap44xx_l4_abe_hwmod
,
5954 .slave
= &omap44xx_wd_timer3_hwmod
,
5955 .clk
= "ocp_abe_iclk",
5956 .addr
= omap44xx_wd_timer3_addrs
,
5957 .user
= OCP_USER_MPU
,
5960 static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs
[] = {
5962 .pa_start
= 0x49030000,
5963 .pa_end
= 0x4903007f,
5964 .flags
= ADDR_TYPE_RT
5969 /* l4_abe -> wd_timer3 (dma) */
5970 static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma
= {
5971 .master
= &omap44xx_l4_abe_hwmod
,
5972 .slave
= &omap44xx_wd_timer3_hwmod
,
5973 .clk
= "ocp_abe_iclk",
5974 .addr
= omap44xx_wd_timer3_dma_addrs
,
5975 .user
= OCP_USER_SDMA
,
5978 static struct omap_hwmod_ocp_if
*omap44xx_hwmod_ocp_ifs
[] __initdata
= {
5979 &omap44xx_c2c__c2c_target_fw
,
5980 &omap44xx_l4_cfg__c2c_target_fw
,
5981 &omap44xx_l3_main_1__dmm
,
5983 &omap44xx_c2c__emif_fw
,
5984 &omap44xx_dmm__emif_fw
,
5985 &omap44xx_l4_cfg__emif_fw
,
5986 &omap44xx_iva__l3_instr
,
5987 &omap44xx_l3_main_3__l3_instr
,
5988 &omap44xx_ocp_wp_noc__l3_instr
,
5989 &omap44xx_dsp__l3_main_1
,
5990 &omap44xx_dss__l3_main_1
,
5991 &omap44xx_l3_main_2__l3_main_1
,
5992 &omap44xx_l4_cfg__l3_main_1
,
5993 &omap44xx_mmc1__l3_main_1
,
5994 &omap44xx_mmc2__l3_main_1
,
5995 &omap44xx_mpu__l3_main_1
,
5996 &omap44xx_c2c_target_fw__l3_main_2
,
5997 &omap44xx_debugss__l3_main_2
,
5998 &omap44xx_dma_system__l3_main_2
,
5999 &omap44xx_fdif__l3_main_2
,
6000 &omap44xx_gpu__l3_main_2
,
6001 &omap44xx_hsi__l3_main_2
,
6002 &omap44xx_ipu__l3_main_2
,
6003 &omap44xx_iss__l3_main_2
,
6004 &omap44xx_iva__l3_main_2
,
6005 &omap44xx_l3_main_1__l3_main_2
,
6006 &omap44xx_l4_cfg__l3_main_2
,
6007 /* &omap44xx_usb_host_fs__l3_main_2, */
6008 &omap44xx_usb_host_hs__l3_main_2
,
6009 &omap44xx_usb_otg_hs__l3_main_2
,
6010 &omap44xx_l3_main_1__l3_main_3
,
6011 &omap44xx_l3_main_2__l3_main_3
,
6012 &omap44xx_l4_cfg__l3_main_3
,
6013 /* &omap44xx_aess__l4_abe, */
6014 &omap44xx_dsp__l4_abe
,
6015 &omap44xx_l3_main_1__l4_abe
,
6016 &omap44xx_mpu__l4_abe
,
6017 &omap44xx_l3_main_1__l4_cfg
,
6018 &omap44xx_l3_main_2__l4_per
,
6019 &omap44xx_l4_cfg__l4_wkup
,
6020 &omap44xx_mpu__mpu_private
,
6021 &omap44xx_l4_cfg__ocp_wp_noc
,
6022 /* &omap44xx_l4_abe__aess, */
6023 /* &omap44xx_l4_abe__aess_dma, */
6024 &omap44xx_l3_main_2__c2c
,
6025 &omap44xx_l4_wkup__counter_32k
,
6026 &omap44xx_l4_cfg__ctrl_module_core
,
6027 &omap44xx_l4_cfg__ctrl_module_pad_core
,
6028 &omap44xx_l4_wkup__ctrl_module_wkup
,
6029 &omap44xx_l4_wkup__ctrl_module_pad_wkup
,
6030 &omap44xx_l3_instr__debugss
,
6031 &omap44xx_l4_cfg__dma_system
,
6032 &omap44xx_l4_abe__dmic
,
6033 &omap44xx_l4_abe__dmic_dma
,
6035 &omap44xx_dsp__sl2if
,
6036 &omap44xx_l4_cfg__dsp
,
6037 &omap44xx_l3_main_2__dss
,
6038 &omap44xx_l4_per__dss
,
6039 &omap44xx_l3_main_2__dss_dispc
,
6040 &omap44xx_l4_per__dss_dispc
,
6041 &omap44xx_l3_main_2__dss_dsi1
,
6042 &omap44xx_l4_per__dss_dsi1
,
6043 &omap44xx_l3_main_2__dss_dsi2
,
6044 &omap44xx_l4_per__dss_dsi2
,
6045 &omap44xx_l3_main_2__dss_hdmi
,
6046 &omap44xx_l4_per__dss_hdmi
,
6047 &omap44xx_l3_main_2__dss_rfbi
,
6048 &omap44xx_l4_per__dss_rfbi
,
6049 &omap44xx_l3_main_2__dss_venc
,
6050 &omap44xx_l4_per__dss_venc
,
6051 &omap44xx_l4_per__elm
,
6052 &omap44xx_emif_fw__emif1
,
6053 &omap44xx_emif_fw__emif2
,
6054 &omap44xx_l4_cfg__fdif
,
6055 &omap44xx_l4_wkup__gpio1
,
6056 &omap44xx_l4_per__gpio2
,
6057 &omap44xx_l4_per__gpio3
,
6058 &omap44xx_l4_per__gpio4
,
6059 &omap44xx_l4_per__gpio5
,
6060 &omap44xx_l4_per__gpio6
,
6061 &omap44xx_l3_main_2__gpmc
,
6062 &omap44xx_l3_main_2__gpu
,
6063 &omap44xx_l4_per__hdq1w
,
6064 &omap44xx_l4_cfg__hsi
,
6065 &omap44xx_l4_per__i2c1
,
6066 &omap44xx_l4_per__i2c2
,
6067 &omap44xx_l4_per__i2c3
,
6068 &omap44xx_l4_per__i2c4
,
6069 &omap44xx_l3_main_2__ipu
,
6070 &omap44xx_l3_main_2__iss
,
6071 &omap44xx_iva__sl2if
,
6072 &omap44xx_l3_main_2__iva
,
6073 &omap44xx_l4_wkup__kbd
,
6074 &omap44xx_l4_cfg__mailbox
,
6075 &omap44xx_l4_abe__mcasp
,
6076 &omap44xx_l4_abe__mcasp_dma
,
6077 &omap44xx_l4_abe__mcbsp1
,
6078 &omap44xx_l4_abe__mcbsp1_dma
,
6079 &omap44xx_l4_abe__mcbsp2
,
6080 &omap44xx_l4_abe__mcbsp2_dma
,
6081 &omap44xx_l4_abe__mcbsp3
,
6082 &omap44xx_l4_abe__mcbsp3_dma
,
6083 &omap44xx_l4_per__mcbsp4
,
6084 &omap44xx_l4_abe__mcpdm
,
6085 &omap44xx_l4_abe__mcpdm_dma
,
6086 &omap44xx_l4_per__mcspi1
,
6087 &omap44xx_l4_per__mcspi2
,
6088 &omap44xx_l4_per__mcspi3
,
6089 &omap44xx_l4_per__mcspi4
,
6090 &omap44xx_l4_per__mmc1
,
6091 &omap44xx_l4_per__mmc2
,
6092 &omap44xx_l4_per__mmc3
,
6093 &omap44xx_l4_per__mmc4
,
6094 &omap44xx_l4_per__mmc5
,
6095 &omap44xx_l3_main_2__ocmc_ram
,
6096 &omap44xx_l4_cfg__ocp2scp_usb_phy
,
6097 &omap44xx_mpu_private__prcm_mpu
,
6098 &omap44xx_l4_wkup__cm_core_aon
,
6099 &omap44xx_l4_cfg__cm_core
,
6100 &omap44xx_l4_wkup__prm
,
6101 &omap44xx_l4_wkup__scrm
,
6102 &omap44xx_l3_main_2__sl2if
,
6103 &omap44xx_l4_abe__slimbus1
,
6104 &omap44xx_l4_abe__slimbus1_dma
,
6105 &omap44xx_l4_per__slimbus2
,
6106 &omap44xx_l4_cfg__smartreflex_core
,
6107 &omap44xx_l4_cfg__smartreflex_iva
,
6108 &omap44xx_l4_cfg__smartreflex_mpu
,
6109 &omap44xx_l4_cfg__spinlock
,
6110 &omap44xx_l4_wkup__timer1
,
6111 &omap44xx_l4_per__timer2
,
6112 &omap44xx_l4_per__timer3
,
6113 &omap44xx_l4_per__timer4
,
6114 &omap44xx_l4_abe__timer5
,
6115 &omap44xx_l4_abe__timer5_dma
,
6116 &omap44xx_l4_abe__timer6
,
6117 &omap44xx_l4_abe__timer6_dma
,
6118 &omap44xx_l4_abe__timer7
,
6119 &omap44xx_l4_abe__timer7_dma
,
6120 &omap44xx_l4_abe__timer8
,
6121 &omap44xx_l4_abe__timer8_dma
,
6122 &omap44xx_l4_per__timer9
,
6123 &omap44xx_l4_per__timer10
,
6124 &omap44xx_l4_per__timer11
,
6125 &omap44xx_l4_per__uart1
,
6126 &omap44xx_l4_per__uart2
,
6127 &omap44xx_l4_per__uart3
,
6128 &omap44xx_l4_per__uart4
,
6129 /* &omap44xx_l4_cfg__usb_host_fs, */
6130 &omap44xx_l4_cfg__usb_host_hs
,
6131 &omap44xx_l4_cfg__usb_otg_hs
,
6132 &omap44xx_l4_cfg__usb_tll_hs
,
6133 &omap44xx_l4_wkup__wd_timer2
,
6134 &omap44xx_l4_abe__wd_timer3
,
6135 &omap44xx_l4_abe__wd_timer3_dma
,
6139 int __init
omap44xx_hwmod_init(void)
6142 return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs
);