2 * Hardware modules present on the OMAP54xx chips
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/i2c-omap.h>
25 #include <linux/omap-dma.h>
26 #include <linux/platform_data/spi-omap2-mcspi.h>
27 #include <linux/platform_data/asoc-ti-mcbsp.h>
28 #include <plat/dmtimer.h>
30 #include "omap_hwmod.h"
31 #include "omap_hwmod_common_data.h"
39 /* Base offset for all OMAP5 interrupts external to MPUSS */
40 #define OMAP54XX_IRQ_GIC_START 32
42 /* Base offset for all OMAP5 dma requests */
43 #define OMAP54XX_DMA_REQ_START 1
54 static struct omap_hwmod_class omap54xx_dmm_hwmod_class
= {
59 static struct omap_hwmod omap54xx_dmm_hwmod
= {
61 .class = &omap54xx_dmm_hwmod_class
,
62 .clkdm_name
= "emif_clkdm",
65 .clkctrl_offs
= OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET
,
66 .context_offs
= OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET
,
73 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
75 static struct omap_hwmod_class omap54xx_l3_hwmod_class
= {
80 static struct omap_hwmod omap54xx_l3_instr_hwmod
= {
82 .class = &omap54xx_l3_hwmod_class
,
83 .clkdm_name
= "l3instr_clkdm",
86 .clkctrl_offs
= OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET
,
87 .context_offs
= OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET
,
88 .modulemode
= MODULEMODE_HWCTRL
,
94 static struct omap_hwmod omap54xx_l3_main_1_hwmod
= {
96 .class = &omap54xx_l3_hwmod_class
,
97 .clkdm_name
= "l3main1_clkdm",
100 .clkctrl_offs
= OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET
,
101 .context_offs
= OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET
,
107 static struct omap_hwmod omap54xx_l3_main_2_hwmod
= {
109 .class = &omap54xx_l3_hwmod_class
,
110 .clkdm_name
= "l3main2_clkdm",
113 .clkctrl_offs
= OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET
,
114 .context_offs
= OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET
,
120 static struct omap_hwmod omap54xx_l3_main_3_hwmod
= {
122 .class = &omap54xx_l3_hwmod_class
,
123 .clkdm_name
= "l3instr_clkdm",
126 .clkctrl_offs
= OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET
,
127 .context_offs
= OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET
,
128 .modulemode
= MODULEMODE_HWCTRL
,
135 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
137 static struct omap_hwmod_class omap54xx_l4_hwmod_class
= {
142 static struct omap_hwmod omap54xx_l4_abe_hwmod
= {
144 .class = &omap54xx_l4_hwmod_class
,
145 .clkdm_name
= "abe_clkdm",
148 .clkctrl_offs
= OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET
,
149 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
155 static struct omap_hwmod omap54xx_l4_cfg_hwmod
= {
157 .class = &omap54xx_l4_hwmod_class
,
158 .clkdm_name
= "l4cfg_clkdm",
161 .clkctrl_offs
= OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET
,
162 .context_offs
= OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET
,
168 static struct omap_hwmod omap54xx_l4_per_hwmod
= {
170 .class = &omap54xx_l4_hwmod_class
,
171 .clkdm_name
= "l4per_clkdm",
174 .clkctrl_offs
= OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET
,
175 .context_offs
= OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET
,
181 static struct omap_hwmod omap54xx_l4_wkup_hwmod
= {
183 .class = &omap54xx_l4_hwmod_class
,
184 .clkdm_name
= "wkupaon_clkdm",
187 .clkctrl_offs
= OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET
,
188 .context_offs
= OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET
,
195 * instance(s): mpu_private
197 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class
= {
202 static struct omap_hwmod omap54xx_mpu_private_hwmod
= {
203 .name
= "mpu_private",
204 .class = &omap54xx_mpu_bus_hwmod_class
,
205 .clkdm_name
= "mpu_clkdm",
208 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
215 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
218 static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc
= {
221 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
222 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
),
223 .sysc_fields
= &omap_hwmod_sysc_type1
,
226 static struct omap_hwmod_class omap54xx_counter_hwmod_class
= {
228 .sysc
= &omap54xx_counter_sysc
,
232 static struct omap_hwmod omap54xx_counter_32k_hwmod
= {
233 .name
= "counter_32k",
234 .class = &omap54xx_counter_hwmod_class
,
235 .clkdm_name
= "wkupaon_clkdm",
236 .flags
= HWMOD_SWSUP_SIDLE
,
237 .main_clk
= "wkupaon_iclk_mux",
240 .clkctrl_offs
= OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET
,
241 .context_offs
= OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET
,
248 * dma controller for data exchange between memory to memory (i.e. internal or
249 * external memory) and gp peripherals to memory or memory to gp peripherals
252 static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc
= {
256 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
257 SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
258 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
259 SYSS_HAS_RESET_STATUS
),
260 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
261 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
262 .sysc_fields
= &omap_hwmod_sysc_type1
,
265 static struct omap_hwmod_class omap54xx_dma_hwmod_class
= {
267 .sysc
= &omap54xx_dma_sysc
,
271 static struct omap_dma_dev_attr dma_dev_attr
= {
272 .dev_caps
= RESERVE_CHANNEL
| DMA_LINKED_LCH
| GLOBAL_PRIORITY
|
273 IS_CSSA_32
| IS_CDSA_32
| IS_RW_PRIORITY
,
278 static struct omap_hwmod_irq_info omap54xx_dma_system_irqs
[] = {
279 { .name
= "0", .irq
= 12 + OMAP54XX_IRQ_GIC_START
},
280 { .name
= "1", .irq
= 13 + OMAP54XX_IRQ_GIC_START
},
281 { .name
= "2", .irq
= 14 + OMAP54XX_IRQ_GIC_START
},
282 { .name
= "3", .irq
= 15 + OMAP54XX_IRQ_GIC_START
},
286 static struct omap_hwmod omap54xx_dma_system_hwmod
= {
287 .name
= "dma_system",
288 .class = &omap54xx_dma_hwmod_class
,
289 .clkdm_name
= "dma_clkdm",
290 .mpu_irqs
= omap54xx_dma_system_irqs
,
291 .main_clk
= "l3_iclk_div",
294 .clkctrl_offs
= OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET
,
295 .context_offs
= OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET
,
298 .dev_attr
= &dma_dev_attr
,
303 * digital microphone controller
306 static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc
= {
309 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
310 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
311 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
313 .sysc_fields
= &omap_hwmod_sysc_type2
,
316 static struct omap_hwmod_class omap54xx_dmic_hwmod_class
= {
318 .sysc
= &omap54xx_dmic_sysc
,
322 static struct omap_hwmod omap54xx_dmic_hwmod
= {
324 .class = &omap54xx_dmic_hwmod_class
,
325 .clkdm_name
= "abe_clkdm",
326 .main_clk
= "dmic_gfclk",
329 .clkctrl_offs
= OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET
,
330 .context_offs
= OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET
,
331 .modulemode
= MODULEMODE_SWCTRL
,
338 * external memory interface no1 (wrapper)
341 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc
= {
345 static struct omap_hwmod_class omap54xx_emif_hwmod_class
= {
347 .sysc
= &omap54xx_emif_sysc
,
351 static struct omap_hwmod omap54xx_emif1_hwmod
= {
353 .class = &omap54xx_emif_hwmod_class
,
354 .clkdm_name
= "emif_clkdm",
355 .flags
= HWMOD_INIT_NO_IDLE
,
356 .main_clk
= "dpll_core_h11x2_ck",
359 .clkctrl_offs
= OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET
,
360 .context_offs
= OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET
,
361 .modulemode
= MODULEMODE_HWCTRL
,
367 static struct omap_hwmod omap54xx_emif2_hwmod
= {
369 .class = &omap54xx_emif_hwmod_class
,
370 .clkdm_name
= "emif_clkdm",
371 .flags
= HWMOD_INIT_NO_IDLE
,
372 .main_clk
= "dpll_core_h11x2_ck",
375 .clkctrl_offs
= OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET
,
376 .context_offs
= OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET
,
377 .modulemode
= MODULEMODE_HWCTRL
,
384 * general purpose io module
387 static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc
= {
391 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
392 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
393 SYSS_HAS_RESET_STATUS
),
394 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
396 .sysc_fields
= &omap_hwmod_sysc_type1
,
399 static struct omap_hwmod_class omap54xx_gpio_hwmod_class
= {
401 .sysc
= &omap54xx_gpio_sysc
,
406 static struct omap_gpio_dev_attr gpio_dev_attr
= {
412 static struct omap_hwmod_opt_clk gpio1_opt_clks
[] = {
413 { .role
= "dbclk", .clk
= "gpio1_dbclk" },
416 static struct omap_hwmod omap54xx_gpio1_hwmod
= {
418 .class = &omap54xx_gpio_hwmod_class
,
419 .clkdm_name
= "wkupaon_clkdm",
420 .main_clk
= "wkupaon_iclk_mux",
423 .clkctrl_offs
= OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET
,
424 .context_offs
= OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET
,
425 .modulemode
= MODULEMODE_HWCTRL
,
428 .opt_clks
= gpio1_opt_clks
,
429 .opt_clks_cnt
= ARRAY_SIZE(gpio1_opt_clks
),
430 .dev_attr
= &gpio_dev_attr
,
434 static struct omap_hwmod_opt_clk gpio2_opt_clks
[] = {
435 { .role
= "dbclk", .clk
= "gpio2_dbclk" },
438 static struct omap_hwmod omap54xx_gpio2_hwmod
= {
440 .class = &omap54xx_gpio_hwmod_class
,
441 .clkdm_name
= "l4per_clkdm",
442 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
443 .main_clk
= "l4_root_clk_div",
446 .clkctrl_offs
= OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET
,
447 .context_offs
= OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET
,
448 .modulemode
= MODULEMODE_HWCTRL
,
451 .opt_clks
= gpio2_opt_clks
,
452 .opt_clks_cnt
= ARRAY_SIZE(gpio2_opt_clks
),
453 .dev_attr
= &gpio_dev_attr
,
457 static struct omap_hwmod_opt_clk gpio3_opt_clks
[] = {
458 { .role
= "dbclk", .clk
= "gpio3_dbclk" },
461 static struct omap_hwmod omap54xx_gpio3_hwmod
= {
463 .class = &omap54xx_gpio_hwmod_class
,
464 .clkdm_name
= "l4per_clkdm",
465 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
466 .main_clk
= "l4_root_clk_div",
469 .clkctrl_offs
= OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET
,
470 .context_offs
= OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET
,
471 .modulemode
= MODULEMODE_HWCTRL
,
474 .opt_clks
= gpio3_opt_clks
,
475 .opt_clks_cnt
= ARRAY_SIZE(gpio3_opt_clks
),
476 .dev_attr
= &gpio_dev_attr
,
480 static struct omap_hwmod_opt_clk gpio4_opt_clks
[] = {
481 { .role
= "dbclk", .clk
= "gpio4_dbclk" },
484 static struct omap_hwmod omap54xx_gpio4_hwmod
= {
486 .class = &omap54xx_gpio_hwmod_class
,
487 .clkdm_name
= "l4per_clkdm",
488 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
489 .main_clk
= "l4_root_clk_div",
492 .clkctrl_offs
= OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET
,
493 .context_offs
= OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET
,
494 .modulemode
= MODULEMODE_HWCTRL
,
497 .opt_clks
= gpio4_opt_clks
,
498 .opt_clks_cnt
= ARRAY_SIZE(gpio4_opt_clks
),
499 .dev_attr
= &gpio_dev_attr
,
503 static struct omap_hwmod_opt_clk gpio5_opt_clks
[] = {
504 { .role
= "dbclk", .clk
= "gpio5_dbclk" },
507 static struct omap_hwmod omap54xx_gpio5_hwmod
= {
509 .class = &omap54xx_gpio_hwmod_class
,
510 .clkdm_name
= "l4per_clkdm",
511 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
512 .main_clk
= "l4_root_clk_div",
515 .clkctrl_offs
= OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET
,
516 .context_offs
= OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET
,
517 .modulemode
= MODULEMODE_HWCTRL
,
520 .opt_clks
= gpio5_opt_clks
,
521 .opt_clks_cnt
= ARRAY_SIZE(gpio5_opt_clks
),
522 .dev_attr
= &gpio_dev_attr
,
526 static struct omap_hwmod_opt_clk gpio6_opt_clks
[] = {
527 { .role
= "dbclk", .clk
= "gpio6_dbclk" },
530 static struct omap_hwmod omap54xx_gpio6_hwmod
= {
532 .class = &omap54xx_gpio_hwmod_class
,
533 .clkdm_name
= "l4per_clkdm",
534 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
535 .main_clk
= "l4_root_clk_div",
538 .clkctrl_offs
= OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET
,
539 .context_offs
= OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET
,
540 .modulemode
= MODULEMODE_HWCTRL
,
543 .opt_clks
= gpio6_opt_clks
,
544 .opt_clks_cnt
= ARRAY_SIZE(gpio6_opt_clks
),
545 .dev_attr
= &gpio_dev_attr
,
549 static struct omap_hwmod_opt_clk gpio7_opt_clks
[] = {
550 { .role
= "dbclk", .clk
= "gpio7_dbclk" },
553 static struct omap_hwmod omap54xx_gpio7_hwmod
= {
555 .class = &omap54xx_gpio_hwmod_class
,
556 .clkdm_name
= "l4per_clkdm",
557 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
558 .main_clk
= "l4_root_clk_div",
561 .clkctrl_offs
= OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET
,
562 .context_offs
= OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET
,
563 .modulemode
= MODULEMODE_HWCTRL
,
566 .opt_clks
= gpio7_opt_clks
,
567 .opt_clks_cnt
= ARRAY_SIZE(gpio7_opt_clks
),
568 .dev_attr
= &gpio_dev_attr
,
572 static struct omap_hwmod_opt_clk gpio8_opt_clks
[] = {
573 { .role
= "dbclk", .clk
= "gpio8_dbclk" },
576 static struct omap_hwmod omap54xx_gpio8_hwmod
= {
578 .class = &omap54xx_gpio_hwmod_class
,
579 .clkdm_name
= "l4per_clkdm",
580 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
581 .main_clk
= "l4_root_clk_div",
584 .clkctrl_offs
= OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET
,
585 .context_offs
= OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET
,
586 .modulemode
= MODULEMODE_HWCTRL
,
589 .opt_clks
= gpio8_opt_clks
,
590 .opt_clks_cnt
= ARRAY_SIZE(gpio8_opt_clks
),
591 .dev_attr
= &gpio_dev_attr
,
596 * multimaster high-speed i2c controller
599 static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc
= {
602 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
603 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
604 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
605 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
607 .clockact
= CLOCKACT_TEST_ICLK
,
608 .sysc_fields
= &omap_hwmod_sysc_type1
,
611 static struct omap_hwmod_class omap54xx_i2c_hwmod_class
= {
613 .sysc
= &omap54xx_i2c_sysc
,
614 .reset
= &omap_i2c_reset
,
615 .rev
= OMAP_I2C_IP_VERSION_2
,
619 static struct omap_i2c_dev_attr i2c_dev_attr
= {
620 .flags
= OMAP_I2C_FLAG_BUS_SHIFT_NONE
,
624 static struct omap_hwmod omap54xx_i2c1_hwmod
= {
626 .class = &omap54xx_i2c_hwmod_class
,
627 .clkdm_name
= "l4per_clkdm",
628 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
629 .main_clk
= "func_96m_fclk",
632 .clkctrl_offs
= OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET
,
633 .context_offs
= OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET
,
634 .modulemode
= MODULEMODE_SWCTRL
,
637 .dev_attr
= &i2c_dev_attr
,
641 static struct omap_hwmod omap54xx_i2c2_hwmod
= {
643 .class = &omap54xx_i2c_hwmod_class
,
644 .clkdm_name
= "l4per_clkdm",
645 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
646 .main_clk
= "func_96m_fclk",
649 .clkctrl_offs
= OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET
,
650 .context_offs
= OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET
,
651 .modulemode
= MODULEMODE_SWCTRL
,
654 .dev_attr
= &i2c_dev_attr
,
658 static struct omap_hwmod omap54xx_i2c3_hwmod
= {
660 .class = &omap54xx_i2c_hwmod_class
,
661 .clkdm_name
= "l4per_clkdm",
662 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
663 .main_clk
= "func_96m_fclk",
666 .clkctrl_offs
= OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET
,
667 .context_offs
= OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET
,
668 .modulemode
= MODULEMODE_SWCTRL
,
671 .dev_attr
= &i2c_dev_attr
,
675 static struct omap_hwmod omap54xx_i2c4_hwmod
= {
677 .class = &omap54xx_i2c_hwmod_class
,
678 .clkdm_name
= "l4per_clkdm",
679 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
680 .main_clk
= "func_96m_fclk",
683 .clkctrl_offs
= OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET
,
684 .context_offs
= OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET
,
685 .modulemode
= MODULEMODE_SWCTRL
,
688 .dev_attr
= &i2c_dev_attr
,
692 static struct omap_hwmod omap54xx_i2c5_hwmod
= {
694 .class = &omap54xx_i2c_hwmod_class
,
695 .clkdm_name
= "l4per_clkdm",
696 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
697 .main_clk
= "func_96m_fclk",
700 .clkctrl_offs
= OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET
,
701 .context_offs
= OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET
,
702 .modulemode
= MODULEMODE_SWCTRL
,
705 .dev_attr
= &i2c_dev_attr
,
710 * keyboard controller
713 static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc
= {
716 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_SIDLEMODE
|
718 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
719 .sysc_fields
= &omap_hwmod_sysc_type1
,
722 static struct omap_hwmod_class omap54xx_kbd_hwmod_class
= {
724 .sysc
= &omap54xx_kbd_sysc
,
728 static struct omap_hwmod omap54xx_kbd_hwmod
= {
730 .class = &omap54xx_kbd_hwmod_class
,
731 .clkdm_name
= "wkupaon_clkdm",
732 .main_clk
= "sys_32k_ck",
735 .clkctrl_offs
= OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET
,
736 .context_offs
= OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET
,
737 .modulemode
= MODULEMODE_SWCTRL
,
744 * mailbox module allowing communication between the on-chip processors using a
745 * queued mailbox-interrupt mechanism.
748 static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc
= {
751 .sysc_flags
= (SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
753 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
754 .sysc_fields
= &omap_hwmod_sysc_type2
,
757 static struct omap_hwmod_class omap54xx_mailbox_hwmod_class
= {
759 .sysc
= &omap54xx_mailbox_sysc
,
763 static struct omap_hwmod omap54xx_mailbox_hwmod
= {
765 .class = &omap54xx_mailbox_hwmod_class
,
766 .clkdm_name
= "l4cfg_clkdm",
769 .clkctrl_offs
= OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET
,
770 .context_offs
= OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET
,
777 * multi channel buffered serial port controller
780 static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc
= {
782 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_ENAWAKEUP
|
783 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
784 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
785 .sysc_fields
= &omap_hwmod_sysc_type1
,
788 static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class
= {
790 .sysc
= &omap54xx_mcbsp_sysc
,
791 .rev
= MCBSP_CONFIG_TYPE4
,
795 static struct omap_hwmod_opt_clk mcbsp1_opt_clks
[] = {
796 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
797 { .role
= "prcm_fck", .clk
= "mcbsp1_sync_mux_ck" },
800 static struct omap_hwmod omap54xx_mcbsp1_hwmod
= {
802 .class = &omap54xx_mcbsp_hwmod_class
,
803 .clkdm_name
= "abe_clkdm",
804 .main_clk
= "mcbsp1_gfclk",
807 .clkctrl_offs
= OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET
,
808 .context_offs
= OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET
,
809 .modulemode
= MODULEMODE_SWCTRL
,
812 .opt_clks
= mcbsp1_opt_clks
,
813 .opt_clks_cnt
= ARRAY_SIZE(mcbsp1_opt_clks
),
817 static struct omap_hwmod_opt_clk mcbsp2_opt_clks
[] = {
818 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
819 { .role
= "prcm_fck", .clk
= "mcbsp2_sync_mux_ck" },
822 static struct omap_hwmod omap54xx_mcbsp2_hwmod
= {
824 .class = &omap54xx_mcbsp_hwmod_class
,
825 .clkdm_name
= "abe_clkdm",
826 .main_clk
= "mcbsp2_gfclk",
829 .clkctrl_offs
= OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET
,
830 .context_offs
= OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET
,
831 .modulemode
= MODULEMODE_SWCTRL
,
834 .opt_clks
= mcbsp2_opt_clks
,
835 .opt_clks_cnt
= ARRAY_SIZE(mcbsp2_opt_clks
),
839 static struct omap_hwmod_opt_clk mcbsp3_opt_clks
[] = {
840 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
841 { .role
= "prcm_fck", .clk
= "mcbsp3_sync_mux_ck" },
844 static struct omap_hwmod omap54xx_mcbsp3_hwmod
= {
846 .class = &omap54xx_mcbsp_hwmod_class
,
847 .clkdm_name
= "abe_clkdm",
848 .main_clk
= "mcbsp3_gfclk",
851 .clkctrl_offs
= OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET
,
852 .context_offs
= OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET
,
853 .modulemode
= MODULEMODE_SWCTRL
,
856 .opt_clks
= mcbsp3_opt_clks
,
857 .opt_clks_cnt
= ARRAY_SIZE(mcbsp3_opt_clks
),
862 * multi channel pdm controller (proprietary interface with phoenix power
866 static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc
= {
869 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
870 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
871 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
873 .sysc_fields
= &omap_hwmod_sysc_type2
,
876 static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class
= {
878 .sysc
= &omap54xx_mcpdm_sysc
,
882 static struct omap_hwmod omap54xx_mcpdm_hwmod
= {
884 .class = &omap54xx_mcpdm_hwmod_class
,
885 .clkdm_name
= "abe_clkdm",
887 * It's suspected that the McPDM requires an off-chip main
888 * functional clock, controlled via I2C. This IP block is
889 * currently reset very early during boot, before I2C is
890 * available, so it doesn't seem that we have any choice in
891 * the kernel other than to avoid resetting it. XXX This is
892 * really a hardware issue workaround: every IP block should
893 * be able to source its main functional clock from either
894 * on-chip or off-chip sources. McPDM seems to be the only
898 .flags
= HWMOD_EXT_OPT_MAIN_CLK
,
899 .main_clk
= "pad_clks_ck",
902 .clkctrl_offs
= OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET
,
903 .context_offs
= OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET
,
904 .modulemode
= MODULEMODE_SWCTRL
,
911 * multichannel serial port interface (mcspi) / master/slave synchronous serial
915 static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc
= {
918 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
919 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
920 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
922 .sysc_fields
= &omap_hwmod_sysc_type2
,
925 static struct omap_hwmod_class omap54xx_mcspi_hwmod_class
= {
927 .sysc
= &omap54xx_mcspi_sysc
,
928 .rev
= OMAP4_MCSPI_REV
,
932 /* mcspi1 dev_attr */
933 static struct omap2_mcspi_dev_attr mcspi1_dev_attr
= {
937 static struct omap_hwmod omap54xx_mcspi1_hwmod
= {
939 .class = &omap54xx_mcspi_hwmod_class
,
940 .clkdm_name
= "l4per_clkdm",
941 .main_clk
= "func_48m_fclk",
944 .clkctrl_offs
= OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET
,
945 .context_offs
= OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET
,
946 .modulemode
= MODULEMODE_SWCTRL
,
949 .dev_attr
= &mcspi1_dev_attr
,
953 /* mcspi2 dev_attr */
954 static struct omap2_mcspi_dev_attr mcspi2_dev_attr
= {
958 static struct omap_hwmod omap54xx_mcspi2_hwmod
= {
960 .class = &omap54xx_mcspi_hwmod_class
,
961 .clkdm_name
= "l4per_clkdm",
962 .main_clk
= "func_48m_fclk",
965 .clkctrl_offs
= OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET
,
966 .context_offs
= OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET
,
967 .modulemode
= MODULEMODE_SWCTRL
,
970 .dev_attr
= &mcspi2_dev_attr
,
974 /* mcspi3 dev_attr */
975 static struct omap2_mcspi_dev_attr mcspi3_dev_attr
= {
979 static struct omap_hwmod omap54xx_mcspi3_hwmod
= {
981 .class = &omap54xx_mcspi_hwmod_class
,
982 .clkdm_name
= "l4per_clkdm",
983 .main_clk
= "func_48m_fclk",
986 .clkctrl_offs
= OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET
,
987 .context_offs
= OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET
,
988 .modulemode
= MODULEMODE_SWCTRL
,
991 .dev_attr
= &mcspi3_dev_attr
,
995 /* mcspi4 dev_attr */
996 static struct omap2_mcspi_dev_attr mcspi4_dev_attr
= {
1000 static struct omap_hwmod omap54xx_mcspi4_hwmod
= {
1002 .class = &omap54xx_mcspi_hwmod_class
,
1003 .clkdm_name
= "l4per_clkdm",
1004 .main_clk
= "func_48m_fclk",
1007 .clkctrl_offs
= OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET
,
1008 .context_offs
= OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET
,
1009 .modulemode
= MODULEMODE_SWCTRL
,
1012 .dev_attr
= &mcspi4_dev_attr
,
1017 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1020 static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc
= {
1022 .sysc_offs
= 0x0010,
1023 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
1024 SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
1025 SYSC_HAS_SOFTRESET
),
1026 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1027 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1028 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1029 .sysc_fields
= &omap_hwmod_sysc_type2
,
1032 static struct omap_hwmod_class omap54xx_mmc_hwmod_class
= {
1034 .sysc
= &omap54xx_mmc_sysc
,
1038 static struct omap_hwmod_opt_clk mmc1_opt_clks
[] = {
1039 { .role
= "32khz_clk", .clk
= "mmc1_32khz_clk" },
1043 static struct omap_mmc_dev_attr mmc1_dev_attr
= {
1044 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
1047 static struct omap_hwmod omap54xx_mmc1_hwmod
= {
1049 .class = &omap54xx_mmc_hwmod_class
,
1050 .clkdm_name
= "l3init_clkdm",
1051 .main_clk
= "mmc1_fclk",
1054 .clkctrl_offs
= OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET
,
1055 .context_offs
= OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET
,
1056 .modulemode
= MODULEMODE_SWCTRL
,
1059 .opt_clks
= mmc1_opt_clks
,
1060 .opt_clks_cnt
= ARRAY_SIZE(mmc1_opt_clks
),
1061 .dev_attr
= &mmc1_dev_attr
,
1065 static struct omap_hwmod omap54xx_mmc2_hwmod
= {
1067 .class = &omap54xx_mmc_hwmod_class
,
1068 .clkdm_name
= "l3init_clkdm",
1069 .main_clk
= "mmc2_fclk",
1072 .clkctrl_offs
= OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET
,
1073 .context_offs
= OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET
,
1074 .modulemode
= MODULEMODE_SWCTRL
,
1080 static struct omap_hwmod omap54xx_mmc3_hwmod
= {
1082 .class = &omap54xx_mmc_hwmod_class
,
1083 .clkdm_name
= "l4per_clkdm",
1084 .main_clk
= "func_48m_fclk",
1087 .clkctrl_offs
= OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET
,
1088 .context_offs
= OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET
,
1089 .modulemode
= MODULEMODE_SWCTRL
,
1095 static struct omap_hwmod omap54xx_mmc4_hwmod
= {
1097 .class = &omap54xx_mmc_hwmod_class
,
1098 .clkdm_name
= "l4per_clkdm",
1099 .main_clk
= "func_48m_fclk",
1102 .clkctrl_offs
= OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET
,
1103 .context_offs
= OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET
,
1104 .modulemode
= MODULEMODE_SWCTRL
,
1110 static struct omap_hwmod omap54xx_mmc5_hwmod
= {
1112 .class = &omap54xx_mmc_hwmod_class
,
1113 .clkdm_name
= "l4per_clkdm",
1114 .main_clk
= "func_96m_fclk",
1117 .clkctrl_offs
= OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET
,
1118 .context_offs
= OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET
,
1119 .modulemode
= MODULEMODE_SWCTRL
,
1129 static struct omap_hwmod_class omap54xx_mpu_hwmod_class
= {
1134 static struct omap_hwmod omap54xx_mpu_hwmod
= {
1136 .class = &omap54xx_mpu_hwmod_class
,
1137 .clkdm_name
= "mpu_clkdm",
1138 .flags
= HWMOD_INIT_NO_IDLE
,
1139 .main_clk
= "dpll_mpu_m2_ck",
1142 .clkctrl_offs
= OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET
,
1143 .context_offs
= OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET
,
1150 * spinlock provides hardware assistance for synchronizing the processes
1151 * running on multiple processors
1154 static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc
= {
1156 .sysc_offs
= 0x0010,
1157 .syss_offs
= 0x0014,
1158 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
1159 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
1160 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1161 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1162 .sysc_fields
= &omap_hwmod_sysc_type1
,
1165 static struct omap_hwmod_class omap54xx_spinlock_hwmod_class
= {
1167 .sysc
= &omap54xx_spinlock_sysc
,
1171 static struct omap_hwmod omap54xx_spinlock_hwmod
= {
1173 .class = &omap54xx_spinlock_hwmod_class
,
1174 .clkdm_name
= "l4cfg_clkdm",
1177 .clkctrl_offs
= OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET
,
1178 .context_offs
= OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET
,
1185 * bridge to transform ocp interface protocol to scp (serial control port)
1189 static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc
= {
1191 .sysc_offs
= 0x0010,
1192 .syss_offs
= 0x0014,
1193 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_SIDLEMODE
|
1194 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1195 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1196 .sysc_fields
= &omap_hwmod_sysc_type1
,
1199 static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class
= {
1201 .sysc
= &omap54xx_ocp2scp_sysc
,
1205 static struct omap_hwmod omap54xx_ocp2scp1_hwmod
= {
1207 .class = &omap54xx_ocp2scp_hwmod_class
,
1208 .clkdm_name
= "l3init_clkdm",
1209 .main_clk
= "l4_root_clk_div",
1212 .clkctrl_offs
= OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET
,
1213 .context_offs
= OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET
,
1214 .modulemode
= MODULEMODE_HWCTRL
,
1221 * general purpose timer module with accurate 1ms tick
1222 * This class contains several variants: ['timer_1ms', 'timer']
1225 static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc
= {
1227 .sysc_offs
= 0x0010,
1228 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
1229 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1230 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1232 .sysc_fields
= &omap_hwmod_sysc_type2
,
1233 .clockact
= CLOCKACT_TEST_ICLK
,
1236 static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class
= {
1238 .sysc
= &omap54xx_timer_1ms_sysc
,
1241 static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc
= {
1243 .sysc_offs
= 0x0010,
1244 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
1245 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1246 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1248 .sysc_fields
= &omap_hwmod_sysc_type2
,
1251 static struct omap_hwmod_class omap54xx_timer_hwmod_class
= {
1253 .sysc
= &omap54xx_timer_sysc
,
1257 static struct omap_hwmod omap54xx_timer1_hwmod
= {
1259 .class = &omap54xx_timer_1ms_hwmod_class
,
1260 .clkdm_name
= "wkupaon_clkdm",
1261 .main_clk
= "timer1_gfclk_mux",
1262 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
1265 .clkctrl_offs
= OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET
,
1266 .context_offs
= OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET
,
1267 .modulemode
= MODULEMODE_SWCTRL
,
1273 static struct omap_hwmod omap54xx_timer2_hwmod
= {
1275 .class = &omap54xx_timer_1ms_hwmod_class
,
1276 .clkdm_name
= "l4per_clkdm",
1277 .main_clk
= "timer2_gfclk_mux",
1278 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
1281 .clkctrl_offs
= OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET
,
1282 .context_offs
= OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET
,
1283 .modulemode
= MODULEMODE_SWCTRL
,
1289 static struct omap_hwmod omap54xx_timer3_hwmod
= {
1291 .class = &omap54xx_timer_hwmod_class
,
1292 .clkdm_name
= "l4per_clkdm",
1293 .main_clk
= "timer3_gfclk_mux",
1296 .clkctrl_offs
= OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET
,
1297 .context_offs
= OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET
,
1298 .modulemode
= MODULEMODE_SWCTRL
,
1304 static struct omap_hwmod omap54xx_timer4_hwmod
= {
1306 .class = &omap54xx_timer_hwmod_class
,
1307 .clkdm_name
= "l4per_clkdm",
1308 .main_clk
= "timer4_gfclk_mux",
1311 .clkctrl_offs
= OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET
,
1312 .context_offs
= OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET
,
1313 .modulemode
= MODULEMODE_SWCTRL
,
1319 static struct omap_hwmod omap54xx_timer5_hwmod
= {
1321 .class = &omap54xx_timer_hwmod_class
,
1322 .clkdm_name
= "abe_clkdm",
1323 .main_clk
= "timer5_gfclk_mux",
1326 .clkctrl_offs
= OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET
,
1327 .context_offs
= OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET
,
1328 .modulemode
= MODULEMODE_SWCTRL
,
1334 static struct omap_hwmod omap54xx_timer6_hwmod
= {
1336 .class = &omap54xx_timer_hwmod_class
,
1337 .clkdm_name
= "abe_clkdm",
1338 .main_clk
= "timer6_gfclk_mux",
1341 .clkctrl_offs
= OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET
,
1342 .context_offs
= OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET
,
1343 .modulemode
= MODULEMODE_SWCTRL
,
1349 static struct omap_hwmod omap54xx_timer7_hwmod
= {
1351 .class = &omap54xx_timer_hwmod_class
,
1352 .clkdm_name
= "abe_clkdm",
1353 .main_clk
= "timer7_gfclk_mux",
1356 .clkctrl_offs
= OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET
,
1357 .context_offs
= OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET
,
1358 .modulemode
= MODULEMODE_SWCTRL
,
1364 static struct omap_hwmod omap54xx_timer8_hwmod
= {
1366 .class = &omap54xx_timer_hwmod_class
,
1367 .clkdm_name
= "abe_clkdm",
1368 .main_clk
= "timer8_gfclk_mux",
1371 .clkctrl_offs
= OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET
,
1372 .context_offs
= OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET
,
1373 .modulemode
= MODULEMODE_SWCTRL
,
1379 static struct omap_hwmod omap54xx_timer9_hwmod
= {
1381 .class = &omap54xx_timer_hwmod_class
,
1382 .clkdm_name
= "l4per_clkdm",
1383 .main_clk
= "timer9_gfclk_mux",
1386 .clkctrl_offs
= OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET
,
1387 .context_offs
= OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET
,
1388 .modulemode
= MODULEMODE_SWCTRL
,
1394 static struct omap_hwmod omap54xx_timer10_hwmod
= {
1396 .class = &omap54xx_timer_1ms_hwmod_class
,
1397 .clkdm_name
= "l4per_clkdm",
1398 .main_clk
= "timer10_gfclk_mux",
1399 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
1402 .clkctrl_offs
= OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET
,
1403 .context_offs
= OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET
,
1404 .modulemode
= MODULEMODE_SWCTRL
,
1410 static struct omap_hwmod omap54xx_timer11_hwmod
= {
1412 .class = &omap54xx_timer_hwmod_class
,
1413 .clkdm_name
= "l4per_clkdm",
1414 .main_clk
= "timer11_gfclk_mux",
1417 .clkctrl_offs
= OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET
,
1418 .context_offs
= OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET
,
1419 .modulemode
= MODULEMODE_SWCTRL
,
1426 * universal asynchronous receiver/transmitter (uart)
1429 static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc
= {
1431 .sysc_offs
= 0x0054,
1432 .syss_offs
= 0x0058,
1433 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
1434 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1435 SYSS_HAS_RESET_STATUS
),
1436 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1438 .sysc_fields
= &omap_hwmod_sysc_type1
,
1441 static struct omap_hwmod_class omap54xx_uart_hwmod_class
= {
1443 .sysc
= &omap54xx_uart_sysc
,
1447 static struct omap_hwmod omap54xx_uart1_hwmod
= {
1449 .class = &omap54xx_uart_hwmod_class
,
1450 .clkdm_name
= "l4per_clkdm",
1451 .main_clk
= "func_48m_fclk",
1454 .clkctrl_offs
= OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET
,
1455 .context_offs
= OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET
,
1456 .modulemode
= MODULEMODE_SWCTRL
,
1462 static struct omap_hwmod omap54xx_uart2_hwmod
= {
1464 .class = &omap54xx_uart_hwmod_class
,
1465 .clkdm_name
= "l4per_clkdm",
1466 .main_clk
= "func_48m_fclk",
1469 .clkctrl_offs
= OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET
,
1470 .context_offs
= OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET
,
1471 .modulemode
= MODULEMODE_SWCTRL
,
1477 static struct omap_hwmod omap54xx_uart3_hwmod
= {
1479 .class = &omap54xx_uart_hwmod_class
,
1480 .clkdm_name
= "l4per_clkdm",
1481 .flags
= DEBUG_OMAP4UART3_FLAGS
,
1482 .main_clk
= "func_48m_fclk",
1485 .clkctrl_offs
= OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET
,
1486 .context_offs
= OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET
,
1487 .modulemode
= MODULEMODE_SWCTRL
,
1493 static struct omap_hwmod omap54xx_uart4_hwmod
= {
1495 .class = &omap54xx_uart_hwmod_class
,
1496 .clkdm_name
= "l4per_clkdm",
1497 .flags
= DEBUG_OMAP4UART4_FLAGS
,
1498 .main_clk
= "func_48m_fclk",
1501 .clkctrl_offs
= OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET
,
1502 .context_offs
= OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET
,
1503 .modulemode
= MODULEMODE_SWCTRL
,
1509 static struct omap_hwmod omap54xx_uart5_hwmod
= {
1511 .class = &omap54xx_uart_hwmod_class
,
1512 .clkdm_name
= "l4per_clkdm",
1513 .main_clk
= "func_48m_fclk",
1516 .clkctrl_offs
= OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET
,
1517 .context_offs
= OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET
,
1518 .modulemode
= MODULEMODE_SWCTRL
,
1524 static struct omap_hwmod omap54xx_uart6_hwmod
= {
1526 .class = &omap54xx_uart_hwmod_class
,
1527 .clkdm_name
= "l4per_clkdm",
1528 .main_clk
= "func_48m_fclk",
1531 .clkctrl_offs
= OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET
,
1532 .context_offs
= OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET
,
1533 .modulemode
= MODULEMODE_SWCTRL
,
1539 * 'usb_host_hs' class
1540 * high-speed multi-port usb host controller
1543 static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc
= {
1545 .sysc_offs
= 0x0010,
1546 .sysc_flags
= (SYSC_HAS_MIDLEMODE
| SYSC_HAS_RESET_STATUS
|
1547 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1548 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1549 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1550 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1551 .sysc_fields
= &omap_hwmod_sysc_type2
,
1554 static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class
= {
1555 .name
= "usb_host_hs",
1556 .sysc
= &omap54xx_usb_host_hs_sysc
,
1559 static struct omap_hwmod omap54xx_usb_host_hs_hwmod
= {
1560 .name
= "usb_host_hs",
1561 .class = &omap54xx_usb_host_hs_hwmod_class
,
1562 .clkdm_name
= "l3init_clkdm",
1564 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1568 * In the following configuration :
1569 * - USBHOST module is set to smart-idle mode
1570 * - PRCM asserts idle_req to the USBHOST module ( This typically
1571 * happens when the system is going to a low power mode : all ports
1572 * have been suspended, the master part of the USBHOST module has
1573 * entered the standby state, and SW has cut the functional clocks)
1574 * - an USBHOST interrupt occurs before the module is able to answer
1575 * idle_ack, typically a remote wakeup IRQ.
1576 * Then the USB HOST module will enter a deadlock situation where it
1577 * is no more accessible nor functional.
1580 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1584 * Errata: USB host EHCI may stall when entering smart-standby mode
1588 * When the USBHOST module is set to smart-standby mode, and when it is
1589 * ready to enter the standby state (i.e. all ports are suspended and
1590 * all attached devices are in suspend mode), then it can wrongly assert
1591 * the Mstandby signal too early while there are still some residual OCP
1592 * transactions ongoing. If this condition occurs, the internal state
1593 * machine may go to an undefined state and the USB link may be stuck
1594 * upon the next resume.
1597 * Don't use smart standby; use only force standby,
1598 * hence HWMOD_SWSUP_MSTANDBY
1602 * During system boot; If the hwmod framework resets the module
1603 * the module will have smart idle settings; which can lead to deadlock
1604 * (above Errata Id:i660); so, dont reset the module during boot;
1605 * Use HWMOD_INIT_NO_RESET.
1608 .flags
= HWMOD_SWSUP_SIDLE
| HWMOD_SWSUP_MSTANDBY
|
1609 HWMOD_INIT_NO_RESET
,
1610 .main_clk
= "l3init_60m_fclk",
1613 .clkctrl_offs
= OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET
,
1614 .context_offs
= OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET
,
1615 .modulemode
= MODULEMODE_SWCTRL
,
1621 * 'usb_tll_hs' class
1622 * usb_tll_hs module is the adapter on the usb_host_hs ports
1625 static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc
= {
1627 .sysc_offs
= 0x0010,
1628 .syss_offs
= 0x0014,
1629 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
1630 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
1631 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1632 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
1633 .sysc_fields
= &omap_hwmod_sysc_type1
,
1636 static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class
= {
1637 .name
= "usb_tll_hs",
1638 .sysc
= &omap54xx_usb_tll_hs_sysc
,
1641 static struct omap_hwmod omap54xx_usb_tll_hs_hwmod
= {
1642 .name
= "usb_tll_hs",
1643 .class = &omap54xx_usb_tll_hs_hwmod_class
,
1644 .clkdm_name
= "l3init_clkdm",
1645 .main_clk
= "l4_root_clk_div",
1648 .clkctrl_offs
= OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET
,
1649 .context_offs
= OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET
,
1650 .modulemode
= MODULEMODE_HWCTRL
,
1656 * 'usb_otg_ss' class
1657 * 2.0 super speed (usb_otg_ss) controller
1660 static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc
= {
1662 .sysc_offs
= 0x0010,
1663 .sysc_flags
= (SYSC_HAS_DMADISABLE
| SYSC_HAS_MIDLEMODE
|
1664 SYSC_HAS_SIDLEMODE
),
1665 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1666 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1667 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1668 .sysc_fields
= &omap_hwmod_sysc_type2
,
1671 static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class
= {
1672 .name
= "usb_otg_ss",
1673 .sysc
= &omap54xx_usb_otg_ss_sysc
,
1677 static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks
[] = {
1678 { .role
= "refclk960m", .clk
= "usb_otg_ss_refclk960m" },
1681 static struct omap_hwmod omap54xx_usb_otg_ss_hwmod
= {
1682 .name
= "usb_otg_ss",
1683 .class = &omap54xx_usb_otg_ss_hwmod_class
,
1684 .clkdm_name
= "l3init_clkdm",
1685 .flags
= HWMOD_SWSUP_SIDLE
,
1686 .main_clk
= "dpll_core_h13x2_ck",
1689 .clkctrl_offs
= OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET
,
1690 .context_offs
= OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET
,
1691 .modulemode
= MODULEMODE_HWCTRL
,
1694 .opt_clks
= usb_otg_ss_opt_clks
,
1695 .opt_clks_cnt
= ARRAY_SIZE(usb_otg_ss_opt_clks
),
1700 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1701 * overflow condition
1704 static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc
= {
1706 .sysc_offs
= 0x0010,
1707 .syss_offs
= 0x0014,
1708 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_SIDLEMODE
|
1709 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1710 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1712 .sysc_fields
= &omap_hwmod_sysc_type1
,
1715 static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class
= {
1717 .sysc
= &omap54xx_wd_timer_sysc
,
1718 .pre_shutdown
= &omap2_wd_timer_disable
,
1722 static struct omap_hwmod omap54xx_wd_timer2_hwmod
= {
1723 .name
= "wd_timer2",
1724 .class = &omap54xx_wd_timer_hwmod_class
,
1725 .clkdm_name
= "wkupaon_clkdm",
1726 .main_clk
= "sys_32k_ck",
1729 .clkctrl_offs
= OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET
,
1730 .context_offs
= OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET
,
1731 .modulemode
= MODULEMODE_SWCTRL
,
1741 /* l3_main_1 -> dmm */
1742 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm
= {
1743 .master
= &omap54xx_l3_main_1_hwmod
,
1744 .slave
= &omap54xx_dmm_hwmod
,
1745 .clk
= "l3_iclk_div",
1746 .user
= OCP_USER_SDMA
,
1749 /* l3_main_3 -> l3_instr */
1750 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr
= {
1751 .master
= &omap54xx_l3_main_3_hwmod
,
1752 .slave
= &omap54xx_l3_instr_hwmod
,
1753 .clk
= "l3_iclk_div",
1754 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1757 /* l3_main_2 -> l3_main_1 */
1758 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1
= {
1759 .master
= &omap54xx_l3_main_2_hwmod
,
1760 .slave
= &omap54xx_l3_main_1_hwmod
,
1761 .clk
= "l3_iclk_div",
1762 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1765 /* l4_cfg -> l3_main_1 */
1766 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1
= {
1767 .master
= &omap54xx_l4_cfg_hwmod
,
1768 .slave
= &omap54xx_l3_main_1_hwmod
,
1769 .clk
= "l3_iclk_div",
1770 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1773 /* mpu -> l3_main_1 */
1774 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1
= {
1775 .master
= &omap54xx_mpu_hwmod
,
1776 .slave
= &omap54xx_l3_main_1_hwmod
,
1777 .clk
= "l3_iclk_div",
1778 .user
= OCP_USER_MPU
,
1781 /* l3_main_1 -> l3_main_2 */
1782 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2
= {
1783 .master
= &omap54xx_l3_main_1_hwmod
,
1784 .slave
= &omap54xx_l3_main_2_hwmod
,
1785 .clk
= "l3_iclk_div",
1786 .user
= OCP_USER_MPU
,
1789 /* l4_cfg -> l3_main_2 */
1790 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2
= {
1791 .master
= &omap54xx_l4_cfg_hwmod
,
1792 .slave
= &omap54xx_l3_main_2_hwmod
,
1793 .clk
= "l3_iclk_div",
1794 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1797 /* l3_main_1 -> l3_main_3 */
1798 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3
= {
1799 .master
= &omap54xx_l3_main_1_hwmod
,
1800 .slave
= &omap54xx_l3_main_3_hwmod
,
1801 .clk
= "l3_iclk_div",
1802 .user
= OCP_USER_MPU
,
1805 /* l3_main_2 -> l3_main_3 */
1806 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3
= {
1807 .master
= &omap54xx_l3_main_2_hwmod
,
1808 .slave
= &omap54xx_l3_main_3_hwmod
,
1809 .clk
= "l3_iclk_div",
1810 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1813 /* l4_cfg -> l3_main_3 */
1814 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3
= {
1815 .master
= &omap54xx_l4_cfg_hwmod
,
1816 .slave
= &omap54xx_l3_main_3_hwmod
,
1817 .clk
= "l3_iclk_div",
1818 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1821 /* l3_main_1 -> l4_abe */
1822 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe
= {
1823 .master
= &omap54xx_l3_main_1_hwmod
,
1824 .slave
= &omap54xx_l4_abe_hwmod
,
1826 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1830 static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe
= {
1831 .master
= &omap54xx_mpu_hwmod
,
1832 .slave
= &omap54xx_l4_abe_hwmod
,
1834 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1837 /* l3_main_1 -> l4_cfg */
1838 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg
= {
1839 .master
= &omap54xx_l3_main_1_hwmod
,
1840 .slave
= &omap54xx_l4_cfg_hwmod
,
1841 .clk
= "l4_root_clk_div",
1842 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1845 /* l3_main_2 -> l4_per */
1846 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per
= {
1847 .master
= &omap54xx_l3_main_2_hwmod
,
1848 .slave
= &omap54xx_l4_per_hwmod
,
1849 .clk
= "l4_root_clk_div",
1850 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1853 /* l3_main_1 -> l4_wkup */
1854 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup
= {
1855 .master
= &omap54xx_l3_main_1_hwmod
,
1856 .slave
= &omap54xx_l4_wkup_hwmod
,
1857 .clk
= "wkupaon_iclk_mux",
1858 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1861 /* mpu -> mpu_private */
1862 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private
= {
1863 .master
= &omap54xx_mpu_hwmod
,
1864 .slave
= &omap54xx_mpu_private_hwmod
,
1865 .clk
= "l3_iclk_div",
1866 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1869 /* l4_wkup -> counter_32k */
1870 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k
= {
1871 .master
= &omap54xx_l4_wkup_hwmod
,
1872 .slave
= &omap54xx_counter_32k_hwmod
,
1873 .clk
= "wkupaon_iclk_mux",
1874 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1877 static struct omap_hwmod_addr_space omap54xx_dma_system_addrs
[] = {
1879 .pa_start
= 0x4a056000,
1880 .pa_end
= 0x4a056fff,
1881 .flags
= ADDR_TYPE_RT
1886 /* l4_cfg -> dma_system */
1887 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system
= {
1888 .master
= &omap54xx_l4_cfg_hwmod
,
1889 .slave
= &omap54xx_dma_system_hwmod
,
1890 .clk
= "l4_root_clk_div",
1891 .addr
= omap54xx_dma_system_addrs
,
1892 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1895 /* l4_abe -> dmic */
1896 static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic
= {
1897 .master
= &omap54xx_l4_abe_hwmod
,
1898 .slave
= &omap54xx_dmic_hwmod
,
1900 .user
= OCP_USER_MPU
,
1904 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1
= {
1905 .master
= &omap54xx_mpu_hwmod
,
1906 .slave
= &omap54xx_emif1_hwmod
,
1907 .clk
= "dpll_core_h11x2_ck",
1908 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1912 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2
= {
1913 .master
= &omap54xx_mpu_hwmod
,
1914 .slave
= &omap54xx_emif2_hwmod
,
1915 .clk
= "dpll_core_h11x2_ck",
1916 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1919 /* l4_wkup -> gpio1 */
1920 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1
= {
1921 .master
= &omap54xx_l4_wkup_hwmod
,
1922 .slave
= &omap54xx_gpio1_hwmod
,
1923 .clk
= "wkupaon_iclk_mux",
1924 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1927 /* l4_per -> gpio2 */
1928 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2
= {
1929 .master
= &omap54xx_l4_per_hwmod
,
1930 .slave
= &omap54xx_gpio2_hwmod
,
1931 .clk
= "l4_root_clk_div",
1932 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1935 /* l4_per -> gpio3 */
1936 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3
= {
1937 .master
= &omap54xx_l4_per_hwmod
,
1938 .slave
= &omap54xx_gpio3_hwmod
,
1939 .clk
= "l4_root_clk_div",
1940 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1943 /* l4_per -> gpio4 */
1944 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4
= {
1945 .master
= &omap54xx_l4_per_hwmod
,
1946 .slave
= &omap54xx_gpio4_hwmod
,
1947 .clk
= "l4_root_clk_div",
1948 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1951 /* l4_per -> gpio5 */
1952 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5
= {
1953 .master
= &omap54xx_l4_per_hwmod
,
1954 .slave
= &omap54xx_gpio5_hwmod
,
1955 .clk
= "l4_root_clk_div",
1956 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1959 /* l4_per -> gpio6 */
1960 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6
= {
1961 .master
= &omap54xx_l4_per_hwmod
,
1962 .slave
= &omap54xx_gpio6_hwmod
,
1963 .clk
= "l4_root_clk_div",
1964 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1967 /* l4_per -> gpio7 */
1968 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7
= {
1969 .master
= &omap54xx_l4_per_hwmod
,
1970 .slave
= &omap54xx_gpio7_hwmod
,
1971 .clk
= "l4_root_clk_div",
1972 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1975 /* l4_per -> gpio8 */
1976 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8
= {
1977 .master
= &omap54xx_l4_per_hwmod
,
1978 .slave
= &omap54xx_gpio8_hwmod
,
1979 .clk
= "l4_root_clk_div",
1980 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1983 /* l4_per -> i2c1 */
1984 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1
= {
1985 .master
= &omap54xx_l4_per_hwmod
,
1986 .slave
= &omap54xx_i2c1_hwmod
,
1987 .clk
= "l4_root_clk_div",
1988 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1991 /* l4_per -> i2c2 */
1992 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2
= {
1993 .master
= &omap54xx_l4_per_hwmod
,
1994 .slave
= &omap54xx_i2c2_hwmod
,
1995 .clk
= "l4_root_clk_div",
1996 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1999 /* l4_per -> i2c3 */
2000 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3
= {
2001 .master
= &omap54xx_l4_per_hwmod
,
2002 .slave
= &omap54xx_i2c3_hwmod
,
2003 .clk
= "l4_root_clk_div",
2004 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2007 /* l4_per -> i2c4 */
2008 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4
= {
2009 .master
= &omap54xx_l4_per_hwmod
,
2010 .slave
= &omap54xx_i2c4_hwmod
,
2011 .clk
= "l4_root_clk_div",
2012 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2015 /* l4_per -> i2c5 */
2016 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5
= {
2017 .master
= &omap54xx_l4_per_hwmod
,
2018 .slave
= &omap54xx_i2c5_hwmod
,
2019 .clk
= "l4_root_clk_div",
2020 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2023 /* l4_wkup -> kbd */
2024 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd
= {
2025 .master
= &omap54xx_l4_wkup_hwmod
,
2026 .slave
= &omap54xx_kbd_hwmod
,
2027 .clk
= "wkupaon_iclk_mux",
2028 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2031 /* l4_cfg -> mailbox */
2032 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox
= {
2033 .master
= &omap54xx_l4_cfg_hwmod
,
2034 .slave
= &omap54xx_mailbox_hwmod
,
2035 .clk
= "l4_root_clk_div",
2036 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2039 /* l4_abe -> mcbsp1 */
2040 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1
= {
2041 .master
= &omap54xx_l4_abe_hwmod
,
2042 .slave
= &omap54xx_mcbsp1_hwmod
,
2044 .user
= OCP_USER_MPU
,
2047 /* l4_abe -> mcbsp2 */
2048 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2
= {
2049 .master
= &omap54xx_l4_abe_hwmod
,
2050 .slave
= &omap54xx_mcbsp2_hwmod
,
2052 .user
= OCP_USER_MPU
,
2055 /* l4_abe -> mcbsp3 */
2056 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3
= {
2057 .master
= &omap54xx_l4_abe_hwmod
,
2058 .slave
= &omap54xx_mcbsp3_hwmod
,
2060 .user
= OCP_USER_MPU
,
2063 /* l4_abe -> mcpdm */
2064 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm
= {
2065 .master
= &omap54xx_l4_abe_hwmod
,
2066 .slave
= &omap54xx_mcpdm_hwmod
,
2068 .user
= OCP_USER_MPU
,
2071 /* l4_per -> mcspi1 */
2072 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1
= {
2073 .master
= &omap54xx_l4_per_hwmod
,
2074 .slave
= &omap54xx_mcspi1_hwmod
,
2075 .clk
= "l4_root_clk_div",
2076 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2079 /* l4_per -> mcspi2 */
2080 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2
= {
2081 .master
= &omap54xx_l4_per_hwmod
,
2082 .slave
= &omap54xx_mcspi2_hwmod
,
2083 .clk
= "l4_root_clk_div",
2084 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2087 /* l4_per -> mcspi3 */
2088 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3
= {
2089 .master
= &omap54xx_l4_per_hwmod
,
2090 .slave
= &omap54xx_mcspi3_hwmod
,
2091 .clk
= "l4_root_clk_div",
2092 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2095 /* l4_per -> mcspi4 */
2096 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4
= {
2097 .master
= &omap54xx_l4_per_hwmod
,
2098 .slave
= &omap54xx_mcspi4_hwmod
,
2099 .clk
= "l4_root_clk_div",
2100 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2103 /* l4_per -> mmc1 */
2104 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1
= {
2105 .master
= &omap54xx_l4_per_hwmod
,
2106 .slave
= &omap54xx_mmc1_hwmod
,
2107 .clk
= "l3_iclk_div",
2108 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2111 /* l4_per -> mmc2 */
2112 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2
= {
2113 .master
= &omap54xx_l4_per_hwmod
,
2114 .slave
= &omap54xx_mmc2_hwmod
,
2115 .clk
= "l3_iclk_div",
2116 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2119 /* l4_per -> mmc3 */
2120 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3
= {
2121 .master
= &omap54xx_l4_per_hwmod
,
2122 .slave
= &omap54xx_mmc3_hwmod
,
2123 .clk
= "l4_root_clk_div",
2124 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2127 /* l4_per -> mmc4 */
2128 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4
= {
2129 .master
= &omap54xx_l4_per_hwmod
,
2130 .slave
= &omap54xx_mmc4_hwmod
,
2131 .clk
= "l4_root_clk_div",
2132 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2135 /* l4_per -> mmc5 */
2136 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5
= {
2137 .master
= &omap54xx_l4_per_hwmod
,
2138 .slave
= &omap54xx_mmc5_hwmod
,
2139 .clk
= "l4_root_clk_div",
2140 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2144 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu
= {
2145 .master
= &omap54xx_l4_cfg_hwmod
,
2146 .slave
= &omap54xx_mpu_hwmod
,
2147 .clk
= "l4_root_clk_div",
2148 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2151 /* l4_cfg -> spinlock */
2152 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock
= {
2153 .master
= &omap54xx_l4_cfg_hwmod
,
2154 .slave
= &omap54xx_spinlock_hwmod
,
2155 .clk
= "l4_root_clk_div",
2156 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2159 /* l4_cfg -> ocp2scp1 */
2160 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1
= {
2161 .master
= &omap54xx_l4_cfg_hwmod
,
2162 .slave
= &omap54xx_ocp2scp1_hwmod
,
2163 .clk
= "l4_root_clk_div",
2164 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2167 /* l4_wkup -> timer1 */
2168 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1
= {
2169 .master
= &omap54xx_l4_wkup_hwmod
,
2170 .slave
= &omap54xx_timer1_hwmod
,
2171 .clk
= "wkupaon_iclk_mux",
2172 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2175 /* l4_per -> timer2 */
2176 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2
= {
2177 .master
= &omap54xx_l4_per_hwmod
,
2178 .slave
= &omap54xx_timer2_hwmod
,
2179 .clk
= "l4_root_clk_div",
2180 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2183 /* l4_per -> timer3 */
2184 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3
= {
2185 .master
= &omap54xx_l4_per_hwmod
,
2186 .slave
= &omap54xx_timer3_hwmod
,
2187 .clk
= "l4_root_clk_div",
2188 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2191 /* l4_per -> timer4 */
2192 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4
= {
2193 .master
= &omap54xx_l4_per_hwmod
,
2194 .slave
= &omap54xx_timer4_hwmod
,
2195 .clk
= "l4_root_clk_div",
2196 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2199 /* l4_abe -> timer5 */
2200 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5
= {
2201 .master
= &omap54xx_l4_abe_hwmod
,
2202 .slave
= &omap54xx_timer5_hwmod
,
2204 .user
= OCP_USER_MPU
,
2207 /* l4_abe -> timer6 */
2208 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6
= {
2209 .master
= &omap54xx_l4_abe_hwmod
,
2210 .slave
= &omap54xx_timer6_hwmod
,
2212 .user
= OCP_USER_MPU
,
2215 /* l4_abe -> timer7 */
2216 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7
= {
2217 .master
= &omap54xx_l4_abe_hwmod
,
2218 .slave
= &omap54xx_timer7_hwmod
,
2220 .user
= OCP_USER_MPU
,
2223 /* l4_abe -> timer8 */
2224 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8
= {
2225 .master
= &omap54xx_l4_abe_hwmod
,
2226 .slave
= &omap54xx_timer8_hwmod
,
2228 .user
= OCP_USER_MPU
,
2231 /* l4_per -> timer9 */
2232 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9
= {
2233 .master
= &omap54xx_l4_per_hwmod
,
2234 .slave
= &omap54xx_timer9_hwmod
,
2235 .clk
= "l4_root_clk_div",
2236 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2239 /* l4_per -> timer10 */
2240 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10
= {
2241 .master
= &omap54xx_l4_per_hwmod
,
2242 .slave
= &omap54xx_timer10_hwmod
,
2243 .clk
= "l4_root_clk_div",
2244 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2247 /* l4_per -> timer11 */
2248 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11
= {
2249 .master
= &omap54xx_l4_per_hwmod
,
2250 .slave
= &omap54xx_timer11_hwmod
,
2251 .clk
= "l4_root_clk_div",
2252 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2255 /* l4_per -> uart1 */
2256 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1
= {
2257 .master
= &omap54xx_l4_per_hwmod
,
2258 .slave
= &omap54xx_uart1_hwmod
,
2259 .clk
= "l4_root_clk_div",
2260 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2263 /* l4_per -> uart2 */
2264 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2
= {
2265 .master
= &omap54xx_l4_per_hwmod
,
2266 .slave
= &omap54xx_uart2_hwmod
,
2267 .clk
= "l4_root_clk_div",
2268 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2271 /* l4_per -> uart3 */
2272 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3
= {
2273 .master
= &omap54xx_l4_per_hwmod
,
2274 .slave
= &omap54xx_uart3_hwmod
,
2275 .clk
= "l4_root_clk_div",
2276 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2279 /* l4_per -> uart4 */
2280 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4
= {
2281 .master
= &omap54xx_l4_per_hwmod
,
2282 .slave
= &omap54xx_uart4_hwmod
,
2283 .clk
= "l4_root_clk_div",
2284 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2287 /* l4_per -> uart5 */
2288 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5
= {
2289 .master
= &omap54xx_l4_per_hwmod
,
2290 .slave
= &omap54xx_uart5_hwmod
,
2291 .clk
= "l4_root_clk_div",
2292 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2295 /* l4_per -> uart6 */
2296 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6
= {
2297 .master
= &omap54xx_l4_per_hwmod
,
2298 .slave
= &omap54xx_uart6_hwmod
,
2299 .clk
= "l4_root_clk_div",
2300 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2303 /* l4_cfg -> usb_host_hs */
2304 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs
= {
2305 .master
= &omap54xx_l4_cfg_hwmod
,
2306 .slave
= &omap54xx_usb_host_hs_hwmod
,
2307 .clk
= "l3_iclk_div",
2308 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2311 /* l4_cfg -> usb_tll_hs */
2312 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs
= {
2313 .master
= &omap54xx_l4_cfg_hwmod
,
2314 .slave
= &omap54xx_usb_tll_hs_hwmod
,
2315 .clk
= "l4_root_clk_div",
2316 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2319 /* l4_cfg -> usb_otg_ss */
2320 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss
= {
2321 .master
= &omap54xx_l4_cfg_hwmod
,
2322 .slave
= &omap54xx_usb_otg_ss_hwmod
,
2323 .clk
= "dpll_core_h13x2_ck",
2324 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2327 /* l4_wkup -> wd_timer2 */
2328 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2
= {
2329 .master
= &omap54xx_l4_wkup_hwmod
,
2330 .slave
= &omap54xx_wd_timer2_hwmod
,
2331 .clk
= "wkupaon_iclk_mux",
2332 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2335 static struct omap_hwmod_ocp_if
*omap54xx_hwmod_ocp_ifs
[] __initdata
= {
2336 &omap54xx_l3_main_1__dmm
,
2337 &omap54xx_l3_main_3__l3_instr
,
2338 &omap54xx_l3_main_2__l3_main_1
,
2339 &omap54xx_l4_cfg__l3_main_1
,
2340 &omap54xx_mpu__l3_main_1
,
2341 &omap54xx_l3_main_1__l3_main_2
,
2342 &omap54xx_l4_cfg__l3_main_2
,
2343 &omap54xx_l3_main_1__l3_main_3
,
2344 &omap54xx_l3_main_2__l3_main_3
,
2345 &omap54xx_l4_cfg__l3_main_3
,
2346 &omap54xx_l3_main_1__l4_abe
,
2347 &omap54xx_mpu__l4_abe
,
2348 &omap54xx_l3_main_1__l4_cfg
,
2349 &omap54xx_l3_main_2__l4_per
,
2350 &omap54xx_l3_main_1__l4_wkup
,
2351 &omap54xx_mpu__mpu_private
,
2352 &omap54xx_l4_wkup__counter_32k
,
2353 &omap54xx_l4_cfg__dma_system
,
2354 &omap54xx_l4_abe__dmic
,
2355 &omap54xx_mpu__emif1
,
2356 &omap54xx_mpu__emif2
,
2357 &omap54xx_l4_wkup__gpio1
,
2358 &omap54xx_l4_per__gpio2
,
2359 &omap54xx_l4_per__gpio3
,
2360 &omap54xx_l4_per__gpio4
,
2361 &omap54xx_l4_per__gpio5
,
2362 &omap54xx_l4_per__gpio6
,
2363 &omap54xx_l4_per__gpio7
,
2364 &omap54xx_l4_per__gpio8
,
2365 &omap54xx_l4_per__i2c1
,
2366 &omap54xx_l4_per__i2c2
,
2367 &omap54xx_l4_per__i2c3
,
2368 &omap54xx_l4_per__i2c4
,
2369 &omap54xx_l4_per__i2c5
,
2370 &omap54xx_l4_wkup__kbd
,
2371 &omap54xx_l4_cfg__mailbox
,
2372 &omap54xx_l4_abe__mcbsp1
,
2373 &omap54xx_l4_abe__mcbsp2
,
2374 &omap54xx_l4_abe__mcbsp3
,
2375 &omap54xx_l4_abe__mcpdm
,
2376 &omap54xx_l4_per__mcspi1
,
2377 &omap54xx_l4_per__mcspi2
,
2378 &omap54xx_l4_per__mcspi3
,
2379 &omap54xx_l4_per__mcspi4
,
2380 &omap54xx_l4_per__mmc1
,
2381 &omap54xx_l4_per__mmc2
,
2382 &omap54xx_l4_per__mmc3
,
2383 &omap54xx_l4_per__mmc4
,
2384 &omap54xx_l4_per__mmc5
,
2385 &omap54xx_l4_cfg__mpu
,
2386 &omap54xx_l4_cfg__spinlock
,
2387 &omap54xx_l4_cfg__ocp2scp1
,
2388 &omap54xx_l4_wkup__timer1
,
2389 &omap54xx_l4_per__timer2
,
2390 &omap54xx_l4_per__timer3
,
2391 &omap54xx_l4_per__timer4
,
2392 &omap54xx_l4_abe__timer5
,
2393 &omap54xx_l4_abe__timer6
,
2394 &omap54xx_l4_abe__timer7
,
2395 &omap54xx_l4_abe__timer8
,
2396 &omap54xx_l4_per__timer9
,
2397 &omap54xx_l4_per__timer10
,
2398 &omap54xx_l4_per__timer11
,
2399 &omap54xx_l4_per__uart1
,
2400 &omap54xx_l4_per__uart2
,
2401 &omap54xx_l4_per__uart3
,
2402 &omap54xx_l4_per__uart4
,
2403 &omap54xx_l4_per__uart5
,
2404 &omap54xx_l4_per__uart6
,
2405 &omap54xx_l4_cfg__usb_host_hs
,
2406 &omap54xx_l4_cfg__usb_tll_hs
,
2407 &omap54xx_l4_cfg__usb_otg_ss
,
2408 &omap54xx_l4_wkup__wd_timer2
,
2412 int __init
omap54xx_hwmod_init(void)
2415 return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs
);