2 * Hardware modules present on the OMAP54xx chips
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/i2c-omap.h>
25 #include <linux/omap-dma.h>
26 #include <linux/platform_data/spi-omap2-mcspi.h>
27 #include <linux/platform_data/asoc-ti-mcbsp.h>
28 #include <plat/dmtimer.h>
30 #include "omap_hwmod.h"
31 #include "omap_hwmod_common_data.h"
35 #include "prm-regbits-54xx.h"
40 /* Base offset for all OMAP5 interrupts external to MPUSS */
41 #define OMAP54XX_IRQ_GIC_START 32
43 /* Base offset for all OMAP5 dma requests */
44 #define OMAP54XX_DMA_REQ_START 1
55 static struct omap_hwmod_class omap54xx_dmm_hwmod_class
= {
60 static struct omap_hwmod omap54xx_dmm_hwmod
= {
62 .class = &omap54xx_dmm_hwmod_class
,
63 .clkdm_name
= "emif_clkdm",
66 .clkctrl_offs
= OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET
,
67 .context_offs
= OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET
,
74 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
76 static struct omap_hwmod_class omap54xx_l3_hwmod_class
= {
81 static struct omap_hwmod omap54xx_l3_instr_hwmod
= {
83 .class = &omap54xx_l3_hwmod_class
,
84 .clkdm_name
= "l3instr_clkdm",
87 .clkctrl_offs
= OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET
,
88 .context_offs
= OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET
,
89 .modulemode
= MODULEMODE_HWCTRL
,
95 static struct omap_hwmod omap54xx_l3_main_1_hwmod
= {
97 .class = &omap54xx_l3_hwmod_class
,
98 .clkdm_name
= "l3main1_clkdm",
101 .clkctrl_offs
= OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET
,
102 .context_offs
= OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET
,
108 static struct omap_hwmod omap54xx_l3_main_2_hwmod
= {
110 .class = &omap54xx_l3_hwmod_class
,
111 .clkdm_name
= "l3main2_clkdm",
114 .clkctrl_offs
= OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET
,
115 .context_offs
= OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET
,
121 static struct omap_hwmod omap54xx_l3_main_3_hwmod
= {
123 .class = &omap54xx_l3_hwmod_class
,
124 .clkdm_name
= "l3instr_clkdm",
127 .clkctrl_offs
= OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET
,
128 .context_offs
= OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET
,
129 .modulemode
= MODULEMODE_HWCTRL
,
136 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
138 static struct omap_hwmod_class omap54xx_l4_hwmod_class
= {
143 static struct omap_hwmod omap54xx_l4_abe_hwmod
= {
145 .class = &omap54xx_l4_hwmod_class
,
146 .clkdm_name
= "abe_clkdm",
149 .clkctrl_offs
= OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET
,
150 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
156 static struct omap_hwmod omap54xx_l4_cfg_hwmod
= {
158 .class = &omap54xx_l4_hwmod_class
,
159 .clkdm_name
= "l4cfg_clkdm",
162 .clkctrl_offs
= OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET
,
163 .context_offs
= OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET
,
169 static struct omap_hwmod omap54xx_l4_per_hwmod
= {
171 .class = &omap54xx_l4_hwmod_class
,
172 .clkdm_name
= "l4per_clkdm",
175 .clkctrl_offs
= OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET
,
176 .context_offs
= OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET
,
182 static struct omap_hwmod omap54xx_l4_wkup_hwmod
= {
184 .class = &omap54xx_l4_hwmod_class
,
185 .clkdm_name
= "wkupaon_clkdm",
188 .clkctrl_offs
= OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET
,
189 .context_offs
= OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET
,
196 * instance(s): mpu_private
198 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class
= {
203 static struct omap_hwmod omap54xx_mpu_private_hwmod
= {
204 .name
= "mpu_private",
205 .class = &omap54xx_mpu_bus_hwmod_class
,
206 .clkdm_name
= "mpu_clkdm",
209 .flags
= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT
,
216 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
219 static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc
= {
222 .sysc_flags
= SYSC_HAS_SIDLEMODE
,
223 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
),
224 .sysc_fields
= &omap_hwmod_sysc_type1
,
227 static struct omap_hwmod_class omap54xx_counter_hwmod_class
= {
229 .sysc
= &omap54xx_counter_sysc
,
233 static struct omap_hwmod omap54xx_counter_32k_hwmod
= {
234 .name
= "counter_32k",
235 .class = &omap54xx_counter_hwmod_class
,
236 .clkdm_name
= "wkupaon_clkdm",
237 .flags
= HWMOD_SWSUP_SIDLE
,
238 .main_clk
= "wkupaon_iclk_mux",
241 .clkctrl_offs
= OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET
,
242 .context_offs
= OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET
,
249 * dma controller for data exchange between memory to memory (i.e. internal or
250 * external memory) and gp peripherals to memory or memory to gp peripherals
253 static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc
= {
257 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
258 SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
259 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
260 SYSS_HAS_RESET_STATUS
),
261 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
262 MSTANDBY_FORCE
| MSTANDBY_NO
| MSTANDBY_SMART
),
263 .sysc_fields
= &omap_hwmod_sysc_type1
,
266 static struct omap_hwmod_class omap54xx_dma_hwmod_class
= {
268 .sysc
= &omap54xx_dma_sysc
,
272 static struct omap_dma_dev_attr dma_dev_attr
= {
273 .dev_caps
= RESERVE_CHANNEL
| DMA_LINKED_LCH
| GLOBAL_PRIORITY
|
274 IS_CSSA_32
| IS_CDSA_32
| IS_RW_PRIORITY
,
279 static struct omap_hwmod_irq_info omap54xx_dma_system_irqs
[] = {
280 { .name
= "0", .irq
= 12 + OMAP54XX_IRQ_GIC_START
},
281 { .name
= "1", .irq
= 13 + OMAP54XX_IRQ_GIC_START
},
282 { .name
= "2", .irq
= 14 + OMAP54XX_IRQ_GIC_START
},
283 { .name
= "3", .irq
= 15 + OMAP54XX_IRQ_GIC_START
},
287 static struct omap_hwmod omap54xx_dma_system_hwmod
= {
288 .name
= "dma_system",
289 .class = &omap54xx_dma_hwmod_class
,
290 .clkdm_name
= "dma_clkdm",
291 .mpu_irqs
= omap54xx_dma_system_irqs
,
292 .main_clk
= "l3_iclk_div",
295 .clkctrl_offs
= OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET
,
296 .context_offs
= OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET
,
299 .dev_attr
= &dma_dev_attr
,
304 * digital microphone controller
307 static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc
= {
310 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
311 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
312 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
314 .sysc_fields
= &omap_hwmod_sysc_type2
,
317 static struct omap_hwmod_class omap54xx_dmic_hwmod_class
= {
319 .sysc
= &omap54xx_dmic_sysc
,
323 static struct omap_hwmod omap54xx_dmic_hwmod
= {
325 .class = &omap54xx_dmic_hwmod_class
,
326 .clkdm_name
= "abe_clkdm",
327 .main_clk
= "dmic_gfclk",
330 .clkctrl_offs
= OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET
,
331 .context_offs
= OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET
,
332 .modulemode
= MODULEMODE_SWCTRL
,
339 * external memory interface no1 (wrapper)
342 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc
= {
346 static struct omap_hwmod_class omap54xx_emif_hwmod_class
= {
348 .sysc
= &omap54xx_emif_sysc
,
352 static struct omap_hwmod omap54xx_emif1_hwmod
= {
354 .class = &omap54xx_emif_hwmod_class
,
355 .clkdm_name
= "emif_clkdm",
356 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
357 .main_clk
= "dpll_core_h11x2_ck",
360 .clkctrl_offs
= OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET
,
361 .context_offs
= OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET
,
362 .modulemode
= MODULEMODE_HWCTRL
,
368 static struct omap_hwmod omap54xx_emif2_hwmod
= {
370 .class = &omap54xx_emif_hwmod_class
,
371 .clkdm_name
= "emif_clkdm",
372 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
373 .main_clk
= "dpll_core_h11x2_ck",
376 .clkctrl_offs
= OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET
,
377 .context_offs
= OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET
,
378 .modulemode
= MODULEMODE_HWCTRL
,
385 * general purpose io module
388 static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc
= {
392 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
393 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
394 SYSS_HAS_RESET_STATUS
),
395 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
397 .sysc_fields
= &omap_hwmod_sysc_type1
,
400 static struct omap_hwmod_class omap54xx_gpio_hwmod_class
= {
402 .sysc
= &omap54xx_gpio_sysc
,
407 static struct omap_gpio_dev_attr gpio_dev_attr
= {
413 static struct omap_hwmod_opt_clk gpio1_opt_clks
[] = {
414 { .role
= "dbclk", .clk
= "gpio1_dbclk" },
417 static struct omap_hwmod omap54xx_gpio1_hwmod
= {
419 .class = &omap54xx_gpio_hwmod_class
,
420 .clkdm_name
= "wkupaon_clkdm",
421 .main_clk
= "wkupaon_iclk_mux",
424 .clkctrl_offs
= OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET
,
425 .context_offs
= OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET
,
426 .modulemode
= MODULEMODE_HWCTRL
,
429 .opt_clks
= gpio1_opt_clks
,
430 .opt_clks_cnt
= ARRAY_SIZE(gpio1_opt_clks
),
431 .dev_attr
= &gpio_dev_attr
,
435 static struct omap_hwmod_opt_clk gpio2_opt_clks
[] = {
436 { .role
= "dbclk", .clk
= "gpio2_dbclk" },
439 static struct omap_hwmod omap54xx_gpio2_hwmod
= {
441 .class = &omap54xx_gpio_hwmod_class
,
442 .clkdm_name
= "l4per_clkdm",
443 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
444 .main_clk
= "l4_root_clk_div",
447 .clkctrl_offs
= OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET
,
448 .context_offs
= OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET
,
449 .modulemode
= MODULEMODE_HWCTRL
,
452 .opt_clks
= gpio2_opt_clks
,
453 .opt_clks_cnt
= ARRAY_SIZE(gpio2_opt_clks
),
454 .dev_attr
= &gpio_dev_attr
,
458 static struct omap_hwmod_opt_clk gpio3_opt_clks
[] = {
459 { .role
= "dbclk", .clk
= "gpio3_dbclk" },
462 static struct omap_hwmod omap54xx_gpio3_hwmod
= {
464 .class = &omap54xx_gpio_hwmod_class
,
465 .clkdm_name
= "l4per_clkdm",
466 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
467 .main_clk
= "l4_root_clk_div",
470 .clkctrl_offs
= OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET
,
471 .context_offs
= OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET
,
472 .modulemode
= MODULEMODE_HWCTRL
,
475 .opt_clks
= gpio3_opt_clks
,
476 .opt_clks_cnt
= ARRAY_SIZE(gpio3_opt_clks
),
477 .dev_attr
= &gpio_dev_attr
,
481 static struct omap_hwmod_opt_clk gpio4_opt_clks
[] = {
482 { .role
= "dbclk", .clk
= "gpio4_dbclk" },
485 static struct omap_hwmod omap54xx_gpio4_hwmod
= {
487 .class = &omap54xx_gpio_hwmod_class
,
488 .clkdm_name
= "l4per_clkdm",
489 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
490 .main_clk
= "l4_root_clk_div",
493 .clkctrl_offs
= OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET
,
494 .context_offs
= OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET
,
495 .modulemode
= MODULEMODE_HWCTRL
,
498 .opt_clks
= gpio4_opt_clks
,
499 .opt_clks_cnt
= ARRAY_SIZE(gpio4_opt_clks
),
500 .dev_attr
= &gpio_dev_attr
,
504 static struct omap_hwmod_opt_clk gpio5_opt_clks
[] = {
505 { .role
= "dbclk", .clk
= "gpio5_dbclk" },
508 static struct omap_hwmod omap54xx_gpio5_hwmod
= {
510 .class = &omap54xx_gpio_hwmod_class
,
511 .clkdm_name
= "l4per_clkdm",
512 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
513 .main_clk
= "l4_root_clk_div",
516 .clkctrl_offs
= OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET
,
517 .context_offs
= OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET
,
518 .modulemode
= MODULEMODE_HWCTRL
,
521 .opt_clks
= gpio5_opt_clks
,
522 .opt_clks_cnt
= ARRAY_SIZE(gpio5_opt_clks
),
523 .dev_attr
= &gpio_dev_attr
,
527 static struct omap_hwmod_opt_clk gpio6_opt_clks
[] = {
528 { .role
= "dbclk", .clk
= "gpio6_dbclk" },
531 static struct omap_hwmod omap54xx_gpio6_hwmod
= {
533 .class = &omap54xx_gpio_hwmod_class
,
534 .clkdm_name
= "l4per_clkdm",
535 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
536 .main_clk
= "l4_root_clk_div",
539 .clkctrl_offs
= OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET
,
540 .context_offs
= OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET
,
541 .modulemode
= MODULEMODE_HWCTRL
,
544 .opt_clks
= gpio6_opt_clks
,
545 .opt_clks_cnt
= ARRAY_SIZE(gpio6_opt_clks
),
546 .dev_attr
= &gpio_dev_attr
,
550 static struct omap_hwmod_opt_clk gpio7_opt_clks
[] = {
551 { .role
= "dbclk", .clk
= "gpio7_dbclk" },
554 static struct omap_hwmod omap54xx_gpio7_hwmod
= {
556 .class = &omap54xx_gpio_hwmod_class
,
557 .clkdm_name
= "l4per_clkdm",
558 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
559 .main_clk
= "l4_root_clk_div",
562 .clkctrl_offs
= OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET
,
563 .context_offs
= OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET
,
564 .modulemode
= MODULEMODE_HWCTRL
,
567 .opt_clks
= gpio7_opt_clks
,
568 .opt_clks_cnt
= ARRAY_SIZE(gpio7_opt_clks
),
569 .dev_attr
= &gpio_dev_attr
,
573 static struct omap_hwmod_opt_clk gpio8_opt_clks
[] = {
574 { .role
= "dbclk", .clk
= "gpio8_dbclk" },
577 static struct omap_hwmod omap54xx_gpio8_hwmod
= {
579 .class = &omap54xx_gpio_hwmod_class
,
580 .clkdm_name
= "l4per_clkdm",
581 .flags
= HWMOD_CONTROL_OPT_CLKS_IN_RESET
,
582 .main_clk
= "l4_root_clk_div",
585 .clkctrl_offs
= OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET
,
586 .context_offs
= OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET
,
587 .modulemode
= MODULEMODE_HWCTRL
,
590 .opt_clks
= gpio8_opt_clks
,
591 .opt_clks_cnt
= ARRAY_SIZE(gpio8_opt_clks
),
592 .dev_attr
= &gpio_dev_attr
,
597 * multimaster high-speed i2c controller
600 static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc
= {
603 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_CLOCKACTIVITY
|
604 SYSC_HAS_ENAWAKEUP
| SYSC_HAS_SIDLEMODE
|
605 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
606 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
608 .clockact
= CLOCKACT_TEST_ICLK
,
609 .sysc_fields
= &omap_hwmod_sysc_type1
,
612 static struct omap_hwmod_class omap54xx_i2c_hwmod_class
= {
614 .sysc
= &omap54xx_i2c_sysc
,
615 .reset
= &omap_i2c_reset
,
616 .rev
= OMAP_I2C_IP_VERSION_2
,
620 static struct omap_i2c_dev_attr i2c_dev_attr
= {
621 .flags
= OMAP_I2C_FLAG_BUS_SHIFT_NONE
,
625 static struct omap_hwmod omap54xx_i2c1_hwmod
= {
627 .class = &omap54xx_i2c_hwmod_class
,
628 .clkdm_name
= "l4per_clkdm",
629 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
630 .main_clk
= "func_96m_fclk",
633 .clkctrl_offs
= OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET
,
634 .context_offs
= OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET
,
635 .modulemode
= MODULEMODE_SWCTRL
,
638 .dev_attr
= &i2c_dev_attr
,
642 static struct omap_hwmod omap54xx_i2c2_hwmod
= {
644 .class = &omap54xx_i2c_hwmod_class
,
645 .clkdm_name
= "l4per_clkdm",
646 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
647 .main_clk
= "func_96m_fclk",
650 .clkctrl_offs
= OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET
,
651 .context_offs
= OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET
,
652 .modulemode
= MODULEMODE_SWCTRL
,
655 .dev_attr
= &i2c_dev_attr
,
659 static struct omap_hwmod omap54xx_i2c3_hwmod
= {
661 .class = &omap54xx_i2c_hwmod_class
,
662 .clkdm_name
= "l4per_clkdm",
663 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
664 .main_clk
= "func_96m_fclk",
667 .clkctrl_offs
= OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET
,
668 .context_offs
= OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET
,
669 .modulemode
= MODULEMODE_SWCTRL
,
672 .dev_attr
= &i2c_dev_attr
,
676 static struct omap_hwmod omap54xx_i2c4_hwmod
= {
678 .class = &omap54xx_i2c_hwmod_class
,
679 .clkdm_name
= "l4per_clkdm",
680 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
681 .main_clk
= "func_96m_fclk",
684 .clkctrl_offs
= OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET
,
685 .context_offs
= OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET
,
686 .modulemode
= MODULEMODE_SWCTRL
,
689 .dev_attr
= &i2c_dev_attr
,
693 static struct omap_hwmod omap54xx_i2c5_hwmod
= {
695 .class = &omap54xx_i2c_hwmod_class
,
696 .clkdm_name
= "l4per_clkdm",
697 .flags
= HWMOD_16BIT_REG
| HWMOD_SET_DEFAULT_CLOCKACT
,
698 .main_clk
= "func_96m_fclk",
701 .clkctrl_offs
= OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET
,
702 .context_offs
= OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET
,
703 .modulemode
= MODULEMODE_SWCTRL
,
706 .dev_attr
= &i2c_dev_attr
,
711 * keyboard controller
714 static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc
= {
717 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_SIDLEMODE
|
719 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
720 .sysc_fields
= &omap_hwmod_sysc_type1
,
723 static struct omap_hwmod_class omap54xx_kbd_hwmod_class
= {
725 .sysc
= &omap54xx_kbd_sysc
,
729 static struct omap_hwmod omap54xx_kbd_hwmod
= {
731 .class = &omap54xx_kbd_hwmod_class
,
732 .clkdm_name
= "wkupaon_clkdm",
733 .main_clk
= "sys_32k_ck",
736 .clkctrl_offs
= OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET
,
737 .context_offs
= OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET
,
738 .modulemode
= MODULEMODE_SWCTRL
,
745 * multi channel buffered serial port controller
748 static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc
= {
750 .sysc_flags
= (SYSC_HAS_CLOCKACTIVITY
| SYSC_HAS_ENAWAKEUP
|
751 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
752 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
),
753 .sysc_fields
= &omap_hwmod_sysc_type1
,
756 static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class
= {
758 .sysc
= &omap54xx_mcbsp_sysc
,
759 .rev
= MCBSP_CONFIG_TYPE4
,
763 static struct omap_hwmod_opt_clk mcbsp1_opt_clks
[] = {
764 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
765 { .role
= "prcm_fck", .clk
= "mcbsp1_sync_mux_ck" },
768 static struct omap_hwmod omap54xx_mcbsp1_hwmod
= {
770 .class = &omap54xx_mcbsp_hwmod_class
,
771 .clkdm_name
= "abe_clkdm",
772 .main_clk
= "mcbsp1_gfclk",
775 .clkctrl_offs
= OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET
,
776 .context_offs
= OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET
,
777 .modulemode
= MODULEMODE_SWCTRL
,
780 .opt_clks
= mcbsp1_opt_clks
,
781 .opt_clks_cnt
= ARRAY_SIZE(mcbsp1_opt_clks
),
785 static struct omap_hwmod_opt_clk mcbsp2_opt_clks
[] = {
786 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
787 { .role
= "prcm_fck", .clk
= "mcbsp2_sync_mux_ck" },
790 static struct omap_hwmod omap54xx_mcbsp2_hwmod
= {
792 .class = &omap54xx_mcbsp_hwmod_class
,
793 .clkdm_name
= "abe_clkdm",
794 .main_clk
= "mcbsp2_gfclk",
797 .clkctrl_offs
= OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET
,
798 .context_offs
= OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET
,
799 .modulemode
= MODULEMODE_SWCTRL
,
802 .opt_clks
= mcbsp2_opt_clks
,
803 .opt_clks_cnt
= ARRAY_SIZE(mcbsp2_opt_clks
),
807 static struct omap_hwmod_opt_clk mcbsp3_opt_clks
[] = {
808 { .role
= "pad_fck", .clk
= "pad_clks_ck" },
809 { .role
= "prcm_fck", .clk
= "mcbsp3_sync_mux_ck" },
812 static struct omap_hwmod omap54xx_mcbsp3_hwmod
= {
814 .class = &omap54xx_mcbsp_hwmod_class
,
815 .clkdm_name
= "abe_clkdm",
816 .main_clk
= "mcbsp3_gfclk",
819 .clkctrl_offs
= OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET
,
820 .context_offs
= OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET
,
821 .modulemode
= MODULEMODE_SWCTRL
,
824 .opt_clks
= mcbsp3_opt_clks
,
825 .opt_clks_cnt
= ARRAY_SIZE(mcbsp3_opt_clks
),
830 * multi channel pdm controller (proprietary interface with phoenix power
834 static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc
= {
837 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
838 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
839 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
841 .sysc_fields
= &omap_hwmod_sysc_type2
,
844 static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class
= {
846 .sysc
= &omap54xx_mcpdm_sysc
,
850 static struct omap_hwmod omap54xx_mcpdm_hwmod
= {
852 .class = &omap54xx_mcpdm_hwmod_class
,
853 .clkdm_name
= "abe_clkdm",
855 * It's suspected that the McPDM requires an off-chip main
856 * functional clock, controlled via I2C. This IP block is
857 * currently reset very early during boot, before I2C is
858 * available, so it doesn't seem that we have any choice in
859 * the kernel other than to avoid resetting it. XXX This is
860 * really a hardware issue workaround: every IP block should
861 * be able to source its main functional clock from either
862 * on-chip or off-chip sources. McPDM seems to be the only
866 .flags
= HWMOD_EXT_OPT_MAIN_CLK
,
867 .main_clk
= "pad_clks_ck",
870 .clkctrl_offs
= OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET
,
871 .context_offs
= OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET
,
872 .modulemode
= MODULEMODE_SWCTRL
,
879 * multichannel serial port interface (mcspi) / master/slave synchronous serial
883 static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc
= {
886 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
887 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
888 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
890 .sysc_fields
= &omap_hwmod_sysc_type2
,
893 static struct omap_hwmod_class omap54xx_mcspi_hwmod_class
= {
895 .sysc
= &omap54xx_mcspi_sysc
,
896 .rev
= OMAP4_MCSPI_REV
,
900 /* mcspi1 dev_attr */
901 static struct omap2_mcspi_dev_attr mcspi1_dev_attr
= {
905 static struct omap_hwmod omap54xx_mcspi1_hwmod
= {
907 .class = &omap54xx_mcspi_hwmod_class
,
908 .clkdm_name
= "l4per_clkdm",
909 .main_clk
= "func_48m_fclk",
912 .clkctrl_offs
= OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET
,
913 .context_offs
= OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET
,
914 .modulemode
= MODULEMODE_SWCTRL
,
917 .dev_attr
= &mcspi1_dev_attr
,
921 /* mcspi2 dev_attr */
922 static struct omap2_mcspi_dev_attr mcspi2_dev_attr
= {
926 static struct omap_hwmod omap54xx_mcspi2_hwmod
= {
928 .class = &omap54xx_mcspi_hwmod_class
,
929 .clkdm_name
= "l4per_clkdm",
930 .main_clk
= "func_48m_fclk",
933 .clkctrl_offs
= OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET
,
934 .context_offs
= OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET
,
935 .modulemode
= MODULEMODE_SWCTRL
,
938 .dev_attr
= &mcspi2_dev_attr
,
942 /* mcspi3 dev_attr */
943 static struct omap2_mcspi_dev_attr mcspi3_dev_attr
= {
947 static struct omap_hwmod omap54xx_mcspi3_hwmod
= {
949 .class = &omap54xx_mcspi_hwmod_class
,
950 .clkdm_name
= "l4per_clkdm",
951 .main_clk
= "func_48m_fclk",
954 .clkctrl_offs
= OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET
,
955 .context_offs
= OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET
,
956 .modulemode
= MODULEMODE_SWCTRL
,
959 .dev_attr
= &mcspi3_dev_attr
,
963 /* mcspi4 dev_attr */
964 static struct omap2_mcspi_dev_attr mcspi4_dev_attr
= {
968 static struct omap_hwmod omap54xx_mcspi4_hwmod
= {
970 .class = &omap54xx_mcspi_hwmod_class
,
971 .clkdm_name
= "l4per_clkdm",
972 .main_clk
= "func_48m_fclk",
975 .clkctrl_offs
= OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET
,
976 .context_offs
= OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET
,
977 .modulemode
= MODULEMODE_SWCTRL
,
980 .dev_attr
= &mcspi4_dev_attr
,
985 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
988 static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc
= {
991 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_MIDLEMODE
|
992 SYSC_HAS_RESET_STATUS
| SYSC_HAS_SIDLEMODE
|
994 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
995 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
996 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
997 .sysc_fields
= &omap_hwmod_sysc_type2
,
1000 static struct omap_hwmod_class omap54xx_mmc_hwmod_class
= {
1002 .sysc
= &omap54xx_mmc_sysc
,
1006 static struct omap_hwmod_opt_clk mmc1_opt_clks
[] = {
1007 { .role
= "32khz_clk", .clk
= "mmc1_32khz_clk" },
1011 static struct omap_mmc_dev_attr mmc1_dev_attr
= {
1012 .flags
= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
,
1015 static struct omap_hwmod omap54xx_mmc1_hwmod
= {
1017 .class = &omap54xx_mmc_hwmod_class
,
1018 .clkdm_name
= "l3init_clkdm",
1019 .main_clk
= "mmc1_fclk",
1022 .clkctrl_offs
= OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET
,
1023 .context_offs
= OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET
,
1024 .modulemode
= MODULEMODE_SWCTRL
,
1027 .opt_clks
= mmc1_opt_clks
,
1028 .opt_clks_cnt
= ARRAY_SIZE(mmc1_opt_clks
),
1029 .dev_attr
= &mmc1_dev_attr
,
1033 static struct omap_hwmod omap54xx_mmc2_hwmod
= {
1035 .class = &omap54xx_mmc_hwmod_class
,
1036 .clkdm_name
= "l3init_clkdm",
1037 .main_clk
= "mmc2_fclk",
1040 .clkctrl_offs
= OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET
,
1041 .context_offs
= OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET
,
1042 .modulemode
= MODULEMODE_SWCTRL
,
1048 static struct omap_hwmod omap54xx_mmc3_hwmod
= {
1050 .class = &omap54xx_mmc_hwmod_class
,
1051 .clkdm_name
= "l4per_clkdm",
1052 .main_clk
= "func_48m_fclk",
1055 .clkctrl_offs
= OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET
,
1056 .context_offs
= OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET
,
1057 .modulemode
= MODULEMODE_SWCTRL
,
1063 static struct omap_hwmod omap54xx_mmc4_hwmod
= {
1065 .class = &omap54xx_mmc_hwmod_class
,
1066 .clkdm_name
= "l4per_clkdm",
1067 .main_clk
= "func_48m_fclk",
1070 .clkctrl_offs
= OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET
,
1071 .context_offs
= OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET
,
1072 .modulemode
= MODULEMODE_SWCTRL
,
1078 static struct omap_hwmod omap54xx_mmc5_hwmod
= {
1080 .class = &omap54xx_mmc_hwmod_class
,
1081 .clkdm_name
= "l4per_clkdm",
1082 .main_clk
= "func_96m_fclk",
1085 .clkctrl_offs
= OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET
,
1086 .context_offs
= OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET
,
1087 .modulemode
= MODULEMODE_SWCTRL
,
1097 static struct omap_hwmod_class omap54xx_mpu_hwmod_class
= {
1102 static struct omap_hwmod omap54xx_mpu_hwmod
= {
1104 .class = &omap54xx_mpu_hwmod_class
,
1105 .clkdm_name
= "mpu_clkdm",
1106 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1107 .main_clk
= "dpll_mpu_m2_ck",
1110 .clkctrl_offs
= OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET
,
1111 .context_offs
= OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET
,
1118 * general purpose timer module with accurate 1ms tick
1119 * This class contains several variants: ['timer_1ms', 'timer']
1122 static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc
= {
1124 .sysc_offs
= 0x0010,
1125 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
1126 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1127 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1129 .sysc_fields
= &omap_hwmod_sysc_type2
,
1130 .clockact
= CLOCKACT_TEST_ICLK
,
1133 static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class
= {
1135 .sysc
= &omap54xx_timer_1ms_sysc
,
1138 static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc
= {
1140 .sysc_offs
= 0x0010,
1141 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_RESET_STATUS
|
1142 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
),
1143 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1145 .sysc_fields
= &omap_hwmod_sysc_type2
,
1148 static struct omap_hwmod_class omap54xx_timer_hwmod_class
= {
1150 .sysc
= &omap54xx_timer_sysc
,
1154 static struct omap_hwmod omap54xx_timer1_hwmod
= {
1156 .class = &omap54xx_timer_1ms_hwmod_class
,
1157 .clkdm_name
= "wkupaon_clkdm",
1158 .main_clk
= "timer1_gfclk_mux",
1159 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
1162 .clkctrl_offs
= OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET
,
1163 .context_offs
= OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET
,
1164 .modulemode
= MODULEMODE_SWCTRL
,
1170 static struct omap_hwmod omap54xx_timer2_hwmod
= {
1172 .class = &omap54xx_timer_1ms_hwmod_class
,
1173 .clkdm_name
= "l4per_clkdm",
1174 .main_clk
= "timer2_gfclk_mux",
1175 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
1178 .clkctrl_offs
= OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET
,
1179 .context_offs
= OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET
,
1180 .modulemode
= MODULEMODE_SWCTRL
,
1186 static struct omap_hwmod omap54xx_timer3_hwmod
= {
1188 .class = &omap54xx_timer_hwmod_class
,
1189 .clkdm_name
= "l4per_clkdm",
1190 .main_clk
= "timer3_gfclk_mux",
1193 .clkctrl_offs
= OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET
,
1194 .context_offs
= OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET
,
1195 .modulemode
= MODULEMODE_SWCTRL
,
1201 static struct omap_hwmod omap54xx_timer4_hwmod
= {
1203 .class = &omap54xx_timer_hwmod_class
,
1204 .clkdm_name
= "l4per_clkdm",
1205 .main_clk
= "timer4_gfclk_mux",
1208 .clkctrl_offs
= OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET
,
1209 .context_offs
= OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET
,
1210 .modulemode
= MODULEMODE_SWCTRL
,
1216 static struct omap_hwmod omap54xx_timer5_hwmod
= {
1218 .class = &omap54xx_timer_hwmod_class
,
1219 .clkdm_name
= "abe_clkdm",
1220 .main_clk
= "timer5_gfclk_mux",
1223 .clkctrl_offs
= OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET
,
1224 .context_offs
= OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET
,
1225 .modulemode
= MODULEMODE_SWCTRL
,
1231 static struct omap_hwmod omap54xx_timer6_hwmod
= {
1233 .class = &omap54xx_timer_hwmod_class
,
1234 .clkdm_name
= "abe_clkdm",
1235 .main_clk
= "timer6_gfclk_mux",
1238 .clkctrl_offs
= OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET
,
1239 .context_offs
= OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET
,
1240 .modulemode
= MODULEMODE_SWCTRL
,
1246 static struct omap_hwmod omap54xx_timer7_hwmod
= {
1248 .class = &omap54xx_timer_hwmod_class
,
1249 .clkdm_name
= "abe_clkdm",
1250 .main_clk
= "timer7_gfclk_mux",
1253 .clkctrl_offs
= OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET
,
1254 .context_offs
= OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET
,
1255 .modulemode
= MODULEMODE_SWCTRL
,
1261 static struct omap_hwmod omap54xx_timer8_hwmod
= {
1263 .class = &omap54xx_timer_hwmod_class
,
1264 .clkdm_name
= "abe_clkdm",
1265 .main_clk
= "timer8_gfclk_mux",
1268 .clkctrl_offs
= OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET
,
1269 .context_offs
= OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET
,
1270 .modulemode
= MODULEMODE_SWCTRL
,
1276 static struct omap_hwmod omap54xx_timer9_hwmod
= {
1278 .class = &omap54xx_timer_hwmod_class
,
1279 .clkdm_name
= "l4per_clkdm",
1280 .main_clk
= "timer9_gfclk_mux",
1283 .clkctrl_offs
= OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET
,
1284 .context_offs
= OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET
,
1285 .modulemode
= MODULEMODE_SWCTRL
,
1291 static struct omap_hwmod omap54xx_timer10_hwmod
= {
1293 .class = &omap54xx_timer_1ms_hwmod_class
,
1294 .clkdm_name
= "l4per_clkdm",
1295 .main_clk
= "timer10_gfclk_mux",
1296 .flags
= HWMOD_SET_DEFAULT_CLOCKACT
,
1299 .clkctrl_offs
= OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET
,
1300 .context_offs
= OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET
,
1301 .modulemode
= MODULEMODE_SWCTRL
,
1307 static struct omap_hwmod omap54xx_timer11_hwmod
= {
1309 .class = &omap54xx_timer_hwmod_class
,
1310 .clkdm_name
= "l4per_clkdm",
1311 .main_clk
= "timer11_gfclk_mux",
1314 .clkctrl_offs
= OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET
,
1315 .context_offs
= OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET
,
1316 .modulemode
= MODULEMODE_SWCTRL
,
1323 * universal asynchronous receiver/transmitter (uart)
1326 static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc
= {
1328 .sysc_offs
= 0x0054,
1329 .syss_offs
= 0x0058,
1330 .sysc_flags
= (SYSC_HAS_AUTOIDLE
| SYSC_HAS_ENAWAKEUP
|
1331 SYSC_HAS_SIDLEMODE
| SYSC_HAS_SOFTRESET
|
1332 SYSS_HAS_RESET_STATUS
),
1333 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1335 .sysc_fields
= &omap_hwmod_sysc_type1
,
1338 static struct omap_hwmod_class omap54xx_uart_hwmod_class
= {
1340 .sysc
= &omap54xx_uart_sysc
,
1344 static struct omap_hwmod omap54xx_uart1_hwmod
= {
1346 .class = &omap54xx_uart_hwmod_class
,
1347 .clkdm_name
= "l4per_clkdm",
1348 .main_clk
= "func_48m_fclk",
1351 .clkctrl_offs
= OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET
,
1352 .context_offs
= OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET
,
1353 .modulemode
= MODULEMODE_SWCTRL
,
1359 static struct omap_hwmod omap54xx_uart2_hwmod
= {
1361 .class = &omap54xx_uart_hwmod_class
,
1362 .clkdm_name
= "l4per_clkdm",
1363 .main_clk
= "func_48m_fclk",
1366 .clkctrl_offs
= OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET
,
1367 .context_offs
= OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET
,
1368 .modulemode
= MODULEMODE_SWCTRL
,
1374 static struct omap_hwmod omap54xx_uart3_hwmod
= {
1376 .class = &omap54xx_uart_hwmod_class
,
1377 .clkdm_name
= "l4per_clkdm",
1378 .flags
= HWMOD_INIT_NO_IDLE
| HWMOD_INIT_NO_RESET
,
1379 .main_clk
= "func_48m_fclk",
1382 .clkctrl_offs
= OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET
,
1383 .context_offs
= OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET
,
1384 .modulemode
= MODULEMODE_SWCTRL
,
1390 static struct omap_hwmod omap54xx_uart4_hwmod
= {
1392 .class = &omap54xx_uart_hwmod_class
,
1393 .clkdm_name
= "l4per_clkdm",
1394 .main_clk
= "func_48m_fclk",
1397 .clkctrl_offs
= OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET
,
1398 .context_offs
= OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET
,
1399 .modulemode
= MODULEMODE_SWCTRL
,
1405 static struct omap_hwmod omap54xx_uart5_hwmod
= {
1407 .class = &omap54xx_uart_hwmod_class
,
1408 .clkdm_name
= "l4per_clkdm",
1409 .main_clk
= "func_48m_fclk",
1412 .clkctrl_offs
= OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET
,
1413 .context_offs
= OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET
,
1414 .modulemode
= MODULEMODE_SWCTRL
,
1420 static struct omap_hwmod omap54xx_uart6_hwmod
= {
1422 .class = &omap54xx_uart_hwmod_class
,
1423 .clkdm_name
= "l4per_clkdm",
1424 .main_clk
= "func_48m_fclk",
1427 .clkctrl_offs
= OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET
,
1428 .context_offs
= OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET
,
1429 .modulemode
= MODULEMODE_SWCTRL
,
1435 * 'usb_otg_ss' class
1436 * 2.0 super speed (usb_otg_ss) controller
1439 static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc
= {
1441 .sysc_offs
= 0x0010,
1442 .sysc_flags
= (SYSC_HAS_DMADISABLE
| SYSC_HAS_MIDLEMODE
|
1443 SYSC_HAS_SIDLEMODE
),
1444 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1445 SIDLE_SMART_WKUP
| MSTANDBY_FORCE
| MSTANDBY_NO
|
1446 MSTANDBY_SMART
| MSTANDBY_SMART_WKUP
),
1447 .sysc_fields
= &omap_hwmod_sysc_type2
,
1450 static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class
= {
1451 .name
= "usb_otg_ss",
1452 .sysc
= &omap54xx_usb_otg_ss_sysc
,
1456 static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks
[] = {
1457 { .role
= "refclk960m", .clk
= "usb_otg_ss_refclk960m" },
1460 static struct omap_hwmod omap54xx_usb_otg_ss_hwmod
= {
1461 .name
= "usb_otg_ss",
1462 .class = &omap54xx_usb_otg_ss_hwmod_class
,
1463 .clkdm_name
= "l3init_clkdm",
1464 .flags
= HWMOD_SWSUP_SIDLE
,
1465 .main_clk
= "dpll_core_h13x2_ck",
1468 .clkctrl_offs
= OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET
,
1469 .context_offs
= OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET
,
1470 .modulemode
= MODULEMODE_HWCTRL
,
1473 .opt_clks
= usb_otg_ss_opt_clks
,
1474 .opt_clks_cnt
= ARRAY_SIZE(usb_otg_ss_opt_clks
),
1479 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1480 * overflow condition
1483 static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc
= {
1485 .sysc_offs
= 0x0010,
1486 .syss_offs
= 0x0014,
1487 .sysc_flags
= (SYSC_HAS_EMUFREE
| SYSC_HAS_SIDLEMODE
|
1488 SYSC_HAS_SOFTRESET
| SYSS_HAS_RESET_STATUS
),
1489 .idlemodes
= (SIDLE_FORCE
| SIDLE_NO
| SIDLE_SMART
|
1491 .sysc_fields
= &omap_hwmod_sysc_type1
,
1494 static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class
= {
1496 .sysc
= &omap54xx_wd_timer_sysc
,
1497 .pre_shutdown
= &omap2_wd_timer_disable
,
1501 static struct omap_hwmod omap54xx_wd_timer2_hwmod
= {
1502 .name
= "wd_timer2",
1503 .class = &omap54xx_wd_timer_hwmod_class
,
1504 .clkdm_name
= "wkupaon_clkdm",
1505 .main_clk
= "sys_32k_ck",
1508 .clkctrl_offs
= OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET
,
1509 .context_offs
= OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET
,
1510 .modulemode
= MODULEMODE_SWCTRL
,
1520 /* l3_main_1 -> dmm */
1521 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm
= {
1522 .master
= &omap54xx_l3_main_1_hwmod
,
1523 .slave
= &omap54xx_dmm_hwmod
,
1524 .clk
= "l3_iclk_div",
1525 .user
= OCP_USER_SDMA
,
1528 /* l3_main_3 -> l3_instr */
1529 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr
= {
1530 .master
= &omap54xx_l3_main_3_hwmod
,
1531 .slave
= &omap54xx_l3_instr_hwmod
,
1532 .clk
= "l3_iclk_div",
1533 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1536 /* l3_main_2 -> l3_main_1 */
1537 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1
= {
1538 .master
= &omap54xx_l3_main_2_hwmod
,
1539 .slave
= &omap54xx_l3_main_1_hwmod
,
1540 .clk
= "l3_iclk_div",
1541 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1544 /* l4_cfg -> l3_main_1 */
1545 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1
= {
1546 .master
= &omap54xx_l4_cfg_hwmod
,
1547 .slave
= &omap54xx_l3_main_1_hwmod
,
1548 .clk
= "l3_iclk_div",
1549 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1552 /* mpu -> l3_main_1 */
1553 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1
= {
1554 .master
= &omap54xx_mpu_hwmod
,
1555 .slave
= &omap54xx_l3_main_1_hwmod
,
1556 .clk
= "l3_iclk_div",
1557 .user
= OCP_USER_MPU
,
1560 /* l3_main_1 -> l3_main_2 */
1561 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2
= {
1562 .master
= &omap54xx_l3_main_1_hwmod
,
1563 .slave
= &omap54xx_l3_main_2_hwmod
,
1564 .clk
= "l3_iclk_div",
1565 .user
= OCP_USER_MPU
,
1568 /* l4_cfg -> l3_main_2 */
1569 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2
= {
1570 .master
= &omap54xx_l4_cfg_hwmod
,
1571 .slave
= &omap54xx_l3_main_2_hwmod
,
1572 .clk
= "l3_iclk_div",
1573 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1576 /* l3_main_1 -> l3_main_3 */
1577 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3
= {
1578 .master
= &omap54xx_l3_main_1_hwmod
,
1579 .slave
= &omap54xx_l3_main_3_hwmod
,
1580 .clk
= "l3_iclk_div",
1581 .user
= OCP_USER_MPU
,
1584 /* l3_main_2 -> l3_main_3 */
1585 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3
= {
1586 .master
= &omap54xx_l3_main_2_hwmod
,
1587 .slave
= &omap54xx_l3_main_3_hwmod
,
1588 .clk
= "l3_iclk_div",
1589 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1592 /* l4_cfg -> l3_main_3 */
1593 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3
= {
1594 .master
= &omap54xx_l4_cfg_hwmod
,
1595 .slave
= &omap54xx_l3_main_3_hwmod
,
1596 .clk
= "l3_iclk_div",
1597 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1600 /* l3_main_1 -> l4_abe */
1601 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe
= {
1602 .master
= &omap54xx_l3_main_1_hwmod
,
1603 .slave
= &omap54xx_l4_abe_hwmod
,
1605 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1609 static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe
= {
1610 .master
= &omap54xx_mpu_hwmod
,
1611 .slave
= &omap54xx_l4_abe_hwmod
,
1613 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1616 /* l3_main_1 -> l4_cfg */
1617 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg
= {
1618 .master
= &omap54xx_l3_main_1_hwmod
,
1619 .slave
= &omap54xx_l4_cfg_hwmod
,
1620 .clk
= "l4_root_clk_div",
1621 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1624 /* l3_main_2 -> l4_per */
1625 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per
= {
1626 .master
= &omap54xx_l3_main_2_hwmod
,
1627 .slave
= &omap54xx_l4_per_hwmod
,
1628 .clk
= "l4_root_clk_div",
1629 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1632 /* l3_main_1 -> l4_wkup */
1633 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup
= {
1634 .master
= &omap54xx_l3_main_1_hwmod
,
1635 .slave
= &omap54xx_l4_wkup_hwmod
,
1636 .clk
= "wkupaon_iclk_mux",
1637 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1640 /* mpu -> mpu_private */
1641 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private
= {
1642 .master
= &omap54xx_mpu_hwmod
,
1643 .slave
= &omap54xx_mpu_private_hwmod
,
1644 .clk
= "l3_iclk_div",
1645 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1648 /* l4_wkup -> counter_32k */
1649 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k
= {
1650 .master
= &omap54xx_l4_wkup_hwmod
,
1651 .slave
= &omap54xx_counter_32k_hwmod
,
1652 .clk
= "wkupaon_iclk_mux",
1653 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1656 static struct omap_hwmod_addr_space omap54xx_dma_system_addrs
[] = {
1658 .pa_start
= 0x4a056000,
1659 .pa_end
= 0x4a056fff,
1660 .flags
= ADDR_TYPE_RT
1665 /* l4_cfg -> dma_system */
1666 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system
= {
1667 .master
= &omap54xx_l4_cfg_hwmod
,
1668 .slave
= &omap54xx_dma_system_hwmod
,
1669 .clk
= "l4_root_clk_div",
1670 .addr
= omap54xx_dma_system_addrs
,
1671 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1674 /* l4_abe -> dmic */
1675 static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic
= {
1676 .master
= &omap54xx_l4_abe_hwmod
,
1677 .slave
= &omap54xx_dmic_hwmod
,
1679 .user
= OCP_USER_MPU
,
1683 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1
= {
1684 .master
= &omap54xx_mpu_hwmod
,
1685 .slave
= &omap54xx_emif1_hwmod
,
1686 .clk
= "dpll_core_h11x2_ck",
1687 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1691 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2
= {
1692 .master
= &omap54xx_mpu_hwmod
,
1693 .slave
= &omap54xx_emif2_hwmod
,
1694 .clk
= "dpll_core_h11x2_ck",
1695 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1698 /* l4_wkup -> gpio1 */
1699 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1
= {
1700 .master
= &omap54xx_l4_wkup_hwmod
,
1701 .slave
= &omap54xx_gpio1_hwmod
,
1702 .clk
= "wkupaon_iclk_mux",
1703 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1706 /* l4_per -> gpio2 */
1707 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2
= {
1708 .master
= &omap54xx_l4_per_hwmod
,
1709 .slave
= &omap54xx_gpio2_hwmod
,
1710 .clk
= "l4_root_clk_div",
1711 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1714 /* l4_per -> gpio3 */
1715 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3
= {
1716 .master
= &omap54xx_l4_per_hwmod
,
1717 .slave
= &omap54xx_gpio3_hwmod
,
1718 .clk
= "l4_root_clk_div",
1719 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1722 /* l4_per -> gpio4 */
1723 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4
= {
1724 .master
= &omap54xx_l4_per_hwmod
,
1725 .slave
= &omap54xx_gpio4_hwmod
,
1726 .clk
= "l4_root_clk_div",
1727 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1730 /* l4_per -> gpio5 */
1731 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5
= {
1732 .master
= &omap54xx_l4_per_hwmod
,
1733 .slave
= &omap54xx_gpio5_hwmod
,
1734 .clk
= "l4_root_clk_div",
1735 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1738 /* l4_per -> gpio6 */
1739 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6
= {
1740 .master
= &omap54xx_l4_per_hwmod
,
1741 .slave
= &omap54xx_gpio6_hwmod
,
1742 .clk
= "l4_root_clk_div",
1743 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1746 /* l4_per -> gpio7 */
1747 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7
= {
1748 .master
= &omap54xx_l4_per_hwmod
,
1749 .slave
= &omap54xx_gpio7_hwmod
,
1750 .clk
= "l4_root_clk_div",
1751 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1754 /* l4_per -> gpio8 */
1755 static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8
= {
1756 .master
= &omap54xx_l4_per_hwmod
,
1757 .slave
= &omap54xx_gpio8_hwmod
,
1758 .clk
= "l4_root_clk_div",
1759 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1762 /* l4_per -> i2c1 */
1763 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1
= {
1764 .master
= &omap54xx_l4_per_hwmod
,
1765 .slave
= &omap54xx_i2c1_hwmod
,
1766 .clk
= "l4_root_clk_div",
1767 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1770 /* l4_per -> i2c2 */
1771 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2
= {
1772 .master
= &omap54xx_l4_per_hwmod
,
1773 .slave
= &omap54xx_i2c2_hwmod
,
1774 .clk
= "l4_root_clk_div",
1775 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1778 /* l4_per -> i2c3 */
1779 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3
= {
1780 .master
= &omap54xx_l4_per_hwmod
,
1781 .slave
= &omap54xx_i2c3_hwmod
,
1782 .clk
= "l4_root_clk_div",
1783 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1786 /* l4_per -> i2c4 */
1787 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4
= {
1788 .master
= &omap54xx_l4_per_hwmod
,
1789 .slave
= &omap54xx_i2c4_hwmod
,
1790 .clk
= "l4_root_clk_div",
1791 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1794 /* l4_per -> i2c5 */
1795 static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5
= {
1796 .master
= &omap54xx_l4_per_hwmod
,
1797 .slave
= &omap54xx_i2c5_hwmod
,
1798 .clk
= "l4_root_clk_div",
1799 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1802 /* l4_wkup -> kbd */
1803 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd
= {
1804 .master
= &omap54xx_l4_wkup_hwmod
,
1805 .slave
= &omap54xx_kbd_hwmod
,
1806 .clk
= "wkupaon_iclk_mux",
1807 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1810 /* l4_abe -> mcbsp1 */
1811 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1
= {
1812 .master
= &omap54xx_l4_abe_hwmod
,
1813 .slave
= &omap54xx_mcbsp1_hwmod
,
1815 .user
= OCP_USER_MPU
,
1818 /* l4_abe -> mcbsp2 */
1819 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2
= {
1820 .master
= &omap54xx_l4_abe_hwmod
,
1821 .slave
= &omap54xx_mcbsp2_hwmod
,
1823 .user
= OCP_USER_MPU
,
1826 /* l4_abe -> mcbsp3 */
1827 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3
= {
1828 .master
= &omap54xx_l4_abe_hwmod
,
1829 .slave
= &omap54xx_mcbsp3_hwmod
,
1831 .user
= OCP_USER_MPU
,
1834 /* l4_abe -> mcpdm */
1835 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm
= {
1836 .master
= &omap54xx_l4_abe_hwmod
,
1837 .slave
= &omap54xx_mcpdm_hwmod
,
1839 .user
= OCP_USER_MPU
,
1842 /* l4_per -> mcspi1 */
1843 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1
= {
1844 .master
= &omap54xx_l4_per_hwmod
,
1845 .slave
= &omap54xx_mcspi1_hwmod
,
1846 .clk
= "l4_root_clk_div",
1847 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1850 /* l4_per -> mcspi2 */
1851 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2
= {
1852 .master
= &omap54xx_l4_per_hwmod
,
1853 .slave
= &omap54xx_mcspi2_hwmod
,
1854 .clk
= "l4_root_clk_div",
1855 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1858 /* l4_per -> mcspi3 */
1859 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3
= {
1860 .master
= &omap54xx_l4_per_hwmod
,
1861 .slave
= &omap54xx_mcspi3_hwmod
,
1862 .clk
= "l4_root_clk_div",
1863 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1866 /* l4_per -> mcspi4 */
1867 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4
= {
1868 .master
= &omap54xx_l4_per_hwmod
,
1869 .slave
= &omap54xx_mcspi4_hwmod
,
1870 .clk
= "l4_root_clk_div",
1871 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1874 /* l4_per -> mmc1 */
1875 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1
= {
1876 .master
= &omap54xx_l4_per_hwmod
,
1877 .slave
= &omap54xx_mmc1_hwmod
,
1878 .clk
= "l3_iclk_div",
1879 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1882 /* l4_per -> mmc2 */
1883 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2
= {
1884 .master
= &omap54xx_l4_per_hwmod
,
1885 .slave
= &omap54xx_mmc2_hwmod
,
1886 .clk
= "l3_iclk_div",
1887 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1890 /* l4_per -> mmc3 */
1891 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3
= {
1892 .master
= &omap54xx_l4_per_hwmod
,
1893 .slave
= &omap54xx_mmc3_hwmod
,
1894 .clk
= "l4_root_clk_div",
1895 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1898 /* l4_per -> mmc4 */
1899 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4
= {
1900 .master
= &omap54xx_l4_per_hwmod
,
1901 .slave
= &omap54xx_mmc4_hwmod
,
1902 .clk
= "l4_root_clk_div",
1903 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1906 /* l4_per -> mmc5 */
1907 static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5
= {
1908 .master
= &omap54xx_l4_per_hwmod
,
1909 .slave
= &omap54xx_mmc5_hwmod
,
1910 .clk
= "l4_root_clk_div",
1911 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1915 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu
= {
1916 .master
= &omap54xx_l4_cfg_hwmod
,
1917 .slave
= &omap54xx_mpu_hwmod
,
1918 .clk
= "l4_root_clk_div",
1919 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1922 /* l4_wkup -> timer1 */
1923 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1
= {
1924 .master
= &omap54xx_l4_wkup_hwmod
,
1925 .slave
= &omap54xx_timer1_hwmod
,
1926 .clk
= "wkupaon_iclk_mux",
1927 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1930 /* l4_per -> timer2 */
1931 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2
= {
1932 .master
= &omap54xx_l4_per_hwmod
,
1933 .slave
= &omap54xx_timer2_hwmod
,
1934 .clk
= "l4_root_clk_div",
1935 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1938 /* l4_per -> timer3 */
1939 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3
= {
1940 .master
= &omap54xx_l4_per_hwmod
,
1941 .slave
= &omap54xx_timer3_hwmod
,
1942 .clk
= "l4_root_clk_div",
1943 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1946 /* l4_per -> timer4 */
1947 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4
= {
1948 .master
= &omap54xx_l4_per_hwmod
,
1949 .slave
= &omap54xx_timer4_hwmod
,
1950 .clk
= "l4_root_clk_div",
1951 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1954 /* l4_abe -> timer5 */
1955 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5
= {
1956 .master
= &omap54xx_l4_abe_hwmod
,
1957 .slave
= &omap54xx_timer5_hwmod
,
1959 .user
= OCP_USER_MPU
,
1962 /* l4_abe -> timer6 */
1963 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6
= {
1964 .master
= &omap54xx_l4_abe_hwmod
,
1965 .slave
= &omap54xx_timer6_hwmod
,
1967 .user
= OCP_USER_MPU
,
1970 /* l4_abe -> timer7 */
1971 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7
= {
1972 .master
= &omap54xx_l4_abe_hwmod
,
1973 .slave
= &omap54xx_timer7_hwmod
,
1975 .user
= OCP_USER_MPU
,
1978 /* l4_abe -> timer8 */
1979 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8
= {
1980 .master
= &omap54xx_l4_abe_hwmod
,
1981 .slave
= &omap54xx_timer8_hwmod
,
1983 .user
= OCP_USER_MPU
,
1986 /* l4_per -> timer9 */
1987 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9
= {
1988 .master
= &omap54xx_l4_per_hwmod
,
1989 .slave
= &omap54xx_timer9_hwmod
,
1990 .clk
= "l4_root_clk_div",
1991 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
1994 /* l4_per -> timer10 */
1995 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10
= {
1996 .master
= &omap54xx_l4_per_hwmod
,
1997 .slave
= &omap54xx_timer10_hwmod
,
1998 .clk
= "l4_root_clk_div",
1999 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2002 /* l4_per -> timer11 */
2003 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11
= {
2004 .master
= &omap54xx_l4_per_hwmod
,
2005 .slave
= &omap54xx_timer11_hwmod
,
2006 .clk
= "l4_root_clk_div",
2007 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2010 /* l4_per -> uart1 */
2011 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1
= {
2012 .master
= &omap54xx_l4_per_hwmod
,
2013 .slave
= &omap54xx_uart1_hwmod
,
2014 .clk
= "l4_root_clk_div",
2015 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2018 /* l4_per -> uart2 */
2019 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2
= {
2020 .master
= &omap54xx_l4_per_hwmod
,
2021 .slave
= &omap54xx_uart2_hwmod
,
2022 .clk
= "l4_root_clk_div",
2023 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2026 /* l4_per -> uart3 */
2027 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3
= {
2028 .master
= &omap54xx_l4_per_hwmod
,
2029 .slave
= &omap54xx_uart3_hwmod
,
2030 .clk
= "l4_root_clk_div",
2031 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2034 /* l4_per -> uart4 */
2035 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4
= {
2036 .master
= &omap54xx_l4_per_hwmod
,
2037 .slave
= &omap54xx_uart4_hwmod
,
2038 .clk
= "l4_root_clk_div",
2039 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2042 /* l4_per -> uart5 */
2043 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5
= {
2044 .master
= &omap54xx_l4_per_hwmod
,
2045 .slave
= &omap54xx_uart5_hwmod
,
2046 .clk
= "l4_root_clk_div",
2047 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2050 /* l4_per -> uart6 */
2051 static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6
= {
2052 .master
= &omap54xx_l4_per_hwmod
,
2053 .slave
= &omap54xx_uart6_hwmod
,
2054 .clk
= "l4_root_clk_div",
2055 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2058 /* l4_cfg -> usb_otg_ss */
2059 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss
= {
2060 .master
= &omap54xx_l4_cfg_hwmod
,
2061 .slave
= &omap54xx_usb_otg_ss_hwmod
,
2062 .clk
= "dpll_core_h13x2_ck",
2063 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2066 /* l4_wkup -> wd_timer2 */
2067 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2
= {
2068 .master
= &omap54xx_l4_wkup_hwmod
,
2069 .slave
= &omap54xx_wd_timer2_hwmod
,
2070 .clk
= "wkupaon_iclk_mux",
2071 .user
= OCP_USER_MPU
| OCP_USER_SDMA
,
2074 static struct omap_hwmod_ocp_if
*omap54xx_hwmod_ocp_ifs
[] __initdata
= {
2075 &omap54xx_l3_main_1__dmm
,
2076 &omap54xx_l3_main_3__l3_instr
,
2077 &omap54xx_l3_main_2__l3_main_1
,
2078 &omap54xx_l4_cfg__l3_main_1
,
2079 &omap54xx_mpu__l3_main_1
,
2080 &omap54xx_l3_main_1__l3_main_2
,
2081 &omap54xx_l4_cfg__l3_main_2
,
2082 &omap54xx_l3_main_1__l3_main_3
,
2083 &omap54xx_l3_main_2__l3_main_3
,
2084 &omap54xx_l4_cfg__l3_main_3
,
2085 &omap54xx_l3_main_1__l4_abe
,
2086 &omap54xx_mpu__l4_abe
,
2087 &omap54xx_l3_main_1__l4_cfg
,
2088 &omap54xx_l3_main_2__l4_per
,
2089 &omap54xx_l3_main_1__l4_wkup
,
2090 &omap54xx_mpu__mpu_private
,
2091 &omap54xx_l4_wkup__counter_32k
,
2092 &omap54xx_l4_cfg__dma_system
,
2093 &omap54xx_l4_abe__dmic
,
2094 &omap54xx_mpu__emif1
,
2095 &omap54xx_mpu__emif2
,
2096 &omap54xx_l4_wkup__gpio1
,
2097 &omap54xx_l4_per__gpio2
,
2098 &omap54xx_l4_per__gpio3
,
2099 &omap54xx_l4_per__gpio4
,
2100 &omap54xx_l4_per__gpio5
,
2101 &omap54xx_l4_per__gpio6
,
2102 &omap54xx_l4_per__gpio7
,
2103 &omap54xx_l4_per__gpio8
,
2104 &omap54xx_l4_per__i2c1
,
2105 &omap54xx_l4_per__i2c2
,
2106 &omap54xx_l4_per__i2c3
,
2107 &omap54xx_l4_per__i2c4
,
2108 &omap54xx_l4_per__i2c5
,
2109 &omap54xx_l4_wkup__kbd
,
2110 &omap54xx_l4_abe__mcbsp1
,
2111 &omap54xx_l4_abe__mcbsp2
,
2112 &omap54xx_l4_abe__mcbsp3
,
2113 &omap54xx_l4_abe__mcpdm
,
2114 &omap54xx_l4_per__mcspi1
,
2115 &omap54xx_l4_per__mcspi2
,
2116 &omap54xx_l4_per__mcspi3
,
2117 &omap54xx_l4_per__mcspi4
,
2118 &omap54xx_l4_per__mmc1
,
2119 &omap54xx_l4_per__mmc2
,
2120 &omap54xx_l4_per__mmc3
,
2121 &omap54xx_l4_per__mmc4
,
2122 &omap54xx_l4_per__mmc5
,
2123 &omap54xx_l4_cfg__mpu
,
2124 &omap54xx_l4_wkup__timer1
,
2125 &omap54xx_l4_per__timer2
,
2126 &omap54xx_l4_per__timer3
,
2127 &omap54xx_l4_per__timer4
,
2128 &omap54xx_l4_abe__timer5
,
2129 &omap54xx_l4_abe__timer6
,
2130 &omap54xx_l4_abe__timer7
,
2131 &omap54xx_l4_abe__timer8
,
2132 &omap54xx_l4_per__timer9
,
2133 &omap54xx_l4_per__timer10
,
2134 &omap54xx_l4_per__timer11
,
2135 &omap54xx_l4_per__uart1
,
2136 &omap54xx_l4_per__uart2
,
2137 &omap54xx_l4_per__uart3
,
2138 &omap54xx_l4_per__uart4
,
2139 &omap54xx_l4_per__uart5
,
2140 &omap54xx_l4_per__uart6
,
2141 &omap54xx_l4_cfg__usb_otg_ss
,
2142 &omap54xx_l4_wkup__wd_timer2
,
2146 int __init
omap54xx_hwmod_init(void)
2149 return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs
);