arch/arm/mach-omap2/prm44xx.c

   1 /*
   2  * OMAP4 PRM module functions
   3  *
   4  * Copyright (C) 2011-2012 Texas Instruments, Inc.
   5  * Copyright (C) 2010 Nokia Corporation
   6  * Benoît Cousson
   7  * Paul Walmsley
   8  * Rajendra Nayak <rnayak@ti.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/delay.h>
  17 #include <linux/errno.h>
  18 #include <linux/err.h>
  19 #include <linux/io.h>
  20 #include <linux/of_irq.h>
  21
  22
  23 #include "soc.h"
  24 #include "iomap.h"
  25 #include "common.h"
  26 #include "vp.h"
  27 #include "prm44xx.h"
  28 #include "prm-regbits-44xx.h"
  29 #include "prcm44xx.h"
  30 #include "prminst44xx.h"
  31 #include "powerdomain.h"
  32
  33 /* Static data */
  34
  35 static const struct omap_prcm_irq omap4_prcm_irqs[] = {
  36         OMAP_PRCM_IRQ("io",     9,      1),
  37 };
  38
  39 static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
  40         .ack                    = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
  41         .mask                   = OMAP4_PRM_IRQENABLE_MPU_OFFSET,
  42         .nr_regs                = 2,
  43         .irqs                   = omap4_prcm_irqs,
  44         .nr_irqs                = ARRAY_SIZE(omap4_prcm_irqs),
  45         .irq                    = 11 + OMAP44XX_IRQ_GIC_START,
  46         .read_pending_irqs      = &omap44xx_prm_read_pending_irqs,
  47         .ocp_barrier            = &omap44xx_prm_ocp_barrier,
  48         .save_and_clear_irqen   = &omap44xx_prm_save_and_clear_irqen,
  49         .restore_irqen          = &omap44xx_prm_restore_irqen,
  50         .reconfigure_io_chain   = &omap44xx_prm_reconfigure_io_chain,
  51 };
  52
  53 /*
  54  * omap44xx_prm_reset_src_map - map from bits in the PRM_RSTST
  55  *   hardware register (which are specific to OMAP44xx SoCs) to reset
  56  *   source ID bit shifts (which is an OMAP SoC-independent
  57  *   enumeration)
  58  */
  59 static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
  60         { OMAP4430_GLOBAL_WARM_SW_RST_SHIFT,
  61           OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
  62         { OMAP4430_GLOBAL_COLD_RST_SHIFT,
  63           OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
  64         { OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT,
  65           OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
  66         { OMAP4430_MPU_WDT_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
  67         { OMAP4430_SECURE_WDT_RST_SHIFT, OMAP_SECU_WD_RST_SRC_ID_SHIFT },
  68         { OMAP4430_EXTERNAL_WARM_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },
  69         { OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT,
  70           OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT },
  71         { OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT,
  72           OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT },
  73         { OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT,
  74           OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT },
  75         { OMAP4430_ICEPICK_RST_SHIFT, OMAP_ICEPICK_RST_SRC_ID_SHIFT },
  76         { OMAP4430_C2C_RST_SHIFT, OMAP_C2C_RST_SRC_ID_SHIFT },
  77         { -1, -1 },
  78 };
  79
  80 /* PRM low-level functions */
  81
  82 /* Read a register in a CM/PRM instance in the PRM module */
  83 u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
  84 {
  85         return readl_relaxed(prm_base + inst + reg);
  86 }
  87
  88 /* Write into a register in a CM/PRM instance in the PRM module */
  89 void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
  90 {
  91         writel_relaxed(val, prm_base + inst + reg);
  92 }
  93
  94 /* Read-modify-write a register in a PRM module. Caller must lock */
  95 u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
  96 {
  97         u32 v;
  98
  99         v = omap4_prm_read_inst_reg(inst, reg);
 100         v &= ~mask;
 101         v |= bits;
 102         omap4_prm_write_inst_reg(v, inst, reg);
 103
 104         return v;
 105 }
 106
 107 /* PRM VP */
 108
 109 /*
 110  * struct omap4_vp - OMAP4 VP register access description.
 111  * @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP
 112  * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
 113  */
 114 struct omap4_vp {
 115         u32 irqstatus_mpu;
 116         u32 tranxdone_status;
 117 };
 118
 119 static struct omap4_vp omap4_vp[] = {
 120         [OMAP4_VP_VDD_MPU_ID] = {
 121                 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
 122                 .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
 123         },
 124         [OMAP4_VP_VDD_IVA_ID] = {
 125                 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
 126                 .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
 127         },
 128         [OMAP4_VP_VDD_CORE_ID] = {
 129                 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
 130                 .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
 131         },
 132 };
 133
 134 u32 omap4_prm_vp_check_txdone(u8 vp_id)
 135 {
 136         struct omap4_vp *vp = &omap4_vp[vp_id];
 137         u32 irqstatus;
 138
 139         irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
 140                                                 OMAP4430_PRM_OCP_SOCKET_INST,
 141                                                 vp->irqstatus_mpu);
 142         return irqstatus & vp->tranxdone_status;
 143 }
 144
 145 void omap4_prm_vp_clear_txdone(u8 vp_id)
 146 {
 147         struct omap4_vp *vp = &omap4_vp[vp_id];
 148
 149         omap4_prminst_write_inst_reg(vp->tranxdone_status,
 150                                      OMAP4430_PRM_PARTITION,
 151                                      OMAP4430_PRM_OCP_SOCKET_INST,
 152                                      vp->irqstatus_mpu);
 153 };
 154
 155 u32 omap4_prm_vcvp_read(u8 offset)
 156 {
 157         s32 inst = omap4_prmst_get_prm_dev_inst();
 158
 159         if (inst == PRM_INSTANCE_UNKNOWN)
 160                 return 0;
 161
 162         return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
 163                                            inst, offset);
 164 }
 165
 166 void omap4_prm_vcvp_write(u32 val, u8 offset)
 167 {
 168         s32 inst = omap4_prmst_get_prm_dev_inst();
 169
 170         if (inst == PRM_INSTANCE_UNKNOWN)
 171                 return;
 172
 173         omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION,
 174                                      inst, offset);
 175 }
 176
 177 u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
 178 {
 179         s32 inst = omap4_prmst_get_prm_dev_inst();
 180
 181         if (inst == PRM_INSTANCE_UNKNOWN)
 182                 return 0;
 183
 184         return omap4_prminst_rmw_inst_reg_bits(mask, bits,
 185                                                OMAP4430_PRM_PARTITION,
 186                                                inst,
 187                                                offset);
 188 }
 189
 190 static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs)
 191 {
 192         u32 mask, st;
 193
 194         /* XXX read mask from RAM? */
 195         mask = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
 196                                        irqen_offs);
 197         st = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, irqst_offs);
 198
 199         return mask & st;
 200 }
 201
 202 /**
 203  * omap44xx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
 204  * @events: ptr to two consecutive u32s, preallocated by caller
 205  *
 206  * Read PRM_IRQSTATUS_MPU* bits, AND'ed with the currently-enabled PRM
 207  * MPU IRQs, and store the result into the two u32s pointed to by @events.
 208  * No return value.
 209  */
 210 void omap44xx_prm_read_pending_irqs(unsigned long *events)
 211 {
 212         events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET,
 213                                           OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
 214
 215         events[1] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_2_OFFSET,
 216                                           OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
 217 }
 218
 219 /**
 220  * omap44xx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
 221  *
 222  * Force any buffered writes to the PRM IP block to complete.  Needed
 223  * by the PRM IRQ handler, which reads and writes directly to the IP
 224  * block, to avoid race conditions after acknowledging or clearing IRQ
 225  * bits.  No return value.
 226  */
 227 void omap44xx_prm_ocp_barrier(void)
 228 {
 229         omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
 230                                 OMAP4_REVISION_PRM_OFFSET);
 231 }
 232
 233 /**
 234  * omap44xx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU* regs
 235  * @saved_mask: ptr to a u32 array to save IRQENABLE bits
 236  *
 237  * Save the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers to
 238  * @saved_mask.  @saved_mask must be allocated by the caller.
 239  * Intended to be used in the PRM interrupt handler suspend callback.
 240  * The OCP barrier is needed to ensure the write to disable PRM
 241  * interrupts reaches the PRM before returning; otherwise, spurious
 242  * interrupts might occur.  No return value.
 243  */
 244 void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
 245 {
 246         saved_mask[0] =
 247                 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
 248                                         OMAP4_PRM_IRQSTATUS_MPU_OFFSET);
 249         saved_mask[1] =
 250                 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
 251                                         OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET);
 252
 253         omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST,
 254                                  OMAP4_PRM_IRQENABLE_MPU_OFFSET);
 255         omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST,
 256                                  OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
 257
 258         /* OCP barrier */
 259         omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
 260                                 OMAP4_REVISION_PRM_OFFSET);
 261 }
 262
 263 /**
 264  * omap44xx_prm_restore_irqen - set PRM_IRQENABLE_MPU* registers from args
 265  * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
 266  *
 267  * Restore the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers from
 268  * @saved_mask.  Intended to be used in the PRM interrupt handler resume
 269  * callback to restore values saved by omap44xx_prm_save_and_clear_irqen().
 270  * No OCP barrier should be needed here; any pending PRM interrupts will fire
 271  * once the writes reach the PRM.  No return value.
 272  */
 273 void omap44xx_prm_restore_irqen(u32 *saved_mask)
 274 {
 275         omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_OCP_SOCKET_INST,
 276                                  OMAP4_PRM_IRQENABLE_MPU_OFFSET);
 277         omap4_prm_write_inst_reg(saved_mask[1], OMAP4430_PRM_OCP_SOCKET_INST,
 278                                  OMAP4_PRM_IRQENABLE_MPU_2_OFFSET);
 279 }
 280
 281 /**
 282  * omap44xx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
 283  *
 284  * Clear any previously-latched I/O wakeup events and ensure that the
 285  * I/O wakeup gates are aligned with the current mux settings.  Works
 286  * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
 287  * deasserting WUCLKIN and waiting for WUCLKOUT to be deasserted.
 288  * No return value. XXX Are the final two steps necessary?
 289  */
 290 void omap44xx_prm_reconfigure_io_chain(void)
 291 {
 292         int i = 0;
 293         s32 inst = omap4_prmst_get_prm_dev_inst();
 294
 295         if (inst == PRM_INSTANCE_UNKNOWN)
 296                 return;
 297
 298         /* Trigger WUCLKIN enable */
 299         omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK,
 300                                     OMAP4430_WUCLK_CTRL_MASK,
 301                                     inst,
 302                                     OMAP4_PRM_IO_PMCTRL_OFFSET);
 303         omap_test_timeout(
 304                 (((omap4_prm_read_inst_reg(inst,
 305                                            OMAP4_PRM_IO_PMCTRL_OFFSET) &
 306                    OMAP4430_WUCLK_STATUS_MASK) >>
 307                   OMAP4430_WUCLK_STATUS_SHIFT) == 1),
 308                 MAX_IOPAD_LATCH_TIME, i);
 309         if (i == MAX_IOPAD_LATCH_TIME)
 310                 pr_warn("PRM: I/O chain clock line assertion timed out\n");
 311
 312         /* Trigger WUCLKIN disable */
 313         omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0,
 314                                     inst,
 315                                     OMAP4_PRM_IO_PMCTRL_OFFSET);
 316         omap_test_timeout(
 317                 (((omap4_prm_read_inst_reg(inst,
 318                                            OMAP4_PRM_IO_PMCTRL_OFFSET) &
 319                    OMAP4430_WUCLK_STATUS_MASK) >>
 320                   OMAP4430_WUCLK_STATUS_SHIFT) == 0),
 321                 MAX_IOPAD_LATCH_TIME, i);
 322         if (i == MAX_IOPAD_LATCH_TIME)
 323                 pr_warn("PRM: I/O chain clock line deassertion timed out\n");
 324
 325         return;
 326 }
 327
 328 /**
 329  * omap44xx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
 330  *
 331  * Activates the I/O wakeup event latches and allows events logged by
 332  * those latches to signal a wakeup event to the PRCM.  For I/O wakeups
 333  * to occur, WAKEUPENABLE bits must be set in the pad mux registers, and
 334  * omap44xx_prm_reconfigure_io_chain() must be called.  No return value.
 335  */
 336 static void __init omap44xx_prm_enable_io_wakeup(void)
 337 {
 338         s32 inst = omap4_prmst_get_prm_dev_inst();
 339
 340         if (inst == PRM_INSTANCE_UNKNOWN)
 341                 return;
 342
 343         omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
 344                                     OMAP4430_GLOBAL_WUEN_MASK,
 345                                     inst,
 346                                     OMAP4_PRM_IO_PMCTRL_OFFSET);
 347 }
 348
 349 /**
 350  * omap44xx_prm_read_reset_sources - return the last SoC reset source
 351  *
 352  * Return a u32 representing the last reset sources of the SoC.  The
 353  * returned reset source bits are standardized across OMAP SoCs.
 354  */
 355 static u32 omap44xx_prm_read_reset_sources(void)
 356 {
 357         struct prm_reset_src_map *p;
 358         u32 r = 0;
 359         u32 v;
 360         s32 inst = omap4_prmst_get_prm_dev_inst();
 361
 362         if (inst == PRM_INSTANCE_UNKNOWN)
 363                 return 0;
 364
 365
 366         v = omap4_prm_read_inst_reg(inst,
 367                                     OMAP4_RM_RSTST);
 368
 369         p = omap44xx_prm_reset_src_map;
 370         while (p->reg_shift >= 0 && p->std_shift >= 0) {
 371                 if (v & (1 << p->reg_shift))
 372                         r |= 1 << p->std_shift;
 373                 p++;
 374         }
 375
 376         return r;
 377 }
 378
 379 /**
 380  * omap44xx_prm_was_any_context_lost_old - was module hardware context lost?
 381  * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
 382  * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
 383  * @idx: CONTEXT register offset
 384  *
 385  * Return 1 if any bits were set in the *_CONTEXT_* register
 386  * identified by (@part, @inst, @idx), which means that some context
 387  * was lost for that module; otherwise, return 0.
 388  */
 389 static bool omap44xx_prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx)
 390 {
 391         return (omap4_prminst_read_inst_reg(part, inst, idx)) ? 1 : 0;
 392 }
 393
 394 /**
 395  * omap44xx_prm_clear_context_lost_flags_old - clear context loss flags
 396  * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
 397  * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
 398  * @idx: CONTEXT register offset
 399  *
 400  * Clear hardware context loss bits for the module identified by
 401  * (@part, @inst, @idx).  No return value.  XXX Writes to reserved bits;
 402  * is there a way to avoid this?
 403  */
 404 static void omap44xx_prm_clear_context_loss_flags_old(u8 part, s16 inst,
 405                                                       u16 idx)
 406 {
 407         omap4_prminst_write_inst_reg(0xffffffff, part, inst, idx);
 408 }
 409
 410 /* Powerdomain low-level functions */
 411
 412 static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
 413 {
 414         omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK,
 415                                         (pwrst << OMAP_POWERSTATE_SHIFT),
 416                                         pwrdm->prcm_partition,
 417                                         pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
 418         return 0;
 419 }
 420
 421 static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
 422 {
 423         u32 v;
 424
 425         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 426                                         OMAP4_PM_PWSTCTRL);
 427         v &= OMAP_POWERSTATE_MASK;
 428         v >>= OMAP_POWERSTATE_SHIFT;
 429
 430         return v;
 431 }
 432
 433 static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
 434 {
 435         u32 v;
 436
 437         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 438                                         OMAP4_PM_PWSTST);
 439         v &= OMAP_POWERSTATEST_MASK;
 440         v >>= OMAP_POWERSTATEST_SHIFT;
 441
 442         return v;
 443 }
 444
 445 static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
 446 {
 447         u32 v;
 448
 449         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 450                                         OMAP4_PM_PWSTST);
 451         v &= OMAP4430_LASTPOWERSTATEENTERED_MASK;
 452         v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;
 453
 454         return v;
 455 }
 456
 457 static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
 458 {
 459         omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
 460                                         (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
 461                                         pwrdm->prcm_partition,
 462                                         pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
 463         return 0;
 464 }
 465
 466 static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
 467 {
 468         omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
 469                                         OMAP4430_LASTPOWERSTATEENTERED_MASK,
 470                                         pwrdm->prcm_partition,
 471                                         pwrdm->prcm_offs, OMAP4_PM_PWSTST);
 472         return 0;
 473 }
 474
 475 static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
 476 {
 477         u32 v;
 478
 479         v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
 480         omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
 481                                         pwrdm->prcm_partition, pwrdm->prcm_offs,
 482                                         OMAP4_PM_PWSTCTRL);
 483
 484         return 0;
 485 }
 486
 487 static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
 488                                     u8 pwrst)
 489 {
 490         u32 m;
 491
 492         m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
 493
 494         omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
 495                                         pwrdm->prcm_partition, pwrdm->prcm_offs,
 496                                         OMAP4_PM_PWSTCTRL);
 497
 498         return 0;
 499 }
 500
 501 static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
 502                                      u8 pwrst)
 503 {
 504         u32 m;
 505
 506         m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
 507
 508         omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
 509                                         pwrdm->prcm_partition, pwrdm->prcm_offs,
 510                                         OMAP4_PM_PWSTCTRL);
 511
 512         return 0;
 513 }
 514
 515 static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
 516 {
 517         u32 v;
 518
 519         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 520                                         OMAP4_PM_PWSTST);
 521         v &= OMAP4430_LOGICSTATEST_MASK;
 522         v >>= OMAP4430_LOGICSTATEST_SHIFT;
 523
 524         return v;
 525 }
 526
 527 static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
 528 {
 529         u32 v;
 530
 531         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 532                                         OMAP4_PM_PWSTCTRL);
 533         v &= OMAP4430_LOGICRETSTATE_MASK;
 534         v >>= OMAP4430_LOGICRETSTATE_SHIFT;
 535
 536         return v;
 537 }
 538
 539 /**
 540  * omap4_pwrdm_read_prev_logic_pwrst - read the previous logic powerstate
 541  * @pwrdm: struct powerdomain * to read the state for
 542  *
 543  * Reads the previous logic powerstate for a powerdomain. This
 544  * function must determine the previous logic powerstate by first
 545  * checking the previous powerstate for the domain. If that was OFF,
 546  * then logic has been lost. If previous state was RETENTION, the
 547  * function reads the setting for the next retention logic state to
 548  * see the actual value.  In every other case, the logic is
 549  * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
 550  * depending whether the logic was retained or not.
 551  */
 552 static int omap4_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
 553 {
 554         int state;
 555
 556         state = omap4_pwrdm_read_prev_pwrst(pwrdm);
 557
 558         if (state == PWRDM_POWER_OFF)
 559                 return PWRDM_POWER_OFF;
 560
 561         if (state != PWRDM_POWER_RET)
 562                 return PWRDM_POWER_RET;
 563
 564         return omap4_pwrdm_read_logic_retst(pwrdm);
 565 }
 566
 567 static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
 568 {
 569         u32 m, v;
 570
 571         m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
 572
 573         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 574                                         OMAP4_PM_PWSTST);
 575         v &= m;
 576         v >>= __ffs(m);
 577
 578         return v;
 579 }
 580
 581 static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
 582 {
 583         u32 m, v;
 584
 585         m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
 586
 587         v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
 588                                         OMAP4_PM_PWSTCTRL);
 589         v &= m;
 590         v >>= __ffs(m);
 591
 592         return v;
 593 }
 594
 595 /**
 596  * omap4_pwrdm_read_prev_mem_pwrst - reads the previous memory powerstate
 597  * @pwrdm: struct powerdomain * to read mem powerstate for
 598  * @bank: memory bank index
 599  *
 600  * Reads the previous memory powerstate for a powerdomain. This
 601  * function must determine the previous memory powerstate by first
 602  * checking the previous powerstate for the domain. If that was OFF,
 603  * then logic has been lost. If previous state was RETENTION, the
 604  * function reads the setting for the next memory retention state to
 605  * see the actual value.  In every other case, the logic is
 606  * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
 607  * depending whether logic was retained or not.
 608  */
 609 static int omap4_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
 610 {
 611         int state;
 612
 613         state = omap4_pwrdm_read_prev_pwrst(pwrdm);
 614
 615         if (state == PWRDM_POWER_OFF)
 616                 return PWRDM_POWER_OFF;
 617
 618         if (state != PWRDM_POWER_RET)
 619                 return PWRDM_POWER_RET;
 620
 621         return omap4_pwrdm_read_mem_retst(pwrdm, bank);
 622 }
 623
 624 static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
 625 {
 626         u32 c = 0;
 627
 628         /*
 629          * REVISIT: pwrdm_wait_transition() may be better implemented
 630          * via a callback and a periodic timer check -- how long do we expect
 631          * powerdomain transitions to take?
 632          */
 633
 634         /* XXX Is this udelay() value meaningful? */
 635         while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition,
 636                                             pwrdm->prcm_offs,
 637                                             OMAP4_PM_PWSTST) &
 638                 OMAP_INTRANSITION_MASK) &&
 639                (c++ < PWRDM_TRANSITION_BAILOUT))
 640                 udelay(1);
 641
 642         if (c > PWRDM_TRANSITION_BAILOUT) {
 643                 pr_err("powerdomain: %s: waited too long to complete transition\n",
 644                        pwrdm->name);
 645                 return -EAGAIN;
 646         }
 647
 648         pr_debug("powerdomain: completed transition in %d loops\n", c);
 649
 650         return 0;
 651 }
 652
 653 static int omap4_check_vcvp(void)
 654 {
 655         if (prm_features & PRM_HAS_VOLTAGE)
 656                 return 1;
 657
 658         return 0;
 659 }
 660
 661 struct pwrdm_ops omap4_pwrdm_operations = {
 662         .pwrdm_set_next_pwrst   = omap4_pwrdm_set_next_pwrst,
 663         .pwrdm_read_next_pwrst  = omap4_pwrdm_read_next_pwrst,
 664         .pwrdm_read_pwrst       = omap4_pwrdm_read_pwrst,
 665         .pwrdm_read_prev_pwrst  = omap4_pwrdm_read_prev_pwrst,
 666         .pwrdm_set_lowpwrstchange       = omap4_pwrdm_set_lowpwrstchange,
 667         .pwrdm_clear_all_prev_pwrst     = omap4_pwrdm_clear_all_prev_pwrst,
 668         .pwrdm_set_logic_retst  = omap4_pwrdm_set_logic_retst,
 669         .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst,
 670         .pwrdm_read_prev_logic_pwrst    = omap4_pwrdm_read_prev_logic_pwrst,
 671         .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst,
 672         .pwrdm_read_mem_pwrst   = omap4_pwrdm_read_mem_pwrst,
 673         .pwrdm_read_mem_retst   = omap4_pwrdm_read_mem_retst,
 674         .pwrdm_read_prev_mem_pwrst      = omap4_pwrdm_read_prev_mem_pwrst,
 675         .pwrdm_set_mem_onst     = omap4_pwrdm_set_mem_onst,
 676         .pwrdm_set_mem_retst    = omap4_pwrdm_set_mem_retst,
 677         .pwrdm_wait_transition  = omap4_pwrdm_wait_transition,
 678         .pwrdm_has_voltdm       = omap4_check_vcvp,
 679 };
 680
 681 static int omap44xx_prm_late_init(void);
 682
 683 /*
 684  * XXX document
 685  */
 686 static struct prm_ll_data omap44xx_prm_ll_data = {
 687         .read_reset_sources = &omap44xx_prm_read_reset_sources,
 688         .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old,
 689         .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old,
 690         .late_init = &omap44xx_prm_late_init,
 691         .assert_hardreset       = omap4_prminst_assert_hardreset,
 692         .deassert_hardreset     = omap4_prminst_deassert_hardreset,
 693         .is_hardreset_asserted  = omap4_prminst_is_hardreset_asserted,
 694 };
 695
 696 int __init omap44xx_prm_init(void)
 697 {
 698         if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx())
 699                 prm_features |= PRM_HAS_IO_WAKEUP;
 700
 701         if (!soc_is_dra7xx())
 702                 prm_features |= PRM_HAS_VOLTAGE;
 703
 704         return prm_register(&omap44xx_prm_ll_data);
 705 }
 706
 707 static struct of_device_id omap_prm_dt_match_table[] = {
 708         { .compatible = "ti,omap4-prm" },
 709         { .compatible = "ti,omap5-prm" },
 710         { .compatible = "ti,dra7-prm" },
 711         { }
 712 };
 713
 714 static int omap44xx_prm_late_init(void)
 715 {
 716         struct device_node *np;
 717         int irq_num;
 718
 719         if (!(prm_features & PRM_HAS_IO_WAKEUP))
 720                 return 0;
 721
 722         /* OMAP4+ is DT only now */
 723         if (!of_have_populated_dt())
 724                 return 0;
 725
 726         np = of_find_matching_node(NULL, omap_prm_dt_match_table);
 727
 728         if (!np) {
 729                 /* Default loaded up with OMAP4 values */
 730                 if (!cpu_is_omap44xx())
 731                         return 0;
 732         } else {
 733                 irq_num = of_irq_get(np, 0);
 734                 /*
 735                  * Already have OMAP4 IRQ num. For all other platforms, we need
 736                  * IRQ numbers from DT
 737                  */
 738                 if (irq_num < 0 && !cpu_is_omap44xx()) {
 739                         if (irq_num == -EPROBE_DEFER)
 740                                 return irq_num;
 741
 742                         /* Have nothing to do */
 743                         return 0;
 744                 }
 745
 746                 /* Once OMAP4 DT is filled as well */
 747                 if (irq_num >= 0)
 748                         omap4_prcm_irq_setup.irq = irq_num;
 749         }
 750
 751         omap44xx_prm_enable_io_wakeup();
 752
 753         return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
 754 }
 755
 756 static void __exit omap44xx_prm_exit(void)
 757 {
 758         prm_unregister(&omap44xx_prm_ll_data);
 759 }
 760 __exitcall(omap44xx_prm_exit);