arch/arm/mach-omap2/sdrc.c

   1 /*
   2  * SMS/SDRC (SDRAM controller) common code for OMAP2/3
   3  *
   4  * Copyright (C) 2005, 2008 Texas Instruments Inc.
   5  * Copyright (C) 2005, 2008 Nokia Corporation
   6  *
   7  * Tony Lindgren <tony@atomide.com>
   8  * Paul Walmsley
   9  * Richard Woodruff <r-woodruff2@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15 #undef DEBUG
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/device.h>
  20 #include <linux/list.h>
  21 #include <linux/errno.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25
  26 #include <plat/common.h>
  27 #include <plat/clock.h>
  28 #include <plat/sram.h>
  29
  30 #include <plat/sdrc.h>
  31 #include "sdrc.h"
  32
  33 static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1;
  34
  35 void __iomem *omap2_sdrc_base;
  36 void __iomem *omap2_sms_base;
  37
  38 struct omap2_sms_regs {
  39         u32     sms_sysconfig;
  40 };
  41
  42 static struct omap2_sms_regs sms_context;
  43
  44 /* SDRC_POWER register bits */
  45 #define SDRC_POWER_EXTCLKDIS_SHIFT              3
  46 #define SDRC_POWER_PWDENA_SHIFT                 2
  47 #define SDRC_POWER_PAGEPOLICY_SHIFT             0
  48
  49 /**
  50  * omap2_sms_save_context - Save SMS registers
  51  *
  52  * Save SMS registers that need to be restored after off mode.
  53  */
  54 void omap2_sms_save_context(void)
  55 {
  56         sms_context.sms_sysconfig = sms_read_reg(SMS_SYSCONFIG);
  57 }
  58
  59 /**
  60  * omap2_sms_restore_context - Restore SMS registers
  61  *
  62  * Restore SMS registers that need to be Restored after off mode.
  63  */
  64 void omap2_sms_restore_context(void)
  65 {
  66         sms_write_reg(sms_context.sms_sysconfig, SMS_SYSCONFIG);
  67 }
  68
  69 /**
  70  * omap2_sdrc_get_params - return SDRC register values for a given clock rate
  71  * @r: SDRC clock rate (in Hz)
  72  * @sdrc_cs0: chip select 0 ram timings **
  73  * @sdrc_cs1: chip select 1 ram timings **
  74  *
  75  * Return pre-calculated values for the SDRC_ACTIM_CTRLA,
  76  *  SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01]
  77  *  structs,for a given SDRC clock rate 'r'.
  78  * These parameters control various timing delays in the SDRAM controller
  79  *  that are expressed in terms of the number of SDRC clock cycles to
  80  *  wait; hence the clock rate dependency.
  81  *
  82  * Supports 2 different timing parameters for both chip selects.
  83  *
  84  * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending.
  85  * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size
  86  *  as sdrc_init_params_cs_0.
  87  *
  88  * Fills in the struct omap_sdrc_params * for each chip select.
  89  * Returns 0 upon success or -1 upon failure.
  90  */
  91 int omap2_sdrc_get_params(unsigned long r,
  92                           struct omap_sdrc_params **sdrc_cs0,
  93                           struct omap_sdrc_params **sdrc_cs1)
  94 {
  95         struct omap_sdrc_params *sp0, *sp1;
  96
  97         if (!sdrc_init_params_cs0)
  98                 return -1;
  99
 100         sp0 = sdrc_init_params_cs0;
 101         sp1 = sdrc_init_params_cs1;
 102
 103         while (sp0->rate && sp0->rate != r) {
 104                 sp0++;
 105                 if (sdrc_init_params_cs1)
 106                         sp1++;
 107         }
 108
 109         if (!sp0->rate)
 110                 return -1;
 111
 112         *sdrc_cs0 = sp0;
 113         *sdrc_cs1 = sp1;
 114         return 0;
 115 }
 116
 117
 118 void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals)
 119 {
 120         /* Static mapping, never released */
 121         if (omap2_globals->sdrc) {
 122                 omap2_sdrc_base = ioremap(omap2_globals->sdrc, SZ_64K);
 123                 WARN_ON(!omap2_sdrc_base);
 124         }
 125         if (omap2_globals->sms) {
 126                 omap2_sms_base = ioremap(omap2_globals->sms, SZ_64K);
 127                 WARN_ON(!omap2_sms_base);
 128         }
 129 }
 130
 131 /**
 132  * omap2_sdrc_init - initialize SMS, SDRC devices on boot
 133  * @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params
 134  *  Support for 2 chip selects timings
 135  *
 136  * Turn on smart idle modes for SDRAM scheduler and controller.
 137  * Program a known-good configuration for the SDRC to deal with buggy
 138  * bootloaders.
 139  */
 140 void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
 141                             struct omap_sdrc_params *sdrc_cs1)
 142 {
 143         u32 l;
 144
 145         l = sms_read_reg(SMS_SYSCONFIG);
 146         l &= ~(0x3 << 3);
 147         l |= (0x2 << 3);
 148         sms_write_reg(l, SMS_SYSCONFIG);
 149
 150         l = sdrc_read_reg(SDRC_SYSCONFIG);
 151         l &= ~(0x3 << 3);
 152         l |= (0x2 << 3);
 153         sdrc_write_reg(l, SDRC_SYSCONFIG);
 154
 155         sdrc_init_params_cs0 = sdrc_cs0;
 156         sdrc_init_params_cs1 = sdrc_cs1;
 157
 158         /* XXX Enable SRFRONIDLEREQ here also? */
 159         /*
 160          * PWDENA should not be set due to 34xx erratum 1.150 - PWDENA
 161          * can cause random memory corruption
 162          */
 163         l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) |
 164                 (1 << SDRC_POWER_PAGEPOLICY_SHIFT);
 165         sdrc_write_reg(l, SDRC_POWER);
 166         omap2_sms_save_context();
 167 }
 168
 169 void omap2_sms_write_rot_control(u32 val, unsigned ctx)
 170 {
 171         sms_write_reg(val, SMS_ROT_CONTROL(ctx));
 172 }
 173
 174 void omap2_sms_write_rot_size(u32 val, unsigned ctx)
 175 {
 176         sms_write_reg(val, SMS_ROT_SIZE(ctx));
 177 }
 178
 179 void omap2_sms_write_rot_physical_ba(u32 val, unsigned ctx)
 180 {
 181         sms_write_reg(val, SMS_ROT_PHYSICAL_BA(ctx));
 182 }
 183