arch/arm/mach-orion/addr-map.c

   1 /*
   2  * arch/arm/mach-orion/addr-map.c
   3  *
   4  * Address map functions for Marvell Orion System On Chip
   5  *
   6  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
   7  *
   8  * This file is licensed under  the terms of the GNU General Public
   9  * License version 2. This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/mbus.h>
  16 #include <asm/hardware.h>
  17 #include "common.h"
  18
  19 /*
  20  * The Orion has fully programable address map. There's a separate address
  21  * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB,
  22  * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own
  23  * address decode windows that allow it to access any of the Orion resources.
  24  *
  25  * CPU address decoding --
  26  * Linux assumes that it is the boot loader that already setup the access to
  27  * DDR and internal registers.
  28  * Setup access to PCI and PCI-E IO/MEM space is issued by core.c.
  29  * Setup access to various devices located on the device bus interface (e.g.
  30  * flashes, RTC, etc) should be issued by machine-setup.c according to
  31  * specific board population (by using orion_setup_cpu_win()).
  32  *
  33  * Non-CPU Masters address decoding --
  34  * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
  35  * banks only (the typical use case).
  36  * Setup access for each master to DDR is issued by common.c.
  37  *
  38  * Note: although orion_setbits() and orion_clrbits() are not atomic
  39  * no locking is necessary here since code in this file is only called
  40  * at boot time when there is no concurrency issues.
  41  */
  42
  43 /*
  44  * Generic Address Decode Windows bit settings
  45  */
  46 #define TARGET_DDR              0
  47 #define TARGET_PCI              3
  48 #define TARGET_PCIE             4
  49 #define TARGET_DEV_BUS          1
  50 #define ATTR_DDR_CS(n)          (((n) ==0) ? 0xe :      \
  51                                 ((n) == 1) ? 0xd :      \
  52                                 ((n) == 2) ? 0xb :      \
  53                                 ((n) == 3) ? 0x7 : 0xf)
  54 #define ATTR_PCIE_MEM           0x59
  55 #define ATTR_PCIE_IO            0x51
  56 #define ATTR_PCI_MEM            0x59
  57 #define ATTR_PCI_IO             0x51
  58 #define ATTR_DEV_CS0            0x1e
  59 #define ATTR_DEV_CS1            0x1d
  60 #define ATTR_DEV_CS2            0x1b
  61 #define ATTR_DEV_BOOT           0xf
  62 #define WIN_EN                  1
  63
  64 /*
  65  * Helpers to get DDR banks info
  66  */
  67 #define DDR_BASE_CS(n)          ORION_DDR_REG(0x1500 + ((n) * 8))
  68 #define DDR_SIZE_CS(n)          ORION_DDR_REG(0x1504 + ((n) * 8))
  69 #define DDR_MAX_CS              4
  70 #define DDR_REG_TO_SIZE(reg)    (((reg) | 0xffffff) + 1)
  71 #define DDR_REG_TO_BASE(reg)    ((reg) & 0xff000000)
  72 #define DDR_BANK_EN             1
  73
  74 /*
  75  * CPU Address Decode Windows registers
  76  */
  77 #define CPU_WIN_CTRL(n)         ORION_BRIDGE_REG(0x000 | ((n) << 4))
  78 #define CPU_WIN_BASE(n)         ORION_BRIDGE_REG(0x004 | ((n) << 4))
  79 #define CPU_WIN_REMAP_LO(n)     ORION_BRIDGE_REG(0x008 | ((n) << 4))
  80 #define CPU_WIN_REMAP_HI(n)     ORION_BRIDGE_REG(0x00c | ((n) << 4))
  81 #define CPU_MAX_WIN             8
  82
  83 /*
  84  * Use this CPU address decode windows allocation
  85  */
  86 #define CPU_WIN_PCIE_IO         0
  87 #define CPU_WIN_PCI_IO          1
  88 #define CPU_WIN_PCIE_MEM        2
  89 #define CPU_WIN_PCI_MEM         3
  90 #define CPU_WIN_DEV_BOOT        4
  91 #define CPU_WIN_DEV_CS0         5
  92 #define CPU_WIN_DEV_CS1         6
  93 #define CPU_WIN_DEV_CS2         7
  94
  95 /*
  96  * Gigabit Ethernet Address Decode Windows registers
  97  */
  98 #define ETH_WIN_BASE(win)       ORION_ETH_REG(0x200 + ((win) * 8))
  99 #define ETH_WIN_SIZE(win)       ORION_ETH_REG(0x204 + ((win) * 8))
 100 #define ETH_WIN_REMAP(win)      ORION_ETH_REG(0x280 + ((win) * 4))
 101 #define ETH_WIN_EN              ORION_ETH_REG(0x290)
 102 #define ETH_WIN_PROT            ORION_ETH_REG(0x294)
 103 #define ETH_MAX_WIN             6
 104 #define ETH_MAX_REMAP_WIN       4
 105
 106
 107 struct mbus_dram_target_info orion_mbus_dram_info;
 108
 109 static int __init orion_cpu_win_can_remap(u32 win)
 110 {
 111         u32 dev, rev;
 112
 113         orion_pcie_id(&dev, &rev);
 114         if ((dev == MV88F5281_DEV_ID && win < 4)
 115             || (dev == MV88F5182_DEV_ID && win < 2)
 116             || (dev == MV88F5181_DEV_ID && win < 2))
 117                 return 1;
 118
 119         return 0;
 120 }
 121
 122 void __init orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap)
 123 {
 124         u32 win, attr, ctrl;
 125
 126         switch (target) {
 127         case ORION_PCIE_IO:
 128                 target = TARGET_PCIE;
 129                 attr = ATTR_PCIE_IO;
 130                 win = CPU_WIN_PCIE_IO;
 131                 break;
 132         case ORION_PCI_IO:
 133                 target = TARGET_PCI;
 134                 attr = ATTR_PCI_IO;
 135                 win = CPU_WIN_PCI_IO;
 136                 break;
 137         case ORION_PCIE_MEM:
 138                 target = TARGET_PCIE;
 139                 attr = ATTR_PCIE_MEM;
 140                 win = CPU_WIN_PCIE_MEM;
 141                 break;
 142         case ORION_PCI_MEM:
 143                 target = TARGET_PCI;
 144                 attr = ATTR_PCI_MEM;
 145                 win = CPU_WIN_PCI_MEM;
 146                 break;
 147         case ORION_DEV_BOOT:
 148                 target = TARGET_DEV_BUS;
 149                 attr = ATTR_DEV_BOOT;
 150                 win = CPU_WIN_DEV_BOOT;
 151                 break;
 152         case ORION_DEV0:
 153                 target = TARGET_DEV_BUS;
 154                 attr = ATTR_DEV_CS0;
 155                 win = CPU_WIN_DEV_CS0;
 156                 break;
 157         case ORION_DEV1:
 158                 target = TARGET_DEV_BUS;
 159                 attr = ATTR_DEV_CS1;
 160                 win = CPU_WIN_DEV_CS1;
 161                 break;
 162         case ORION_DEV2:
 163                 target = TARGET_DEV_BUS;
 164                 attr = ATTR_DEV_CS2;
 165                 win = CPU_WIN_DEV_CS2;
 166                 break;
 167         case ORION_DDR:
 168         case ORION_REGS:
 169                 /*
 170                  * Must be mapped by bootloader.
 171                  */
 172         default:
 173                 target = attr = win = -1;
 174                 BUG();
 175         }
 176
 177         base &= 0xffff0000;
 178         ctrl = (((size - 1) & 0xffff0000) | (attr << 8) |
 179                 (target << 4) | WIN_EN);
 180
 181         orion_write(CPU_WIN_BASE(win), base);
 182         orion_write(CPU_WIN_CTRL(win), ctrl);
 183
 184         if (orion_cpu_win_can_remap(win)) {
 185                 if (remap >= 0) {
 186                         orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000);
 187                         orion_write(CPU_WIN_REMAP_HI(win), 0);
 188                 } else {
 189                         orion_write(CPU_WIN_REMAP_LO(win), base);
 190                         orion_write(CPU_WIN_REMAP_HI(win), 0);
 191                 }
 192         }
 193 }
 194
 195 void __init orion_setup_cpu_wins(void)
 196 {
 197         int i;
 198         int cs;
 199
 200         /*
 201          * First, disable and clear windows
 202          */
 203         for (i = 0; i < CPU_MAX_WIN; i++) {
 204                 orion_write(CPU_WIN_BASE(i), 0);
 205                 orion_write(CPU_WIN_CTRL(i), 0);
 206                 if (orion_cpu_win_can_remap(i)) {
 207                         orion_write(CPU_WIN_REMAP_LO(i), 0);
 208                         orion_write(CPU_WIN_REMAP_HI(i), 0);
 209                 }
 210         }
 211
 212         /*
 213          * Setup windows for PCI+PCIe IO+MEM space.
 214          */
 215         orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_PHYS_BASE,
 216                                 ORION_PCIE_IO_SIZE, ORION_PCIE_IO_BUS_BASE);
 217         orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_PHYS_BASE,
 218                                 ORION_PCI_IO_SIZE, ORION_PCI_IO_BUS_BASE);
 219         orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_PHYS_BASE,
 220                                 ORION_PCIE_MEM_SIZE, -1);
 221         orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE,
 222                                 ORION_PCI_MEM_SIZE, -1);
 223
 224         /*
 225          * Setup MBUS dram target info.
 226          */
 227         orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
 228
 229         for (i = 0, cs = 0; i < 4; i++) {
 230                 u32 base = readl(DDR_BASE_CS(i));
 231                 u32 size = readl(DDR_SIZE_CS(i));
 232
 233                 /*
 234                  * Chip select enabled?
 235                  */
 236                 if (size & 1) {
 237                         struct mbus_dram_window *w;
 238
 239                         w = &orion_mbus_dram_info.cs[cs++];
 240                         w->cs_index = i;
 241                         w->mbus_attr = 0xf & ~(1 << i);
 242                         w->base = base & 0xff000000;
 243                         w->size = (size | 0x00ffffff) + 1;
 244                 }
 245         }
 246         orion_mbus_dram_info.num_cs = cs;
 247 }
 248
 249 void __init orion_setup_eth_wins(void)
 250 {
 251         int i;
 252
 253         /*
 254          * First, disable and clear windows
 255          */
 256         for (i = 0; i < ETH_MAX_WIN; i++) {
 257                 orion_write(ETH_WIN_BASE(i), 0);
 258                 orion_write(ETH_WIN_SIZE(i), 0);
 259                 orion_setbits(ETH_WIN_EN, 1 << i);
 260                 orion_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
 261                 if (i < ETH_MAX_REMAP_WIN)
 262                         orion_write(ETH_WIN_REMAP(i), 0);
 263         }
 264
 265         /*
 266          * Setup windows for DDR banks.
 267          */
 268         for (i = 0; i < DDR_MAX_CS; i++) {
 269                 u32 base, size;
 270                 size = orion_read(DDR_SIZE_CS(i));
 271                 base = orion_read(DDR_BASE_CS(i));
 272                 if (size & DDR_BANK_EN) {
 273                         base = DDR_REG_TO_BASE(base);
 274                         size = DDR_REG_TO_SIZE(size);
 275                         orion_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
 276                         orion_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
 277                                         (ATTR_DDR_CS(i) << 8) |
 278                                         TARGET_DDR);
 279                         orion_clrbits(ETH_WIN_EN, 1 << i);
 280                         orion_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
 281                 }
 282         }
 283 }