arch/arm/mach-orion/addr-map.c

   1 /*
   2  * arch/arm/mach-orion/addr-map.c
   3  *
   4  * Address map functions for Marvell Orion System On Chip
   5  *
   6  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
   7  *
   8  * This file is licensed under  the terms of the GNU General Public
   9  * License version 2. This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/mbus.h>
  16 #include <asm/hardware.h>
  17 #include "common.h"
  18
  19 /*
  20  * The Orion has fully programable address map. There's a separate address
  21  * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIE, USB,
  22  * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own
  23  * address decode windows that allow it to access any of the Orion resources.
  24  *
  25  * CPU address decoding --
  26  * Linux assumes that it is the boot loader that already setup the access to
  27  * DDR and internal registers.
  28  * Setup access to PCI and PCI-E IO/MEM space is issued by core.c.
  29  * Setup access to various devices located on the device bus interface (e.g.
  30  * flashes, RTC, etc) should be issued by machine-setup.c according to
  31  * specific board population (by using orion_setup_cpu_win()).
  32  *
  33  * Non-CPU Masters address decoding --
  34  * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
  35  * banks only (the typical use case).
  36  * Setup access for each master to DDR is issued by common.c.
  37  *
  38  * Note: although orion_setbits() and orion_clrbits() are not atomic
  39  * no locking is necessary here since code in this file is only called
  40  * at boot time when there is no concurrency issues.
  41  */
  42
  43 /*
  44  * Generic Address Decode Windows bit settings
  45  */
  46 #define TARGET_DDR              0
  47 #define TARGET_PCI              3
  48 #define TARGET_PCIE             4
  49 #define TARGET_DEV_BUS          1
  50 #define ATTR_DDR_CS(n)          (((n) ==0) ? 0xe :      \
  51                                 ((n) == 1) ? 0xd :      \
  52                                 ((n) == 2) ? 0xb :      \
  53                                 ((n) == 3) ? 0x7 : 0xf)
  54 #define ATTR_PCIE_MEM           0x59
  55 #define ATTR_PCIE_IO            0x51
  56 #define ATTR_PCI_MEM            0x59
  57 #define ATTR_PCI_IO             0x51
  58 #define ATTR_DEV_CS0            0x1e
  59 #define ATTR_DEV_CS1            0x1d
  60 #define ATTR_DEV_CS2            0x1b
  61 #define ATTR_DEV_BOOT           0xf
  62 #define WIN_EN                  1
  63
  64 /*
  65  * Helpers to get DDR banks info
  66  */
  67 #define DDR_BASE_CS(n)          ORION_DDR_REG(0x1500 + ((n) * 8))
  68 #define DDR_SIZE_CS(n)          ORION_DDR_REG(0x1504 + ((n) * 8))
  69 #define DDR_MAX_CS              4
  70 #define DDR_REG_TO_SIZE(reg)    (((reg) | 0xffffff) + 1)
  71 #define DDR_REG_TO_BASE(reg)    ((reg) & 0xff000000)
  72 #define DDR_BANK_EN             1
  73
  74 /*
  75  * CPU Address Decode Windows registers
  76  */
  77 #define CPU_WIN_CTRL(n)         ORION_BRIDGE_REG(0x000 | ((n) << 4))
  78 #define CPU_WIN_BASE(n)         ORION_BRIDGE_REG(0x004 | ((n) << 4))
  79 #define CPU_WIN_REMAP_LO(n)     ORION_BRIDGE_REG(0x008 | ((n) << 4))
  80 #define CPU_WIN_REMAP_HI(n)     ORION_BRIDGE_REG(0x00c | ((n) << 4))
  81 #define CPU_MAX_WIN             8
  82
  83 /*
  84  * Use this CPU address decode windows allocation
  85  */
  86 #define CPU_WIN_PCIE_IO         0
  87 #define CPU_WIN_PCI_IO          1
  88 #define CPU_WIN_PCIE_MEM        2
  89 #define CPU_WIN_PCI_MEM         3
  90 #define CPU_WIN_DEV_BOOT        4
  91 #define CPU_WIN_DEV_CS0         5
  92 #define CPU_WIN_DEV_CS1         6
  93 #define CPU_WIN_DEV_CS2         7
  94
  95 /*
  96  * Gigabit Ethernet Address Decode Windows registers
  97  */
  98 #define ETH_WIN_BASE(win)       ORION_ETH_REG(0x200 + ((win) * 8))
  99 #define ETH_WIN_SIZE(win)       ORION_ETH_REG(0x204 + ((win) * 8))
 100 #define ETH_WIN_REMAP(win)      ORION_ETH_REG(0x280 + ((win) * 4))
 101 #define ETH_WIN_EN              ORION_ETH_REG(0x290)
 102 #define ETH_WIN_PROT            ORION_ETH_REG(0x294)
 103 #define ETH_MAX_WIN             6
 104 #define ETH_MAX_REMAP_WIN       4
 105
 106 /*
 107  * SATA Address Decode Windows registers
 108  */
 109 #define SATA_WIN_CTRL(win)      ORION_SATA_REG(0x30 + ((win) * 0x10))
 110 #define SATA_WIN_BASE(win)      ORION_SATA_REG(0x34 + ((win) * 0x10))
 111 #define SATA_MAX_WIN            4
 112
 113
 114 struct mbus_dram_target_info orion_mbus_dram_info;
 115
 116 static int __init orion_cpu_win_can_remap(u32 win)
 117 {
 118         u32 dev, rev;
 119
 120         orion_pcie_id(&dev, &rev);
 121         if ((dev == MV88F5281_DEV_ID && win < 4)
 122             || (dev == MV88F5182_DEV_ID && win < 2)
 123             || (dev == MV88F5181_DEV_ID && win < 2))
 124                 return 1;
 125
 126         return 0;
 127 }
 128
 129 void __init orion_setup_cpu_win(enum orion_target target, u32 base, u32 size, int remap)
 130 {
 131         u32 win, attr, ctrl;
 132
 133         switch (target) {
 134         case ORION_PCIE_IO:
 135                 target = TARGET_PCIE;
 136                 attr = ATTR_PCIE_IO;
 137                 win = CPU_WIN_PCIE_IO;
 138                 break;
 139         case ORION_PCI_IO:
 140                 target = TARGET_PCI;
 141                 attr = ATTR_PCI_IO;
 142                 win = CPU_WIN_PCI_IO;
 143                 break;
 144         case ORION_PCIE_MEM:
 145                 target = TARGET_PCIE;
 146                 attr = ATTR_PCIE_MEM;
 147                 win = CPU_WIN_PCIE_MEM;
 148                 break;
 149         case ORION_PCI_MEM:
 150                 target = TARGET_PCI;
 151                 attr = ATTR_PCI_MEM;
 152                 win = CPU_WIN_PCI_MEM;
 153                 break;
 154         case ORION_DEV_BOOT:
 155                 target = TARGET_DEV_BUS;
 156                 attr = ATTR_DEV_BOOT;
 157                 win = CPU_WIN_DEV_BOOT;
 158                 break;
 159         case ORION_DEV0:
 160                 target = TARGET_DEV_BUS;
 161                 attr = ATTR_DEV_CS0;
 162                 win = CPU_WIN_DEV_CS0;
 163                 break;
 164         case ORION_DEV1:
 165                 target = TARGET_DEV_BUS;
 166                 attr = ATTR_DEV_CS1;
 167                 win = CPU_WIN_DEV_CS1;
 168                 break;
 169         case ORION_DEV2:
 170                 target = TARGET_DEV_BUS;
 171                 attr = ATTR_DEV_CS2;
 172                 win = CPU_WIN_DEV_CS2;
 173                 break;
 174         case ORION_DDR:
 175         case ORION_REGS:
 176                 /*
 177                  * Must be mapped by bootloader.
 178                  */
 179         default:
 180                 target = attr = win = -1;
 181                 BUG();
 182         }
 183
 184         base &= 0xffff0000;
 185         ctrl = (((size - 1) & 0xffff0000) | (attr << 8) |
 186                 (target << 4) | WIN_EN);
 187
 188         orion_write(CPU_WIN_BASE(win), base);
 189         orion_write(CPU_WIN_CTRL(win), ctrl);
 190
 191         if (orion_cpu_win_can_remap(win)) {
 192                 if (remap >= 0) {
 193                         orion_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000);
 194                         orion_write(CPU_WIN_REMAP_HI(win), 0);
 195                 } else {
 196                         orion_write(CPU_WIN_REMAP_LO(win), base);
 197                         orion_write(CPU_WIN_REMAP_HI(win), 0);
 198                 }
 199         }
 200 }
 201
 202 void __init orion_setup_cpu_wins(void)
 203 {
 204         int i;
 205         int cs;
 206
 207         /*
 208          * First, disable and clear windows
 209          */
 210         for (i = 0; i < CPU_MAX_WIN; i++) {
 211                 orion_write(CPU_WIN_BASE(i), 0);
 212                 orion_write(CPU_WIN_CTRL(i), 0);
 213                 if (orion_cpu_win_can_remap(i)) {
 214                         orion_write(CPU_WIN_REMAP_LO(i), 0);
 215                         orion_write(CPU_WIN_REMAP_HI(i), 0);
 216                 }
 217         }
 218
 219         /*
 220          * Setup windows for PCI+PCIe IO+MEM space.
 221          */
 222         orion_setup_cpu_win(ORION_PCIE_IO, ORION_PCIE_IO_PHYS_BASE,
 223                                 ORION_PCIE_IO_SIZE, ORION_PCIE_IO_BUS_BASE);
 224         orion_setup_cpu_win(ORION_PCI_IO, ORION_PCI_IO_PHYS_BASE,
 225                                 ORION_PCI_IO_SIZE, ORION_PCI_IO_BUS_BASE);
 226         orion_setup_cpu_win(ORION_PCIE_MEM, ORION_PCIE_MEM_PHYS_BASE,
 227                                 ORION_PCIE_MEM_SIZE, -1);
 228         orion_setup_cpu_win(ORION_PCI_MEM, ORION_PCI_MEM_PHYS_BASE,
 229                                 ORION_PCI_MEM_SIZE, -1);
 230
 231         /*
 232          * Setup MBUS dram target info.
 233          */
 234         orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
 235
 236         for (i = 0, cs = 0; i < 4; i++) {
 237                 u32 base = readl(DDR_BASE_CS(i));
 238                 u32 size = readl(DDR_SIZE_CS(i));
 239
 240                 /*
 241                  * Chip select enabled?
 242                  */
 243                 if (size & 1) {
 244                         struct mbus_dram_window *w;
 245
 246                         w = &orion_mbus_dram_info.cs[cs++];
 247                         w->cs_index = i;
 248                         w->mbus_attr = 0xf & ~(1 << i);
 249                         w->base = base & 0xff000000;
 250                         w->size = (size | 0x00ffffff) + 1;
 251                 }
 252         }
 253         orion_mbus_dram_info.num_cs = cs;
 254 }
 255
 256 void __init orion_setup_eth_wins(void)
 257 {
 258         int i;
 259
 260         /*
 261          * First, disable and clear windows
 262          */
 263         for (i = 0; i < ETH_MAX_WIN; i++) {
 264                 orion_write(ETH_WIN_BASE(i), 0);
 265                 orion_write(ETH_WIN_SIZE(i), 0);
 266                 orion_setbits(ETH_WIN_EN, 1 << i);
 267                 orion_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
 268                 if (i < ETH_MAX_REMAP_WIN)
 269                         orion_write(ETH_WIN_REMAP(i), 0);
 270         }
 271
 272         /*
 273          * Setup windows for DDR banks.
 274          */
 275         for (i = 0; i < DDR_MAX_CS; i++) {
 276                 u32 base, size;
 277                 size = orion_read(DDR_SIZE_CS(i));
 278                 base = orion_read(DDR_BASE_CS(i));
 279                 if (size & DDR_BANK_EN) {
 280                         base = DDR_REG_TO_BASE(base);
 281                         size = DDR_REG_TO_SIZE(size);
 282                         orion_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
 283                         orion_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
 284                                         (ATTR_DDR_CS(i) << 8) |
 285                                         TARGET_DDR);
 286                         orion_clrbits(ETH_WIN_EN, 1 << i);
 287                         orion_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
 288                 }
 289         }
 290 }
 291
 292 void __init orion_setup_sata_wins(void)
 293 {
 294         int i;
 295
 296         /*
 297          * First, disable and clear windows
 298          */
 299         for (i = 0; i < SATA_MAX_WIN; i++) {
 300                 orion_write(SATA_WIN_BASE(i), 0);
 301                 orion_write(SATA_WIN_CTRL(i), 0);
 302         }
 303
 304         /*
 305          * Setup windows for DDR banks.
 306          */
 307         for (i = 0; i < DDR_MAX_CS; i++) {
 308                 u32 base, size;
 309                 size = orion_read(DDR_SIZE_CS(i));
 310                 base = orion_read(DDR_BASE_CS(i));
 311                 if (size & DDR_BANK_EN) {
 312                         base = DDR_REG_TO_BASE(base);
 313                         size = DDR_REG_TO_SIZE(size);
 314                         orion_write(SATA_WIN_CTRL(i),
 315                                         ((size-1) & 0xffff0000) |
 316                                         (ATTR_DDR_CS(i) << 8) |
 317                                         (TARGET_DDR << 4) | WIN_EN);
 318                         orion_write(SATA_WIN_BASE(i),
 319                                         base & 0xffff0000);
 320                 }
 321         }
 322 }