arch/arm/mach-prima2/timer.c

   1 /*
   2  * System timer for CSR SiRFprimaII
   3  *
   4  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/clockchips.h>
  12 #include <linux/clocksource.h>
  13 #include <linux/bitops.h>
  14 #include <linux/irq.h>
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/slab.h>
  18 #include <linux/of.h>
  19 #include <linux/of_address.h>
  20 #include <mach/map.h>
  21 #include <asm/sched_clock.h>
  22 #include <asm/mach/time.h>
  23
  24 #include "common.h"
  25
  26 #define SIRFSOC_TIMER_COUNTER_LO        0x0000
  27 #define SIRFSOC_TIMER_COUNTER_HI        0x0004
  28 #define SIRFSOC_TIMER_MATCH_0           0x0008
  29 #define SIRFSOC_TIMER_MATCH_1           0x000C
  30 #define SIRFSOC_TIMER_MATCH_2           0x0010
  31 #define SIRFSOC_TIMER_MATCH_3           0x0014
  32 #define SIRFSOC_TIMER_MATCH_4           0x0018
  33 #define SIRFSOC_TIMER_MATCH_5           0x001C
  34 #define SIRFSOC_TIMER_STATUS            0x0020
  35 #define SIRFSOC_TIMER_INT_EN            0x0024
  36 #define SIRFSOC_TIMER_WATCHDOG_EN       0x0028
  37 #define SIRFSOC_TIMER_DIV               0x002C
  38 #define SIRFSOC_TIMER_LATCH             0x0030
  39 #define SIRFSOC_TIMER_LATCHED_LO        0x0034
  40 #define SIRFSOC_TIMER_LATCHED_HI        0x0038
  41
  42 #define SIRFSOC_TIMER_WDT_INDEX         5
  43
  44 #define SIRFSOC_TIMER_LATCH_BIT  BIT(0)
  45
  46 #define SIRFSOC_TIMER_REG_CNT 11
  47
  48 static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
  49         SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2,
  50         SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5,
  51         SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV,
  52         SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI,
  53 };
  54
  55 static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
  56
  57 static void __iomem *sirfsoc_timer_base;
  58 static void __init sirfsoc_of_timer_map(void);
  59
  60 /* timer0 interrupt handler */
  61 static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
  62 {
  63         struct clock_event_device *ce = dev_id;
  64
  65         WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) & BIT(0)));
  66
  67         /* clear timer0 interrupt */
  68         writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
  69
  70         ce->event_handler(ce);
  71
  72         return IRQ_HANDLED;
  73 }
  74
  75 /* read 64-bit timer counter */
  76 static cycle_t sirfsoc_timer_read(struct clocksource *cs)
  77 {
  78         u64 cycles;
  79
  80         /* latch the 64-bit timer counter */
  81         writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
  82         cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI);
  83         cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
  84
  85         return cycles;
  86 }
  87
  88 static int sirfsoc_timer_set_next_event(unsigned long delta,
  89         struct clock_event_device *ce)
  90 {
  91         unsigned long now, next;
  92
  93         writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
  94         now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
  95         next = now + delta;
  96         writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
  97         writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
  98         now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
  99
 100         return next - now > delta ? -ETIME : 0;
 101 }
 102
 103 static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
 104         struct clock_event_device *ce)
 105 {
 106         u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
 107         switch (mode) {
 108         case CLOCK_EVT_MODE_PERIODIC:
 109                 WARN_ON(1);
 110                 break;
 111         case CLOCK_EVT_MODE_ONESHOT:
 112                 writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
 113                 break;
 114         case CLOCK_EVT_MODE_SHUTDOWN:
 115                 writel_relaxed(val & ~BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
 116                 break;
 117         case CLOCK_EVT_MODE_UNUSED:
 118         case CLOCK_EVT_MODE_RESUME:
 119                 break;
 120         }
 121 }
 122
 123 static void sirfsoc_clocksource_suspend(struct clocksource *cs)
 124 {
 125         int i;
 126
 127         writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
 128
 129         for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
 130                 sirfsoc_timer_reg_val[i] = readl_relaxed(sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
 131 }
 132
 133 static void sirfsoc_clocksource_resume(struct clocksource *cs)
 134 {
 135         int i;
 136
 137         for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
 138                 writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
 139
 140         writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
 141         writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1], sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
 142 }
 143
 144 static struct clock_event_device sirfsoc_clockevent = {
 145         .name = "sirfsoc_clockevent",
 146         .rating = 200,
 147         .features = CLOCK_EVT_FEAT_ONESHOT,
 148         .set_mode = sirfsoc_timer_set_mode,
 149         .set_next_event = sirfsoc_timer_set_next_event,
 150 };
 151
 152 static struct clocksource sirfsoc_clocksource = {
 153         .name = "sirfsoc_clocksource",
 154         .rating = 200,
 155         .mask = CLOCKSOURCE_MASK(64),
 156         .flags = CLOCK_SOURCE_IS_CONTINUOUS,
 157         .read = sirfsoc_timer_read,
 158         .suspend = sirfsoc_clocksource_suspend,
 159         .resume = sirfsoc_clocksource_resume,
 160 };
 161
 162 static struct irqaction sirfsoc_timer_irq = {
 163         .name = "sirfsoc_timer0",
 164         .flags = IRQF_TIMER,
 165         .irq = 0,
 166         .handler = sirfsoc_timer_interrupt,
 167         .dev_id = &sirfsoc_clockevent,
 168 };
 169
 170 /* Overwrite weak default sched_clock with more precise one */
 171 static u32 notrace sirfsoc_read_sched_clock(void)
 172 {
 173         return (u32)(sirfsoc_timer_read(NULL) & 0xffffffff);
 174 }
 175
 176 static void __init sirfsoc_clockevent_init(void)
 177 {
 178         clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60);
 179
 180         sirfsoc_clockevent.max_delta_ns =
 181                 clockevent_delta2ns(-2, &sirfsoc_clockevent);
 182         sirfsoc_clockevent.min_delta_ns =
 183                 clockevent_delta2ns(2, &sirfsoc_clockevent);
 184
 185         sirfsoc_clockevent.cpumask = cpumask_of(0);
 186         clockevents_register_device(&sirfsoc_clockevent);
 187 }
 188
 189 /* initialize the kernel jiffy timer source */
 190 static void __init sirfsoc_timer_init(void)
 191 {
 192         unsigned long rate;
 193         struct clk *clk;
 194
 195         /* initialize clocking early, we want to set the OS timer */
 196         sirfsoc_of_clk_init();
 197
 198         /* timer's input clock is io clock */
 199         clk = clk_get_sys("io", NULL);
 200
 201         BUG_ON(IS_ERR(clk));
 202
 203         rate = clk_get_rate(clk);
 204
 205         BUG_ON(rate < CLOCK_TICK_RATE);
 206         BUG_ON(rate % CLOCK_TICK_RATE);
 207
 208         sirfsoc_of_timer_map();
 209
 210         writel_relaxed(rate / CLOCK_TICK_RATE / 2 - 1, sirfsoc_timer_base + SIRFSOC_TIMER_DIV);
 211         writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
 212         writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
 213         writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
 214
 215         BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
 216
 217         setup_sched_clock(sirfsoc_read_sched_clock, 32, CLOCK_TICK_RATE);
 218
 219         BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq));
 220
 221         sirfsoc_clockevent_init();
 222 }
 223
 224 static struct of_device_id timer_ids[] = {
 225         { .compatible = "sirf,prima2-tick" },
 226         {},
 227 };
 228
 229 static void __init sirfsoc_of_timer_map(void)
 230 {
 231         struct device_node *np;
 232         const unsigned int *intspec;
 233
 234         np = of_find_matching_node(NULL, timer_ids);
 235         if (!np)
 236                 panic("unable to find compatible timer node in dtb\n");
 237         sirfsoc_timer_base = of_iomap(np, 0);
 238         if (!sirfsoc_timer_base)
 239                 panic("unable to map timer cpu registers\n");
 240
 241         /* Get the interrupts property */
 242         intspec = of_get_property(np, "interrupts", NULL);
 243         BUG_ON(!intspec);
 244         sirfsoc_timer_irq.irq = be32_to_cpup(intspec);
 245
 246         of_node_put(np);
 247 }
 248
 249 struct sys_timer sirfsoc_timer = {
 250         .init = sirfsoc_timer_init,
 251 };