arch/arm/mach-pxa/pxa3xx.c

   1 /*
   2  * linux/arch/arm/mach-pxa/pxa3xx.c
   3  *
   4  * code specific to pxa3xx aka Monahans
   5  *
   6  * Copyright (C) 2006 Marvell International Ltd.
   7  *
   8  * 2007-09-02: eric miao <eric.miao@marvell.com>
   9  *             initial version
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/pm.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/irq.h>
  21 #include <linux/io.h>
  22 #include <linux/of.h>
  23 #include <linux/syscore_ops.h>
  24 #include <linux/i2c/pxa-i2c.h>
  25
  26 #include <asm/mach/map.h>
  27 #include <asm/suspend.h>
  28 #include <mach/hardware.h>
  29 #include <mach/pxa3xx-regs.h>
  30 #include <mach/reset.h>
  31 #include <linux/platform_data/usb-ohci-pxa27x.h>
  32 #include <mach/pm.h>
  33 #include <mach/dma.h>
  34 #include <mach/smemc.h>
  35 #include <mach/irqs.h>
  36
  37 #include "generic.h"
  38 #include "devices.h"
  39 #include "clock.h"
  40
  41 #define PECR_IE(n)      ((1 << ((n) * 2)) << 28)
  42 #define PECR_IS(n)      ((1 << ((n) * 2)) << 29)
  43
  44 extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
  45
  46 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
  47 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
  48 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
  49 static DEFINE_PXA3_CKEN(pxa3xx_i2c, I2C, 32842000, 0);
  50 static DEFINE_PXA3_CKEN(pxa3xx_udc, UDC, 48000000, 5);
  51 static DEFINE_PXA3_CKEN(pxa3xx_usbh, USBH, 48000000, 0);
  52 static DEFINE_PXA3_CKEN(pxa3xx_u2d, USB2, 48000000, 0);
  53 static DEFINE_PXA3_CKEN(pxa3xx_keypad, KEYPAD, 32768, 0);
  54 static DEFINE_PXA3_CKEN(pxa3xx_ssp1, SSP1, 13000000, 0);
  55 static DEFINE_PXA3_CKEN(pxa3xx_ssp2, SSP2, 13000000, 0);
  56 static DEFINE_PXA3_CKEN(pxa3xx_ssp3, SSP3, 13000000, 0);
  57 static DEFINE_PXA3_CKEN(pxa3xx_ssp4, SSP4, 13000000, 0);
  58 static DEFINE_PXA3_CKEN(pxa3xx_pwm0, PWM0, 13000000, 0);
  59 static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
  60 static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
  61 static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
  62 static DEFINE_PXA3_CKEN(pxa3xx_gpio, GPIO, 13000000, 0);
  63
  64 static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
  65 static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops);
  66 static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
  67 static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
  68 static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
  69
  70 static struct clk_lookup pxa3xx_clkregs[] = {
  71         INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
  72         /* Power I2C clock is always on */
  73         INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
  74         INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
  75         INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
  76         INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
  77         INIT_CLKREG(&clk_pxa3xx_ffuart, "pxa2xx-uart.0", NULL),
  78         INIT_CLKREG(&clk_pxa3xx_btuart, "pxa2xx-uart.1", NULL),
  79         INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-uart.2", NULL),
  80         INIT_CLKREG(&clk_pxa3xx_stuart, "pxa2xx-ir", "UARTCLK"),
  81         INIT_CLKREG(&clk_pxa3xx_i2c, "pxa2xx-i2c.0", NULL),
  82         INIT_CLKREG(&clk_pxa3xx_udc, "pxa27x-udc", NULL),
  83         INIT_CLKREG(&clk_pxa3xx_usbh, "pxa27x-ohci", NULL),
  84         INIT_CLKREG(&clk_pxa3xx_u2d, "pxa3xx-u2d", NULL),
  85         INIT_CLKREG(&clk_pxa3xx_keypad, "pxa27x-keypad", NULL),
  86         INIT_CLKREG(&clk_pxa3xx_ssp1, "pxa27x-ssp.0", NULL),
  87         INIT_CLKREG(&clk_pxa3xx_ssp2, "pxa27x-ssp.1", NULL),
  88         INIT_CLKREG(&clk_pxa3xx_ssp3, "pxa27x-ssp.2", NULL),
  89         INIT_CLKREG(&clk_pxa3xx_ssp4, "pxa27x-ssp.3", NULL),
  90         INIT_CLKREG(&clk_pxa3xx_pwm0, "pxa27x-pwm.0", NULL),
  91         INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
  92         INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
  93         INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
  94         INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
  95         INIT_CLKREG(&clk_pxa3xx_gpio, "pxa-gpio", NULL),
  96         INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
  97 };
  98
  99 #ifdef CONFIG_PM
 100
 101 #define ISRAM_START     0x5c000000
 102 #define ISRAM_SIZE      SZ_256K
 103
 104 static void __iomem *sram;
 105 static unsigned long wakeup_src;
 106
 107 /*
 108  * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
 109  * memory controller has to be reinitialised, so we place some code
 110  * in the SRAM to perform this function.
 111  *
 112  * We disable FIQs across the standby - otherwise, we might receive a
 113  * FIQ while the SDRAM is unavailable.
 114  */
 115 static void pxa3xx_cpu_standby(unsigned int pwrmode)
 116 {
 117         extern const char pm_enter_standby_start[], pm_enter_standby_end[];
 118         void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
 119
 120         memcpy_toio(sram + 0x8000, pm_enter_standby_start,
 121                     pm_enter_standby_end - pm_enter_standby_start);
 122
 123         AD2D0SR = ~0;
 124         AD2D1SR = ~0;
 125         AD2D0ER = wakeup_src;
 126         AD2D1ER = 0;
 127         ASCR = ASCR;
 128         ARSR = ARSR;
 129
 130         local_fiq_disable();
 131         fn(pwrmode);
 132         local_fiq_enable();
 133
 134         AD2D0ER = 0;
 135         AD2D1ER = 0;
 136 }
 137
 138 /*
 139  * NOTE:  currently, the OBM (OEM Boot Module) binary comes along with
 140  * PXA3xx development kits assumes that the resuming process continues
 141  * with the address stored within the first 4 bytes of SDRAM. The PSPR
 142  * register is used privately by BootROM and OBM, and _must_ be set to
 143  * 0x5c014000 for the moment.
 144  */
 145 static void pxa3xx_cpu_pm_suspend(void)
 146 {
 147         volatile unsigned long *p = (volatile void *)0xc0000000;
 148         unsigned long saved_data = *p;
 149 #ifndef CONFIG_IWMMXT
 150         u64 acc0;
 151
 152         asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
 153 #endif
 154
 155         extern int pxa3xx_finish_suspend(unsigned long);
 156
 157         /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
 158         CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
 159         CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
 160
 161         /* clear and setup wakeup source */
 162         AD3SR = ~0;
 163         AD3ER = wakeup_src;
 164         ASCR = ASCR;
 165         ARSR = ARSR;
 166
 167         PCFR |= (1u << 13);                     /* L1_DIS */
 168         PCFR &= ~((1u << 12) | (1u << 1));      /* L0_EN | SL_ROD */
 169
 170         PSPR = 0x5c014000;
 171
 172         /* overwrite with the resume address */
 173         *p = virt_to_phys(cpu_resume);
 174
 175         cpu_suspend(0, pxa3xx_finish_suspend);
 176
 177         *p = saved_data;
 178
 179         AD3ER = 0;
 180
 181 #ifndef CONFIG_IWMMXT
 182         asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
 183 #endif
 184 }
 185
 186 static void pxa3xx_cpu_pm_enter(suspend_state_t state)
 187 {
 188         /*
 189          * Don't sleep if no wakeup sources are defined
 190          */
 191         if (wakeup_src == 0) {
 192                 printk(KERN_ERR "Not suspending: no wakeup sources\n");
 193                 return;
 194         }
 195
 196         switch (state) {
 197         case PM_SUSPEND_STANDBY:
 198                 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
 199                 break;
 200
 201         case PM_SUSPEND_MEM:
 202                 pxa3xx_cpu_pm_suspend();
 203                 break;
 204         }
 205 }
 206
 207 static int pxa3xx_cpu_pm_valid(suspend_state_t state)
 208 {
 209         return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
 210 }
 211
 212 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
 213         .valid          = pxa3xx_cpu_pm_valid,
 214         .enter          = pxa3xx_cpu_pm_enter,
 215 };
 216
 217 static void __init pxa3xx_init_pm(void)
 218 {
 219         sram = ioremap(ISRAM_START, ISRAM_SIZE);
 220         if (!sram) {
 221                 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
 222                 return;
 223         }
 224
 225         /*
 226          * Since we copy wakeup code into the SRAM, we need to ensure
 227          * that it is preserved over the low power modes.  Note: bit 8
 228          * is undocumented in the developer manual, but must be set.
 229          */
 230         AD1R |= ADXR_L2 | ADXR_R0;
 231         AD2R |= ADXR_L2 | ADXR_R0;
 232         AD3R |= ADXR_L2 | ADXR_R0;
 233
 234         /*
 235          * Clear the resume enable registers.
 236          */
 237         AD1D0ER = 0;
 238         AD2D0ER = 0;
 239         AD2D1ER = 0;
 240         AD3ER = 0;
 241
 242         pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
 243 }
 244
 245 static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
 246 {
 247         unsigned long flags, mask = 0;
 248
 249         switch (d->irq) {
 250         case IRQ_SSP3:
 251                 mask = ADXER_MFP_WSSP3;
 252                 break;
 253         case IRQ_MSL:
 254                 mask = ADXER_WMSL0;
 255                 break;
 256         case IRQ_USBH2:
 257         case IRQ_USBH1:
 258                 mask = ADXER_WUSBH;
 259                 break;
 260         case IRQ_KEYPAD:
 261                 mask = ADXER_WKP;
 262                 break;
 263         case IRQ_AC97:
 264                 mask = ADXER_MFP_WAC97;
 265                 break;
 266         case IRQ_USIM:
 267                 mask = ADXER_WUSIM0;
 268                 break;
 269         case IRQ_SSP2:
 270                 mask = ADXER_MFP_WSSP2;
 271                 break;
 272         case IRQ_I2C:
 273                 mask = ADXER_MFP_WI2C;
 274                 break;
 275         case IRQ_STUART:
 276                 mask = ADXER_MFP_WUART3;
 277                 break;
 278         case IRQ_BTUART:
 279                 mask = ADXER_MFP_WUART2;
 280                 break;
 281         case IRQ_FFUART:
 282                 mask = ADXER_MFP_WUART1;
 283                 break;
 284         case IRQ_MMC:
 285                 mask = ADXER_MFP_WMMC1;
 286                 break;
 287         case IRQ_SSP:
 288                 mask = ADXER_MFP_WSSP1;
 289                 break;
 290         case IRQ_RTCAlrm:
 291                 mask = ADXER_WRTC;
 292                 break;
 293         case IRQ_SSP4:
 294                 mask = ADXER_MFP_WSSP4;
 295                 break;
 296         case IRQ_TSI:
 297                 mask = ADXER_WTSI;
 298                 break;
 299         case IRQ_USIM2:
 300                 mask = ADXER_WUSIM1;
 301                 break;
 302         case IRQ_MMC2:
 303                 mask = ADXER_MFP_WMMC2;
 304                 break;
 305         case IRQ_NAND:
 306                 mask = ADXER_MFP_WFLASH;
 307                 break;
 308         case IRQ_USB2:
 309                 mask = ADXER_WUSB2;
 310                 break;
 311         case IRQ_WAKEUP0:
 312                 mask = ADXER_WEXTWAKE0;
 313                 break;
 314         case IRQ_WAKEUP1:
 315                 mask = ADXER_WEXTWAKE1;
 316                 break;
 317         case IRQ_MMC3:
 318                 mask = ADXER_MFP_GEN12;
 319                 break;
 320         default:
 321                 return -EINVAL;
 322         }
 323
 324         local_irq_save(flags);
 325         if (on)
 326                 wakeup_src |= mask;
 327         else
 328                 wakeup_src &= ~mask;
 329         local_irq_restore(flags);
 330
 331         return 0;
 332 }
 333 #else
 334 static inline void pxa3xx_init_pm(void) {}
 335 #define pxa3xx_set_wake NULL
 336 #endif
 337
 338 static void pxa_ack_ext_wakeup(struct irq_data *d)
 339 {
 340         PECR |= PECR_IS(d->irq - IRQ_WAKEUP0);
 341 }
 342
 343 static void pxa_mask_ext_wakeup(struct irq_data *d)
 344 {
 345         pxa_mask_irq(d);
 346         PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
 347 }
 348
 349 static void pxa_unmask_ext_wakeup(struct irq_data *d)
 350 {
 351         pxa_unmask_irq(d);
 352         PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);
 353 }
 354
 355 static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
 356 {
 357         if (flow_type & IRQ_TYPE_EDGE_RISING)
 358                 PWER |= 1 << (d->irq - IRQ_WAKEUP0);
 359
 360         if (flow_type & IRQ_TYPE_EDGE_FALLING)
 361                 PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2);
 362
 363         return 0;
 364 }
 365
 366 static struct irq_chip pxa_ext_wakeup_chip = {
 367         .name           = "WAKEUP",
 368         .irq_ack        = pxa_ack_ext_wakeup,
 369         .irq_mask       = pxa_mask_ext_wakeup,
 370         .irq_unmask     = pxa_unmask_ext_wakeup,
 371         .irq_set_type   = pxa_set_ext_wakeup_type,
 372 };
 373
 374 static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
 375                                            unsigned int))
 376 {
 377         int irq;
 378
 379         for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
 380                 irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
 381                                          handle_edge_irq);
 382                 set_irq_flags(irq, IRQF_VALID);
 383         }
 384
 385         pxa_ext_wakeup_chip.irq_set_wake = fn;
 386 }
 387
 388 static void __init __pxa3xx_init_irq(void)
 389 {
 390         /* enable CP6 access */
 391         u32 value;
 392         __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
 393         value |= (1 << 6);
 394         __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
 395
 396         pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
 397 }
 398
 399 void __init pxa3xx_init_irq(void)
 400 {
 401         __pxa3xx_init_irq();
 402         pxa_init_irq(56, pxa3xx_set_wake);
 403 }
 404
 405 #ifdef CONFIG_OF
 406 void __init pxa3xx_dt_init_irq(void)
 407 {
 408         __pxa3xx_init_irq();
 409         pxa_dt_irq_init(pxa3xx_set_wake);
 410 }
 411 #endif  /* CONFIG_OF */
 412
 413 static struct map_desc pxa3xx_io_desc[] __initdata = {
 414         {       /* Mem Ctl */
 415                 .virtual        = (unsigned long)SMEMC_VIRT,
 416                 .pfn            = __phys_to_pfn(PXA3XX_SMEMC_BASE),
 417                 .length         = 0x00200000,
 418                 .type           = MT_DEVICE
 419         }
 420 };
 421
 422 void __init pxa3xx_map_io(void)
 423 {
 424         pxa_map_io();
 425         iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
 426         pxa3xx_get_clk_frequency_khz(1);
 427 }
 428
 429 /*
 430  * device registration specific to PXA3xx.
 431  */
 432
 433 void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 434 {
 435         pxa_register_device(&pxa3xx_device_i2c_power, info);
 436 }
 437
 438 static struct platform_device *devices[] __initdata = {
 439         &pxa_device_gpio,
 440         &pxa27x_device_udc,
 441         &pxa_device_pmu,
 442         &pxa_device_i2s,
 443         &pxa_device_asoc_ssp1,
 444         &pxa_device_asoc_ssp2,
 445         &pxa_device_asoc_ssp3,
 446         &pxa_device_asoc_ssp4,
 447         &pxa_device_asoc_platform,
 448         &sa1100_device_rtc,
 449         &pxa_device_rtc,
 450         &pxa27x_device_ssp1,
 451         &pxa27x_device_ssp2,
 452         &pxa27x_device_ssp3,
 453         &pxa3xx_device_ssp4,
 454         &pxa27x_device_pwm0,
 455         &pxa27x_device_pwm1,
 456 };
 457
 458 static int __init pxa3xx_init(void)
 459 {
 460         int ret = 0;
 461
 462         if (cpu_is_pxa3xx()) {
 463
 464                 reset_status = ARSR;
 465
 466                 /*
 467                  * clear RDH bit every time after reset
 468                  *
 469                  * Note: the last 3 bits DxS are write-1-to-clear so carefully
 470                  * preserve them here in case they will be referenced later
 471                  */
 472                 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
 473
 474                 clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
 475
 476                 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
 477                         return ret;
 478
 479                 pxa3xx_init_pm();
 480
 481                 register_syscore_ops(&pxa_irq_syscore_ops);
 482                 register_syscore_ops(&pxa3xx_mfp_syscore_ops);
 483                 register_syscore_ops(&pxa3xx_clock_syscore_ops);
 484
 485                 if (!of_have_populated_dt())
 486                         ret = platform_add_devices(devices, ARRAY_SIZE(devices));
 487         }
 488
 489         return ret;
 490 }
 491
 492 postcore_initcall(pxa3xx_init);