arch/arm/mach-pxa/sleep.S

   1 /*
   2  * Low-level PXA250/210 sleep/wakeUp support
   3  *
   4  * Initial SA1110 code:
   5  * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
   6  *
   7  * Adapted for PXA by Nicolas Pitre:
   8  * Copyright (c) 2002 Monta Vista Software, Inc.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License.
  12  */
  13
  14 #include <linux/config.h>
  15 #include <linux/linkage.h>
  16 #include <asm/assembler.h>
  17 #include <asm/hardware.h>
  18
  19 #include <asm/arch/pxa-regs.h>
  20
  21 #ifdef CONFIG_PXA27x                    // workaround for Errata 50
  22 #define MDREFR_KDIV     0x200a4000      // all banks
  23 #define CCCR_SLEEP      0x00000107      // L=7 2N=2 A=0 PPDIS=0 CPDIS=0
  24 #endif
  25
  26                 .text
  27
  28 /*
  29  * pxa_cpu_suspend()
  30  *
  31  * Forces CPU into sleep state.
  32  *
  33  * r0 = value for PWRMODE M field for desired sleep state
  34  */
  35
  36 ENTRY(pxa_cpu_suspend)
  37
  38 #ifndef CONFIG_IWMMXT
  39         mra     r2, r3, acc0
  40 #endif
  41         stmfd   sp!, {r2 - r12, lr}             @ save registers on stack
  42
  43         @ get coprocessor registers
  44         mrc     p14, 0, r3, c6, c0, 0           @ clock configuration, for turbo mode
  45         mrc     p15, 0, r4, c15, c1, 0          @ CP access reg
  46         mrc     p15, 0, r5, c13, c0, 0          @ PID
  47         mrc     p15, 0, r6, c3, c0, 0           @ domain ID
  48         mrc     p15, 0, r7, c2, c0, 0           @ translation table base addr
  49         mrc     p15, 0, r8, c1, c1, 0           @ auxiliary control reg
  50         mrc     p15, 0, r9, c1, c0, 0           @ control reg
  51
  52         bic     r3, r3, #2                      @ clear frequency change bit
  53
  54         @ store them plus current virtual stack ptr on stack
  55         mov     r10, sp
  56         stmfd   sp!, {r3 - r10}
  57
  58         mov r5, r0                              @ save sleep mode
  59         @ preserve phys address of stack
  60         mov     r0, sp
  61         bl      sleep_phys_sp
  62         ldr     r1, =sleep_save_sp
  63         str     r0, [r1]
  64
  65         @ clean data cache
  66         bl      xscale_flush_kern_cache_all
  67
  68         @ Put the processor to sleep
  69         @ (also workaround for sighting 28071)
  70
  71         @ prepare value for sleep mode
  72         mov     r1, r5                          @ sleep mode
  73
  74         @ prepare pointer to physical address 0 (virtual mapping in generic.c)
  75         mov     r2, #UNCACHED_PHYS_0
  76
  77         @ prepare SDRAM refresh settings
  78         ldr     r4, =MDREFR
  79         ldr     r5, [r4]
  80
  81         @ enable SDRAM self-refresh mode
  82         orr     r5, r5, #MDREFR_SLFRSH
  83
  84 #ifdef CONFIG_PXA27x
  85         @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50)
  86         ldr     r6, =MDREFR_KDIV
  87         orr     r5, r5, r6
  88 #endif
  89
  90 #ifdef CONFIG_PXA25x
  91         @ Intel PXA255 Specification Update notes problems
  92         @ about suspending with PXBus operating above 133MHz
  93         @ (see Errata 31, GPIO output signals, ... unpredictable in sleep
  94         @
  95         @ We keep the change-down close to the actual suspend on SDRAM
  96         @ as possible to eliminate messing about with the refresh clock
  97         @ as the system will restore with the original speed settings
  98         @
  99         @ Ben Dooks, 13-Sep-2004
 100
 101         ldr     r6, =CCCR
 102         ldr     r8, [r6]                @ keep original value for resume
 103
 104         @ ensure x1 for run and turbo mode with memory clock
 105         bic     r7, r8, #CCCR_M_MASK | CCCR_N_MASK
 106         orr     r7, r7, #(1<<5) | (2<<7)
 107
 108         @ check that the memory frequency is within limits
 109         and     r14, r7, #CCCR_L_MASK
 110         teq     r14, #1
 111         bicne   r7, r7, #CCCR_L_MASK
 112         orrne   r7, r7, #1                      @@ 99.53MHz
 113
 114         @ get ready for the change
 115
 116         @ note, turbo is not preserved over sleep so there is no
 117         @ point in preserving it here. we save it on the stack with the
 118         @ other CP registers instead.
 119         mov     r0, #0
 120         mcr     p14, 0, r0, c6, c0, 0
 121         orr     r0, r0, #2                      @ initiate change bit
 122 #endif
 123 #ifdef CONFIG_PXA27x
 124         @ Intel PXA270 Specification Update notes problems sleeping
 125         @ with core operating above 91 MHz
 126         @ (see Errata 50, ...processor does not exit from sleep...)
 127
 128         ldr     r6, =CCCR
 129         ldr     r8, [r6]                @ keep original value for resume
 130
 131         ldr     r7, =CCCR_SLEEP         @ prepare CCCR sleep value
 132         mov     r0, #0x2                @ prepare value for CLKCFG
 133 #endif
 134
 135         @ align execution to a cache line
 136         b       1f
 137
 138         .ltorg
 139         .align  5
 140 1:
 141
 142         @ All needed values are now in registers.
 143         @ These last instructions should be in cache
 144
 145 #if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
 146         @ initiate the frequency change...
 147         str     r7, [r6]
 148         mcr     p14, 0, r0, c6, c0, 0
 149
 150         @ restore the original cpu speed value for resume
 151         str     r8, [r6]
 152
 153         @ need 6 13-MHz cycles before changing PWRMODE
 154         @ just set frequency to 91-MHz... 6*91/13 = 42
 155
 156         mov     r0, #42
 157 10:     subs    r0, r0, #1
 158         bne     10b
 159 #endif
 160
 161         @ Do not reorder...
 162         @ Intel PXA270 Specification Update notes problems performing
 163         @ external accesses after SDRAM is put in self-refresh mode
 164         @ (see Errata 39 ...hangs when entering self-refresh mode)
 165
 166         @ force address lines low by reading at physical address 0
 167         ldr     r3, [r2]
 168
 169         @ put SDRAM into self-refresh
 170         str     r5, [r4]
 171
 172         @ enter sleep mode
 173         mcr     p14, 0, r1, c7, c0, 0           @ PWRMODE
 174
 175 20:     b       20b                             @ loop waiting for sleep
 176
 177 /*
 178  * cpu_pxa_resume()
 179  *
 180  * entry point from bootloader into kernel during resume
 181  *
 182  * Note: Yes, part of the following code is located into the .data section.
 183  *       This is to allow sleep_save_sp to be accessed with a relative load
 184  *       while we can't rely on any MMU translation.  We could have put
 185  *       sleep_save_sp in the .text section as well, but some setups might
 186  *       insist on it to be truly read-only.
 187  */
 188
 189         .data
 190         .align 5
 191 ENTRY(pxa_cpu_resume)
 192         mov     r0, #PSR_I_BIT | PSR_F_BIT | MODE_SVC   @ set SVC, irqs off
 193         msr     cpsr_c, r0
 194
 195         ldr     r0, sleep_save_sp               @ stack phys addr
 196         ldr     r2, =resume_after_mmu           @ its absolute virtual address
 197         ldmfd   r0, {r3 - r9, sp}               @ CP regs + virt stack ptr
 198
 199         mov     r1, #0
 200         mcr     p15, 0, r1, c8, c7, 0           @ invalidate I & D TLBs
 201         mcr     p15, 0, r1, c7, c7, 0           @ invalidate I & D caches, BTB
 202
 203 #ifdef CONFIG_XSCALE_CACHE_ERRATA
 204         bic     r9, r9, #0x0004                 @ see cpu_xscale_proc_init
 205 #endif
 206
 207         mcr     p14, 0, r3, c6, c0, 0           @ clock configuration, turbo mode.
 208         mcr     p15, 0, r4, c15, c1, 0          @ CP access reg
 209         mcr     p15, 0, r5, c13, c0, 0          @ PID
 210         mcr     p15, 0, r6, c3, c0, 0           @ domain ID
 211         mcr     p15, 0, r7, c2, c0, 0           @ translation table base addr
 212         mcr     p15, 0, r8, c1, c1, 0           @ auxiliary control reg
 213         b       resume_turn_on_mmu              @ cache align execution
 214
 215         .align 5
 216 resume_turn_on_mmu:
 217         mcr     p15, 0, r9, c1, c0, 0           @ turn on MMU, caches, etc.
 218
 219         @ Let us ensure we jump to resume_after_mmu only when the mcr above
 220         @ actually took effect.  They call it the "cpwait" operation.
 221         mrc     p15, 0, r1, c2, c0, 0           @ queue a dependency on CP15
 222         sub     pc, r2, r1, lsr #32             @ jump to virtual addr
 223         nop
 224         nop
 225         nop
 226
 227 sleep_save_sp:
 228         .word   0                               @ preserve stack phys ptr here
 229
 230         .text
 231 resume_after_mmu:
 232 #ifdef CONFIG_XSCALE_CACHE_ERRATA
 233         bl      cpu_xscale_proc_init
 234 #endif
 235         ldmfd   sp!, {r2, r3}
 236 #ifndef CONFIG_IWMMXT
 237         mar     acc0, r2, r3
 238 #endif
 239         ldmfd   sp!, {r4 - r12, pc}             @ return to caller
 240
 241