arch/arm/mach-realview/realview_pb11mp.c

   1 /*
   2  *  linux/arch/arm/mach-realview/realview_pb11mp.c
   3  *
   4  *  Copyright (C) 2008 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/device.h>
  25 #include <linux/amba/bus.h>
  26 #include <linux/amba/pl061.h>
  27 #include <linux/amba/mmci.h>
  28 #include <linux/amba/pl022.h>
  29 #include <linux/io.h>
  30 #include <linux/irqchip/arm-gic.h>
  31 #include <linux/platform_data/clk-realview.h>
  32 #include <linux/reboot.h>
  33
  34 #include "hardware.h"
  35 #include <asm/irq.h>
  36 #include <asm/mach-types.h>
  37 #include <asm/pgtable.h>
  38 #include <asm/hardware/cache-l2x0.h>
  39 #include <asm/smp_twd.h>
  40
  41 #include <asm/mach/arch.h>
  42 #include <asm/mach/flash.h>
  43 #include <asm/mach/map.h>
  44 #include <asm/mach/time.h>
  45 #include <asm/outercache.h>
  46
  47 #include "board-pb11mp.h"
  48 #include "irqs-pb11mp.h"
  49
  50 #include "core.h"
  51
  52 static struct map_desc realview_pb11mp_io_desc[] __initdata = {
  53         {
  54                 .virtual        = IO_ADDRESS(REALVIEW_SYS_BASE),
  55                 .pfn            = __phys_to_pfn(REALVIEW_SYS_BASE),
  56                 .length         = SZ_4K,
  57                 .type           = MT_DEVICE,
  58         }, {
  59                 .virtual        = IO_ADDRESS(REALVIEW_PB11MP_GIC_CPU_BASE),
  60                 .pfn            = __phys_to_pfn(REALVIEW_PB11MP_GIC_CPU_BASE),
  61                 .length         = SZ_4K,
  62                 .type           = MT_DEVICE,
  63         }, {
  64                 .virtual        = IO_ADDRESS(REALVIEW_PB11MP_GIC_DIST_BASE),
  65                 .pfn            = __phys_to_pfn(REALVIEW_PB11MP_GIC_DIST_BASE),
  66                 .length         = SZ_4K,
  67                 .type           = MT_DEVICE,
  68         }, {    /* Maps the SCU, GIC CPU interface, TWD, GIC DIST */
  69                 .virtual        = IO_ADDRESS(REALVIEW_TC11MP_PRIV_MEM_BASE),
  70                 .pfn            = __phys_to_pfn(REALVIEW_TC11MP_PRIV_MEM_BASE),
  71                 .length         = REALVIEW_TC11MP_PRIV_MEM_SIZE,
  72                 .type           = MT_DEVICE,
  73         }, {
  74                 .virtual        = IO_ADDRESS(REALVIEW_SCTL_BASE),
  75                 .pfn            = __phys_to_pfn(REALVIEW_SCTL_BASE),
  76                 .length         = SZ_4K,
  77                 .type           = MT_DEVICE,
  78         }, {
  79                 .virtual        = IO_ADDRESS(REALVIEW_PB11MP_TIMER0_1_BASE),
  80                 .pfn            = __phys_to_pfn(REALVIEW_PB11MP_TIMER0_1_BASE),
  81                 .length         = SZ_4K,
  82                 .type           = MT_DEVICE,
  83         }, {
  84                 .virtual        = IO_ADDRESS(REALVIEW_PB11MP_TIMER2_3_BASE),
  85                 .pfn            = __phys_to_pfn(REALVIEW_PB11MP_TIMER2_3_BASE),
  86                 .length         = SZ_4K,
  87                 .type           = MT_DEVICE,
  88         }, {
  89                 .virtual        = IO_ADDRESS(REALVIEW_TC11MP_L220_BASE),
  90                 .pfn            = __phys_to_pfn(REALVIEW_TC11MP_L220_BASE),
  91                 .length         = SZ_8K,
  92                 .type           = MT_DEVICE,
  93         },
  94 #ifdef CONFIG_DEBUG_LL
  95         {
  96                 .virtual        = IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE),
  97                 .pfn            = __phys_to_pfn(REALVIEW_PB11MP_UART0_BASE),
  98                 .length         = SZ_4K,
  99                 .type           = MT_DEVICE,
 100         },
 101 #endif
 102 };
 103
 104 static void __init realview_pb11mp_map_io(void)
 105 {
 106         iotable_init(realview_pb11mp_io_desc, ARRAY_SIZE(realview_pb11mp_io_desc));
 107 }
 108
 109 static struct pl061_platform_data gpio0_plat_data = {
 110         .gpio_base      = 0,
 111 };
 112
 113 static struct pl061_platform_data gpio1_plat_data = {
 114         .gpio_base      = 8,
 115 };
 116
 117 static struct pl061_platform_data gpio2_plat_data = {
 118         .gpio_base      = 16,
 119 };
 120
 121 static struct pl022_ssp_controller ssp0_plat_data = {
 122         .bus_id = 0,
 123         .enable_dma = 0,
 124         .num_chipselect = 1,
 125 };
 126
 127 /*
 128  * RealView PB11MPCore AMBA devices
 129  */
 130
 131 #define GPIO2_IRQ               { IRQ_PB11MP_GPIO2 }
 132 #define GPIO3_IRQ               { IRQ_PB11MP_GPIO3 }
 133 #define AACI_IRQ                { IRQ_TC11MP_AACI }
 134 #define MMCI0_IRQ               { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B }
 135 #define KMI0_IRQ                { IRQ_TC11MP_KMI0 }
 136 #define KMI1_IRQ                { IRQ_TC11MP_KMI1 }
 137 #define PB11MP_SMC_IRQ          { }
 138 #define MPMC_IRQ                { }
 139 #define PB11MP_CLCD_IRQ         { IRQ_PB11MP_CLCD }
 140 #define DMAC_IRQ                { IRQ_PB11MP_DMAC }
 141 #define SCTL_IRQ                { }
 142 #define PB11MP_WATCHDOG_IRQ     { IRQ_PB11MP_WATCHDOG }
 143 #define PB11MP_GPIO0_IRQ        { IRQ_PB11MP_GPIO0 }
 144 #define GPIO1_IRQ               { IRQ_PB11MP_GPIO1 }
 145 #define PB11MP_RTC_IRQ          { IRQ_TC11MP_RTC }
 146 #define SCI_IRQ                 { IRQ_PB11MP_SCI }
 147 #define PB11MP_UART0_IRQ        { IRQ_TC11MP_UART0 }
 148 #define PB11MP_UART1_IRQ        { IRQ_TC11MP_UART1 }
 149 #define PB11MP_UART2_IRQ        { IRQ_PB11MP_UART2 }
 150 #define PB11MP_UART3_IRQ        { IRQ_PB11MP_UART3 }
 151 #define PB11MP_SSP_IRQ          { IRQ_PB11MP_SSP }
 152
 153 /* FPGA Primecells */
 154 APB_DEVICE(aaci,        "fpga:aaci",    AACI,           NULL);
 155 APB_DEVICE(mmc0,        "fpga:mmc0",    MMCI0,          &realview_mmc0_plat_data);
 156 APB_DEVICE(kmi0,        "fpga:kmi0",    KMI0,           NULL);
 157 APB_DEVICE(kmi1,        "fpga:kmi1",    KMI1,           NULL);
 158 APB_DEVICE(uart3,       "fpga:uart3",   PB11MP_UART3,   NULL);
 159
 160 /* DevChip Primecells */
 161 AHB_DEVICE(smc,         "dev:smc",      PB11MP_SMC,     NULL);
 162 AHB_DEVICE(sctl,        "dev:sctl",     SCTL,           NULL);
 163 APB_DEVICE(wdog,        "dev:wdog",     PB11MP_WATCHDOG, NULL);
 164 APB_DEVICE(gpio0,       "dev:gpio0",    PB11MP_GPIO0,   &gpio0_plat_data);
 165 APB_DEVICE(gpio1,       "dev:gpio1",    GPIO1,          &gpio1_plat_data);
 166 APB_DEVICE(gpio2,       "dev:gpio2",    GPIO2,          &gpio2_plat_data);
 167 APB_DEVICE(rtc,         "dev:rtc",      PB11MP_RTC,     NULL);
 168 APB_DEVICE(sci0,        "dev:sci0",     SCI,            NULL);
 169 APB_DEVICE(uart0,       "dev:uart0",    PB11MP_UART0,   NULL);
 170 APB_DEVICE(uart1,       "dev:uart1",    PB11MP_UART1,   NULL);
 171 APB_DEVICE(uart2,       "dev:uart2",    PB11MP_UART2,   NULL);
 172 APB_DEVICE(ssp0,        "dev:ssp0",     PB11MP_SSP,     &ssp0_plat_data);
 173
 174 /* Primecells on the NEC ISSP chip */
 175 AHB_DEVICE(clcd,        "issp:clcd",    PB11MP_CLCD,    &clcd_plat_data);
 176 AHB_DEVICE(dmac,        "issp:dmac",    DMAC,           NULL);
 177
 178 static struct amba_device *amba_devs[] __initdata = {
 179         &dmac_device,
 180         &uart0_device,
 181         &uart1_device,
 182         &uart2_device,
 183         &uart3_device,
 184         &smc_device,
 185         &clcd_device,
 186         &sctl_device,
 187         &wdog_device,
 188         &gpio0_device,
 189         &gpio1_device,
 190         &gpio2_device,
 191         &rtc_device,
 192         &sci0_device,
 193         &ssp0_device,
 194         &aaci_device,
 195         &mmc0_device,
 196         &kmi0_device,
 197         &kmi1_device,
 198 };
 199
 200 /*
 201  * RealView PB11MPCore platform devices
 202  */
 203 static struct resource realview_pb11mp_flash_resource[] = {
 204         [0] = {
 205                 .start          = REALVIEW_PB11MP_FLASH0_BASE,
 206                 .end            = REALVIEW_PB11MP_FLASH0_BASE + REALVIEW_PB11MP_FLASH0_SIZE - 1,
 207                 .flags          = IORESOURCE_MEM,
 208         },
 209         [1] = {
 210                 .start          = REALVIEW_PB11MP_FLASH1_BASE,
 211                 .end            = REALVIEW_PB11MP_FLASH1_BASE + REALVIEW_PB11MP_FLASH1_SIZE - 1,
 212                 .flags          = IORESOURCE_MEM,
 213         },
 214 };
 215
 216 static struct resource realview_pb11mp_smsc911x_resources[] = {
 217         [0] = {
 218                 .start          = REALVIEW_PB11MP_ETH_BASE,
 219                 .end            = REALVIEW_PB11MP_ETH_BASE + SZ_64K - 1,
 220                 .flags          = IORESOURCE_MEM,
 221         },
 222         [1] = {
 223                 .start          = IRQ_TC11MP_ETH,
 224                 .end            = IRQ_TC11MP_ETH,
 225                 .flags          = IORESOURCE_IRQ,
 226         },
 227 };
 228
 229 static struct resource realview_pb11mp_isp1761_resources[] = {
 230         [0] = {
 231                 .start          = REALVIEW_PB11MP_USB_BASE,
 232                 .end            = REALVIEW_PB11MP_USB_BASE + SZ_128K - 1,
 233                 .flags          = IORESOURCE_MEM,
 234         },
 235         [1] = {
 236                 .start          = IRQ_TC11MP_USB,
 237                 .end            = IRQ_TC11MP_USB,
 238                 .flags          = IORESOURCE_IRQ,
 239         },
 240 };
 241
 242 static struct resource pmu_resources[] = {
 243         [0] = {
 244                 .start          = IRQ_TC11MP_PMU_CPU0,
 245                 .end            = IRQ_TC11MP_PMU_CPU0,
 246                 .flags          = IORESOURCE_IRQ,
 247         },
 248         [1] = {
 249                 .start          = IRQ_TC11MP_PMU_CPU1,
 250                 .end            = IRQ_TC11MP_PMU_CPU1,
 251                 .flags          = IORESOURCE_IRQ,
 252         },
 253         [2] = {
 254                 .start          = IRQ_TC11MP_PMU_CPU2,
 255                 .end            = IRQ_TC11MP_PMU_CPU2,
 256                 .flags          = IORESOURCE_IRQ,
 257         },
 258         [3] = {
 259                 .start          = IRQ_TC11MP_PMU_CPU3,
 260                 .end            = IRQ_TC11MP_PMU_CPU3,
 261                 .flags          = IORESOURCE_IRQ,
 262         },
 263 };
 264
 265 static struct platform_device pmu_device = {
 266         .name                   = "armv6-pmu",
 267         .id                     = -1,
 268         .num_resources          = ARRAY_SIZE(pmu_resources),
 269         .resource               = pmu_resources,
 270 };
 271
 272 static void __init gic_init_irq(void)
 273 {
 274         unsigned int pldctrl;
 275
 276         /* new irq mode with no DCC */
 277         writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
 278         pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
 279         pldctrl |= 2 << 22;
 280         writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
 281         writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
 282
 283         /* ARM11MPCore test chip GIC, primary */
 284         gic_init(0, 29, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE),
 285                  __io_address(REALVIEW_TC11MP_GIC_CPU_BASE));
 286
 287         /* board GIC, secondary */
 288         gic_init(1, IRQ_PB11MP_GIC_START,
 289                  __io_address(REALVIEW_PB11MP_GIC_DIST_BASE),
 290                  __io_address(REALVIEW_PB11MP_GIC_CPU_BASE));
 291         gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1);
 292 }
 293
 294 #ifdef CONFIG_HAVE_ARM_TWD
 295 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
 296                               REALVIEW_TC11MP_TWD_BASE,
 297                               IRQ_LOCALTIMER);
 298
 299 static void __init realview_pb11mp_twd_init(void)
 300 {
 301         int err = twd_local_timer_register(&twd_local_timer);
 302         if (err)
 303                 pr_err("twd_local_timer_register failed %d\n", err);
 304 }
 305 #else
 306 #define realview_pb11mp_twd_init()      do {} while(0)
 307 #endif
 308
 309 static void __init realview_pb11mp_timer_init(void)
 310 {
 311         timer0_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE);
 312         timer1_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE) + 0x20;
 313         timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE);
 314         timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20;
 315
 316         realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
 317         realview_timer_init(IRQ_TC11MP_TIMER0_1);
 318         realview_pb11mp_twd_init();
 319 }
 320
 321 static void realview_pb11mp_restart(enum reboot_mode mode, const char *cmd)
 322 {
 323         void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
 324         void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
 325
 326         /*
 327          * To reset, we hit the on-board reset register
 328          * in the system FPGA
 329          */
 330         __raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
 331         __raw_writel(0x0000, reset_ctrl);
 332         __raw_writel(0x0004, reset_ctrl);
 333         dsb();
 334 }
 335
 336 static void __init realview_pb11mp_init(void)
 337 {
 338         int i;
 339
 340 #ifdef CONFIG_CACHE_L2X0
 341         /*
 342          * The PL220 needs to be manually configured as the hardware
 343          * doesn't report the correct sizes.
 344          * 1MB (128KB/way), 8-way associativity, event monitor and
 345          * parity enabled, ignore share bit, no force write allocate
 346          * Bits:  .... ...0 0111 1001 0000 .... .... ....
 347          */
 348         l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff);
 349         /*
 350          * due to a bug in the l220 cache controller, we must not call
 351          * the sync function. stub it out here instead!
 352          */
 353         outer_cache.sync = NULL;
 354 #endif
 355
 356         realview_flash_register(realview_pb11mp_flash_resource,
 357                                 ARRAY_SIZE(realview_pb11mp_flash_resource));
 358         realview_eth_register(NULL, realview_pb11mp_smsc911x_resources);
 359         platform_device_register(&realview_i2c_device);
 360         platform_device_register(&realview_cf_device);
 361         platform_device_register(&realview_leds_device);
 362         realview_usb_register(realview_pb11mp_isp1761_resources);
 363         platform_device_register(&pmu_device);
 364
 365         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 366                 struct amba_device *d = amba_devs[i];
 367                 amba_device_register(d, &iomem_resource);
 368         }
 369 }
 370
 371 MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
 372         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
 373         .atag_offset    = 0x100,
 374         .smp            = smp_ops(realview_smp_ops),
 375         .fixup          = realview_fixup,
 376         .map_io         = realview_pb11mp_map_io,
 377         .init_early     = realview_init_early,
 378         .init_irq       = gic_init_irq,
 379         .init_time      = realview_pb11mp_timer_init,
 380         .init_machine   = realview_pb11mp_init,
 381 #ifdef CONFIG_ZONE_DMA
 382         .dma_zone_size  = SZ_256M,
 383 #endif
 384         .restart        = realview_pb11mp_restart,
 385 MACHINE_END