arch/arm/mach-s5p64x0/common.c

   1 /*
   2  * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * Common Codes for S5P64X0 machines
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/list.h>
  16 #include <linux/timer.h>
  17 #include <linux/init.h>
  18 #include <linux/clk.h>
  19 #include <linux/io.h>
  20 #include <linux/device.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/serial_s3c.h>
  23 #include <clocksource/samsung_pwm.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/sched.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/gpio.h>
  28 #include <linux/irq.h>
  29 #include <linux/reboot.h>
  30
  31 #include <asm/irq.h>
  32 #include <asm/proc-fns.h>
  33 #include <asm/system_misc.h>
  34 #include <asm/mach/arch.h>
  35 #include <asm/mach/map.h>
  36 #include <asm/mach/irq.h>
  37
  38 #include <mach/map.h>
  39 #include <mach/hardware.h>
  40 #include <mach/regs-clock.h>
  41 #include <mach/regs-gpio.h>
  42
  43 #include <plat/cpu.h>
  44 #include <plat/clock.h>
  45 #include <plat/devs.h>
  46 #include <plat/pm.h>
  47 #include <plat/sdhci.h>
  48 #include <plat/adc-core.h>
  49 #include <plat/fb-core.h>
  50 #include <plat/spi-core.h>
  51 #include <plat/gpio-cfg.h>
  52 #include <plat/pwm-core.h>
  53 #include <plat/regs-irqtype.h>
  54 #include <plat/watchdog-reset.h>
  55
  56 #include "common.h"
  57
  58 static const char name_s5p6440[] = "S5P6440";
  59 static const char name_s5p6450[] = "S5P6450";
  60
  61 static struct cpu_table cpu_ids[] __initdata = {
  62         {
  63                 .idcode         = S5P6440_CPU_ID,
  64                 .idmask         = S5P64XX_CPU_MASK,
  65                 .map_io         = s5p6440_map_io,
  66                 .init_clocks    = s5p6440_init_clocks,
  67                 .init_uarts     = s5p6440_init_uarts,
  68                 .init           = s5p64x0_init,
  69                 .name           = name_s5p6440,
  70         }, {
  71                 .idcode         = S5P6450_CPU_ID,
  72                 .idmask         = S5P64XX_CPU_MASK,
  73                 .map_io         = s5p6450_map_io,
  74                 .init_clocks    = s5p6450_init_clocks,
  75                 .init_uarts     = s5p6450_init_uarts,
  76                 .init           = s5p64x0_init,
  77                 .name           = name_s5p6450,
  78         },
  79 };
  80
  81 /* Initial IO mappings */
  82
  83 static struct map_desc s5p64x0_iodesc[] __initdata = {
  84         {
  85                 .virtual        = (unsigned long)S5P_VA_CHIPID,
  86                 .pfn            = __phys_to_pfn(S5P64X0_PA_CHIPID),
  87                 .length         = SZ_4K,
  88                 .type           = MT_DEVICE,
  89         }, {
  90                 .virtual        = (unsigned long)S3C_VA_SYS,
  91                 .pfn            = __phys_to_pfn(S5P64X0_PA_SYSCON),
  92                 .length         = SZ_64K,
  93                 .type           = MT_DEVICE,
  94         }, {
  95                 .virtual        = (unsigned long)S3C_VA_TIMER,
  96                 .pfn            = __phys_to_pfn(S5P64X0_PA_TIMER),
  97                 .length         = SZ_16K,
  98                 .type           = MT_DEVICE,
  99         }, {
 100                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 101                 .pfn            = __phys_to_pfn(S5P64X0_PA_WDT),
 102                 .length         = SZ_4K,
 103                 .type           = MT_DEVICE,
 104         }, {
 105                 .virtual        = (unsigned long)S5P_VA_SROMC,
 106                 .pfn            = __phys_to_pfn(S5P64X0_PA_SROMC),
 107                 .length         = SZ_4K,
 108                 .type           = MT_DEVICE,
 109         }, {
 110                 .virtual        = (unsigned long)S5P_VA_GPIO,
 111                 .pfn            = __phys_to_pfn(S5P64X0_PA_GPIO),
 112                 .length         = SZ_4K,
 113                 .type           = MT_DEVICE,
 114         }, {
 115                 .virtual        = (unsigned long)VA_VIC0,
 116                 .pfn            = __phys_to_pfn(S5P64X0_PA_VIC0),
 117                 .length         = SZ_16K,
 118                 .type           = MT_DEVICE,
 119         }, {
 120                 .virtual        = (unsigned long)VA_VIC1,
 121                 .pfn            = __phys_to_pfn(S5P64X0_PA_VIC1),
 122                 .length         = SZ_16K,
 123                 .type           = MT_DEVICE,
 124         },
 125 };
 126
 127 static struct map_desc s5p6440_iodesc[] __initdata = {
 128         {
 129                 .virtual        = (unsigned long)S3C_VA_UART,
 130                 .pfn            = __phys_to_pfn(S5P6440_PA_UART(0)),
 131                 .length         = SZ_4K,
 132                 .type           = MT_DEVICE,
 133         },
 134 };
 135
 136 static struct map_desc s5p6450_iodesc[] __initdata = {
 137         {
 138                 .virtual        = (unsigned long)S3C_VA_UART,
 139                 .pfn            = __phys_to_pfn(S5P6450_PA_UART(0)),
 140                 .length         = SZ_512K,
 141                 .type           = MT_DEVICE,
 142         }, {
 143                 .virtual        = (unsigned long)S3C_VA_UART + SZ_512K,
 144                 .pfn            = __phys_to_pfn(S5P6450_PA_UART(5)),
 145                 .length         = SZ_4K,
 146                 .type           = MT_DEVICE,
 147         },
 148 };
 149
 150 static void s5p64x0_idle(void)
 151 {
 152         unsigned long val;
 153
 154         val = __raw_readl(S5P64X0_PWR_CFG);
 155         val &= ~(0x3 << 5);
 156         val |= (0x1 << 5);
 157         __raw_writel(val, S5P64X0_PWR_CFG);
 158
 159         cpu_do_idle();
 160 }
 161
 162 static struct samsung_pwm_variant s5p64x0_pwm_variant = {
 163         .bits           = 32,
 164         .div_base       = 0,
 165         .has_tint_cstat = true,
 166         .tclk_mask      = 0,
 167 };
 168
 169 void __init samsung_set_timer_source(unsigned int event, unsigned int source)
 170 {
 171         s5p64x0_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
 172         s5p64x0_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
 173 }
 174
 175 void __init samsung_timer_init(void)
 176 {
 177         unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
 178                 IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
 179                 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
 180         };
 181
 182         samsung_pwm_clocksource_init(S3C_VA_TIMER,
 183                                         timer_irqs, &s5p64x0_pwm_variant);
 184 }
 185
 186 /*
 187  * s5p64x0_map_io
 188  *
 189  * register the standard CPU IO areas
 190  */
 191
 192 void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
 193 {
 194         /* initialize the io descriptors we need for initialization */
 195         iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
 196         if (mach_desc)
 197                 iotable_init(mach_desc, size);
 198
 199         /* detect cpu id and rev. */
 200         s5p_init_cpu(S5P64X0_SYS_ID);
 201
 202         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 203         samsung_wdt_reset_init(S3C_VA_WATCHDOG);
 204
 205         samsung_pwm_set_platdata(&s5p64x0_pwm_variant);
 206 }
 207
 208 #ifdef CONFIG_CPU_S5P6440
 209 void __init s5p6440_map_io(void)
 210 {
 211         /* initialize any device information early */
 212         s3c_adc_setname("s3c64xx-adc");
 213         s3c_fb_setname("s5p64x0-fb");
 214         s3c64xx_spi_setname("s5p64x0-spi");
 215
 216         s5p64x0_default_sdhci0();
 217         s5p64x0_default_sdhci1();
 218         s5p6440_default_sdhci2();
 219
 220         iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
 221 }
 222 #endif
 223
 224 #ifdef CONFIG_CPU_S5P6450
 225 void __init s5p6450_map_io(void)
 226 {
 227         /* initialize any device information early */
 228         s3c_adc_setname("s3c64xx-adc");
 229         s3c_fb_setname("s5p64x0-fb");
 230         s3c64xx_spi_setname("s5p64x0-spi");
 231
 232         s5p64x0_default_sdhci0();
 233         s5p64x0_default_sdhci1();
 234         s5p6450_default_sdhci2();
 235
 236         iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
 237 }
 238 #endif
 239
 240 /*
 241  * s5p64x0_init_clocks
 242  *
 243  * register and setup the CPU clocks
 244  */
 245 #ifdef CONFIG_CPU_S5P6440
 246 void __init s5p6440_init_clocks(int xtal)
 247 {
 248         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 249
 250         s3c24xx_register_baseclocks(xtal);
 251         s5p_register_clocks(xtal);
 252         s5p6440_register_clocks();
 253         s5p6440_setup_clocks();
 254 }
 255 #endif
 256
 257 #ifdef CONFIG_CPU_S5P6450
 258 void __init s5p6450_init_clocks(int xtal)
 259 {
 260         printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
 261
 262         s3c24xx_register_baseclocks(xtal);
 263         s5p_register_clocks(xtal);
 264         s5p6450_register_clocks();
 265         s5p6450_setup_clocks();
 266 }
 267 #endif
 268
 269 /*
 270  * s5p64x0_init_irq
 271  *
 272  * register the CPU interrupts
 273  */
 274 #ifdef CONFIG_CPU_S5P6440
 275 void __init s5p6440_init_irq(void)
 276 {
 277         /* S5P6440 supports 2 VIC */
 278         u32 vic[2];
 279
 280         /*
 281          * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
 282          * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
 283          */
 284         vic[0] = 0xff800ae7;
 285         vic[1] = 0xffbf23e5;
 286
 287         s5p_init_irq(vic, ARRAY_SIZE(vic));
 288 }
 289 #endif
 290
 291 #ifdef CONFIG_CPU_S5P6450
 292 void __init s5p6450_init_irq(void)
 293 {
 294         /* S5P6450 supports only 2 VIC */
 295         u32 vic[2];
 296
 297         /*
 298          * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
 299          * VIC1 is missing IRQ VIC1[12, 14, 23]
 300          */
 301         vic[0] = 0xff9f1fff;
 302         vic[1] = 0xff7fafff;
 303
 304         s5p_init_irq(vic, ARRAY_SIZE(vic));
 305 }
 306 #endif
 307
 308 struct bus_type s5p64x0_subsys = {
 309         .name           = "s5p64x0-core",
 310         .dev_name       = "s5p64x0-core",
 311 };
 312
 313 static struct device s5p64x0_dev = {
 314         .bus    = &s5p64x0_subsys,
 315 };
 316
 317 static int __init s5p64x0_core_init(void)
 318 {
 319         return subsys_system_register(&s5p64x0_subsys, NULL);
 320 }
 321 core_initcall(s5p64x0_core_init);
 322
 323 int __init s5p64x0_init(void)
 324 {
 325         printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
 326
 327         /* set idle function */
 328         arm_pm_idle = s5p64x0_idle;
 329
 330         return device_register(&s5p64x0_dev);
 331 }
 332
 333 /* uart registration process */
 334 #ifdef CONFIG_CPU_S5P6440
 335 void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 336 {
 337         int uart;
 338
 339         for (uart = 0; uart < no; uart++) {
 340                 s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
 341                 s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
 342         }
 343
 344         s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 345 }
 346 #endif
 347
 348 #ifdef CONFIG_CPU_S5P6450
 349 void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 350 {
 351         s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
 352 }
 353 #endif
 354
 355 #define eint_offset(irq)        ((irq) - IRQ_EINT(0))
 356
 357 static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
 358 {
 359         int offs = eint_offset(data->irq);
 360         int shift;
 361         u32 ctrl, mask;
 362         u32 newvalue = 0;
 363
 364         if (offs > 15)
 365                 return -EINVAL;
 366
 367         switch (type) {
 368         case IRQ_TYPE_NONE:
 369                 printk(KERN_WARNING "No edge setting!\n");
 370                 break;
 371         case IRQ_TYPE_EDGE_RISING:
 372                 newvalue = S3C2410_EXTINT_RISEEDGE;
 373                 break;
 374         case IRQ_TYPE_EDGE_FALLING:
 375                 newvalue = S3C2410_EXTINT_FALLEDGE;
 376                 break;
 377         case IRQ_TYPE_EDGE_BOTH:
 378                 newvalue = S3C2410_EXTINT_BOTHEDGE;
 379                 break;
 380         case IRQ_TYPE_LEVEL_LOW:
 381                 newvalue = S3C2410_EXTINT_LOWLEV;
 382                 break;
 383         case IRQ_TYPE_LEVEL_HIGH:
 384                 newvalue = S3C2410_EXTINT_HILEV;
 385                 break;
 386         default:
 387                 printk(KERN_ERR "No such irq type %d", type);
 388                 return -EINVAL;
 389         }
 390
 391         shift = (offs / 2) * 4;
 392         mask = 0x7 << shift;
 393
 394         ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
 395         ctrl |= newvalue << shift;
 396         __raw_writel(ctrl, S5P64X0_EINT0CON0);
 397
 398         /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
 399         if (soc_is_s5p6450())
 400                 s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
 401         else
 402                 s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
 403
 404         return 0;
 405 }
 406
 407 /*
 408  * s5p64x0_irq_demux_eint
 409  *
 410  * This function demuxes the IRQ from the group0 external interrupts,
 411  * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
 412  * the specific handlers s5p64x0_irq_demux_eintX_Y.
 413  */
 414 static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
 415 {
 416         u32 status = __raw_readl(S5P64X0_EINT0PEND);
 417         u32 mask = __raw_readl(S5P64X0_EINT0MASK);
 418         unsigned int irq;
 419
 420         status &= ~mask;
 421         status >>= start;
 422         status &= (1 << (end - start + 1)) - 1;
 423
 424         for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
 425                 if (status & 1)
 426                         generic_handle_irq(irq);
 427                 status >>= 1;
 428         }
 429 }
 430
 431 static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
 432 {
 433         s5p64x0_irq_demux_eint(0, 3);
 434 }
 435
 436 static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
 437 {
 438         s5p64x0_irq_demux_eint(4, 11);
 439 }
 440
 441 static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
 442                                         struct irq_desc *desc)
 443 {
 444         s5p64x0_irq_demux_eint(12, 15);
 445 }
 446
 447 static int s5p64x0_alloc_gc(void)
 448 {
 449         struct irq_chip_generic *gc;
 450         struct irq_chip_type *ct;
 451
 452         gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
 453                                     S5P_VA_GPIO, handle_level_irq);
 454         if (!gc) {
 455                 printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
 456                         "external interrupts failed\n", __func__);
 457                 return -EINVAL;
 458         }
 459
 460         ct = gc->chip_types;
 461         ct->chip.irq_ack = irq_gc_ack_set_bit;
 462         ct->chip.irq_mask = irq_gc_mask_set_bit;
 463         ct->chip.irq_unmask = irq_gc_mask_clr_bit;
 464         ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
 465         ct->chip.irq_set_wake = s3c_irqext_wake;
 466         ct->regs.ack = EINT0PEND_OFFSET;
 467         ct->regs.mask = EINT0MASK_OFFSET;
 468         irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
 469                                IRQ_NOREQUEST | IRQ_NOPROBE, 0);
 470         return 0;
 471 }
 472
 473 static int __init s5p64x0_init_irq_eint(void)
 474 {
 475         int ret = s5p64x0_alloc_gc();
 476         irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
 477         irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
 478         irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
 479
 480         return ret;
 481 }
 482 arch_initcall(s5p64x0_init_irq_eint);
 483
 484 void s5p64x0_restart(enum reboot_mode mode, const char *cmd)
 485 {
 486         if (mode != REBOOT_SOFT)
 487                 samsung_wdt_reset();
 488
 489         soft_restart(0);
 490 }