arch/arm/mach-sa1100/generic.c

   1 /*
   2  * linux/arch/arm/mach-sa1100/generic.c
   3  *
   4  * Author: Nicolas Pitre
   5  *
   6  * Code common to all SA11x0 machines.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/gpio.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/delay.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/pm.h>
  19 #include <linux/cpufreq.h>
  20 #include <linux/ioport.h>
  21 #include <linux/platform_device.h>
  22
  23 #include <asm/div64.h>
  24 #include <mach/hardware.h>
  25 #include <asm/system.h>
  26 #include <asm/mach/map.h>
  27 #include <asm/mach/flash.h>
  28 #include <asm/irq.h>
  29
  30 #include "generic.h"
  31
  32 unsigned int reset_status;
  33 EXPORT_SYMBOL(reset_status);
  34
  35 #define NR_FREQS        16
  36
  37 /*
  38  * This table is setup for a 3.6864MHz Crystal.
  39  */
  40 static const unsigned short cclk_frequency_100khz[NR_FREQS] = {
  41          590,   /*  59.0 MHz */
  42          737,   /*  73.7 MHz */
  43          885,   /*  88.5 MHz */
  44         1032,   /* 103.2 MHz */
  45         1180,   /* 118.0 MHz */
  46         1327,   /* 132.7 MHz */
  47         1475,   /* 147.5 MHz */
  48         1622,   /* 162.2 MHz */
  49         1769,   /* 176.9 MHz */
  50         1917,   /* 191.7 MHz */
  51         2064,   /* 206.4 MHz */
  52         2212,   /* 221.2 MHz */
  53         2359,   /* 235.9 MHz */
  54         2507,   /* 250.7 MHz */
  55         2654,   /* 265.4 MHz */
  56         2802    /* 280.2 MHz */
  57 };
  58
  59 /* rounds up(!)  */
  60 unsigned int sa11x0_freq_to_ppcr(unsigned int khz)
  61 {
  62         int i;
  63
  64         khz /= 100;
  65
  66         for (i = 0; i < NR_FREQS; i++)
  67                 if (cclk_frequency_100khz[i] >= khz)
  68                         break;
  69
  70         return i;
  71 }
  72
  73 unsigned int sa11x0_ppcr_to_freq(unsigned int idx)
  74 {
  75         unsigned int freq = 0;
  76         if (idx < NR_FREQS)
  77                 freq = cclk_frequency_100khz[idx] * 100;
  78         return freq;
  79 }
  80
  81
  82 /* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on
  83  * this platform, anyway.
  84  */
  85 int sa11x0_verify_speed(struct cpufreq_policy *policy)
  86 {
  87         unsigned int tmp;
  88         if (policy->cpu)
  89                 return -EINVAL;
  90
  91         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
  92
  93         /* make sure that at least one frequency is within the policy */
  94         tmp = cclk_frequency_100khz[sa11x0_freq_to_ppcr(policy->min)] * 100;
  95         if (tmp > policy->max)
  96                 policy->max = tmp;
  97
  98         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
  99
 100         return 0;
 101 }
 102
 103 unsigned int sa11x0_getspeed(unsigned int cpu)
 104 {
 105         if (cpu)
 106                 return 0;
 107         return cclk_frequency_100khz[PPCR & 0xf] * 100;
 108 }
 109
 110 /*
 111  * Default power-off for SA1100
 112  */
 113 static void sa1100_power_off(void)
 114 {
 115         mdelay(100);
 116         local_irq_disable();
 117         /* disable internal oscillator, float CS lines */
 118         PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS);
 119         /* enable wake-up on GPIO0 (Assabet...) */
 120         PWER = GFER = GRER = 1;
 121         /*
 122          * set scratchpad to zero, just in case it is used as a
 123          * restart address by the bootloader.
 124          */
 125         PSPR = 0;
 126         /* enter sleep mode */
 127         PMCR = PMCR_SF;
 128 }
 129
 130 void sa11x0_restart(char mode, const char *cmd)
 131 {
 132         if (mode == 's') {
 133                 /* Jump into ROM at address 0 */
 134                 soft_restart(0);
 135         } else {
 136                 /* Use on-chip reset capability */
 137                 RSRR = RSRR_SWR;
 138         }
 139 }
 140
 141 static void sa11x0_register_device(struct platform_device *dev, void *data)
 142 {
 143         int err;
 144         dev->dev.platform_data = data;
 145         err = platform_device_register(dev);
 146         if (err)
 147                 printk(KERN_ERR "Unable to register device %s: %d\n",
 148                         dev->name, err);
 149 }
 150
 151
 152 static struct resource sa11x0udc_resources[] = {
 153         [0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K),
 154         [1] = DEFINE_RES_IRQ(IRQ_Ser0UDC),
 155 };
 156
 157 static u64 sa11x0udc_dma_mask = 0xffffffffUL;
 158
 159 static struct platform_device sa11x0udc_device = {
 160         .name           = "sa11x0-udc",
 161         .id             = -1,
 162         .dev            = {
 163                 .dma_mask = &sa11x0udc_dma_mask,
 164                 .coherent_dma_mask = 0xffffffff,
 165         },
 166         .num_resources  = ARRAY_SIZE(sa11x0udc_resources),
 167         .resource       = sa11x0udc_resources,
 168 };
 169
 170 static struct resource sa11x0uart1_resources[] = {
 171         [0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K),
 172         [1] = DEFINE_RES_IRQ(IRQ_Ser1UART),
 173 };
 174
 175 static struct platform_device sa11x0uart1_device = {
 176         .name           = "sa11x0-uart",
 177         .id             = 1,
 178         .num_resources  = ARRAY_SIZE(sa11x0uart1_resources),
 179         .resource       = sa11x0uart1_resources,
 180 };
 181
 182 static struct resource sa11x0uart3_resources[] = {
 183         [0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K),
 184         [1] = DEFINE_RES_IRQ(IRQ_Ser3UART),
 185 };
 186
 187 static struct platform_device sa11x0uart3_device = {
 188         .name           = "sa11x0-uart",
 189         .id             = 3,
 190         .num_resources  = ARRAY_SIZE(sa11x0uart3_resources),
 191         .resource       = sa11x0uart3_resources,
 192 };
 193
 194 static struct resource sa11x0mcp_resources[] = {
 195         [0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K),
 196         [1] = DEFINE_RES_IRQ(IRQ_Ser4MCP),
 197 };
 198
 199 static u64 sa11x0mcp_dma_mask = 0xffffffffUL;
 200
 201 static struct platform_device sa11x0mcp_device = {
 202         .name           = "sa11x0-mcp",
 203         .id             = -1,
 204         .dev = {
 205                 .dma_mask = &sa11x0mcp_dma_mask,
 206                 .coherent_dma_mask = 0xffffffff,
 207         },
 208         .num_resources  = ARRAY_SIZE(sa11x0mcp_resources),
 209         .resource       = sa11x0mcp_resources,
 210 };
 211
 212 void sa11x0_register_mcp(struct mcp_plat_data *data)
 213 {
 214         sa11x0_register_device(&sa11x0mcp_device, data);
 215 }
 216
 217 static struct resource sa11x0ssp_resources[] = {
 218         [0] = DEFINE_RES_MEM(0x80070000, SZ_64K),
 219         [1] = DEFINE_RES_IRQ(IRQ_Ser4SSP),
 220 };
 221
 222 static u64 sa11x0ssp_dma_mask = 0xffffffffUL;
 223
 224 static struct platform_device sa11x0ssp_device = {
 225         .name           = "sa11x0-ssp",
 226         .id             = -1,
 227         .dev = {
 228                 .dma_mask = &sa11x0ssp_dma_mask,
 229                 .coherent_dma_mask = 0xffffffff,
 230         },
 231         .num_resources  = ARRAY_SIZE(sa11x0ssp_resources),
 232         .resource       = sa11x0ssp_resources,
 233 };
 234
 235 static struct resource sa11x0fb_resources[] = {
 236         [0] = DEFINE_RES_MEM(0xb0100000, SZ_64K),
 237         [1] = DEFINE_RES_IRQ(IRQ_LCD),
 238 };
 239
 240 static struct platform_device sa11x0fb_device = {
 241         .name           = "sa11x0-fb",
 242         .id             = -1,
 243         .dev = {
 244                 .coherent_dma_mask = 0xffffffff,
 245         },
 246         .num_resources  = ARRAY_SIZE(sa11x0fb_resources),
 247         .resource       = sa11x0fb_resources,
 248 };
 249
 250 static struct platform_device sa11x0pcmcia_device = {
 251         .name           = "sa11x0-pcmcia",
 252         .id             = -1,
 253 };
 254
 255 static struct platform_device sa11x0mtd_device = {
 256         .name           = "sa1100-mtd",
 257         .id             = -1,
 258 };
 259
 260 void sa11x0_register_mtd(struct flash_platform_data *flash,
 261                          struct resource *res, int nr)
 262 {
 263         flash->name = "sa1100";
 264         sa11x0mtd_device.resource = res;
 265         sa11x0mtd_device.num_resources = nr;
 266         sa11x0_register_device(&sa11x0mtd_device, flash);
 267 }
 268
 269 static struct resource sa11x0ir_resources[] = {
 270         DEFINE_RES_MEM(__PREG(Ser2UTCR0), 0x24),
 271         DEFINE_RES_MEM(__PREG(Ser2HSCR0), 0x1c),
 272         DEFINE_RES_MEM(__PREG(Ser2HSCR2), 0x04),
 273         DEFINE_RES_IRQ(IRQ_Ser2ICP),
 274 };
 275
 276 static struct platform_device sa11x0ir_device = {
 277         .name           = "sa11x0-ir",
 278         .id             = -1,
 279         .num_resources  = ARRAY_SIZE(sa11x0ir_resources),
 280         .resource       = sa11x0ir_resources,
 281 };
 282
 283 void sa11x0_register_irda(struct irda_platform_data *irda)
 284 {
 285         sa11x0_register_device(&sa11x0ir_device, irda);
 286 }
 287
 288 static struct platform_device sa11x0rtc_device = {
 289         .name           = "sa1100-rtc",
 290         .id             = -1,
 291 };
 292
 293 static struct resource sa11x0dma_resources[] = {
 294         DEFINE_RES_MEM(__PREG(DDAR(0)), 6 * DMASp),
 295         DEFINE_RES_IRQ(IRQ_DMA0),
 296         DEFINE_RES_IRQ(IRQ_DMA1),
 297         DEFINE_RES_IRQ(IRQ_DMA2),
 298         DEFINE_RES_IRQ(IRQ_DMA3),
 299         DEFINE_RES_IRQ(IRQ_DMA4),
 300         DEFINE_RES_IRQ(IRQ_DMA5),
 301 };
 302
 303 static u64 sa11x0dma_dma_mask = DMA_BIT_MASK(32);
 304
 305 static struct platform_device sa11x0dma_device = {
 306         .name           = "sa11x0-dma",
 307         .id             = -1,
 308         .dev = {
 309                 .dma_mask = &sa11x0dma_dma_mask,
 310                 .coherent_dma_mask = 0xffffffff,
 311         },
 312         .num_resources  = ARRAY_SIZE(sa11x0dma_resources),
 313         .resource       = sa11x0dma_resources,
 314 };
 315
 316 static struct platform_device *sa11x0_devices[] __initdata = {
 317         &sa11x0udc_device,
 318         &sa11x0uart1_device,
 319         &sa11x0uart3_device,
 320         &sa11x0ssp_device,
 321         &sa11x0pcmcia_device,
 322         &sa11x0fb_device,
 323         &sa11x0rtc_device,
 324         &sa11x0dma_device,
 325 };
 326
 327 static int __init sa1100_init(void)
 328 {
 329         pm_power_off = sa1100_power_off;
 330         return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices));
 331 }
 332
 333 arch_initcall(sa1100_init);
 334
 335 void (*sa1100fb_backlight_power)(int on);
 336 void (*sa1100fb_lcd_power)(int on);
 337
 338 EXPORT_SYMBOL(sa1100fb_backlight_power);
 339 EXPORT_SYMBOL(sa1100fb_lcd_power);
 340
 341
 342 /*
 343  * Common I/O mapping:
 344  *
 345  * Typically, static virtual address mappings are as follow:
 346  *
 347  * 0xf0000000-0xf3ffffff:       miscellaneous stuff (CPLDs, etc.)
 348  * 0xf4000000-0xf4ffffff:       SA-1111
 349  * 0xf5000000-0xf5ffffff:       reserved (used by cache flushing area)
 350  * 0xf6000000-0xfffeffff:       reserved (internal SA1100 IO defined above)
 351  * 0xffff0000-0xffff0fff:       SA1100 exception vectors
 352  * 0xffff2000-0xffff2fff:       Minicache copy_user_page area
 353  *
 354  * Below 0xe8000000 is reserved for vm allocation.
 355  *
 356  * The machine specific code must provide the extra mapping beside the
 357  * default mapping provided here.
 358  */
 359
 360 static struct map_desc standard_io_desc[] __initdata = {
 361         {       /* PCM */
 362                 .virtual        =  0xf8000000,
 363                 .pfn            = __phys_to_pfn(0x80000000),
 364                 .length         = 0x00100000,
 365                 .type           = MT_DEVICE
 366         }, {    /* SCM */
 367                 .virtual        =  0xfa000000,
 368                 .pfn            = __phys_to_pfn(0x90000000),
 369                 .length         = 0x00100000,
 370                 .type           = MT_DEVICE
 371         }, {    /* MER */
 372                 .virtual        =  0xfc000000,
 373                 .pfn            = __phys_to_pfn(0xa0000000),
 374                 .length         = 0x00100000,
 375                 .type           = MT_DEVICE
 376         }, {    /* LCD + DMA */
 377                 .virtual        =  0xfe000000,
 378                 .pfn            = __phys_to_pfn(0xb0000000),
 379                 .length         = 0x00200000,
 380                 .type           = MT_DEVICE
 381         },
 382 };
 383
 384 void __init sa1100_map_io(void)
 385 {
 386         iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
 387 }
 388
 389 /*
 390  * Disable the memory bus request/grant signals on the SA1110 to
 391  * ensure that we don't receive spurious memory requests.  We set
 392  * the MBGNT signal false to ensure the SA1111 doesn't own the
 393  * SDRAM bus.
 394  */
 395 void sa1110_mb_disable(void)
 396 {
 397         unsigned long flags;
 398
 399         local_irq_save(flags);
 400
 401         PGSR &= ~GPIO_MBGNT;
 402         GPCR = GPIO_MBGNT;
 403         GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
 404
 405         GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ);
 406
 407         local_irq_restore(flags);
 408 }
 409
 410 /*
 411  * If the system is going to use the SA-1111 DMA engines, set up
 412  * the memory bus request/grant pins.
 413  */
 414 void sa1110_mb_enable(void)
 415 {
 416         unsigned long flags;
 417
 418         local_irq_save(flags);
 419
 420         PGSR &= ~GPIO_MBGNT;
 421         GPCR = GPIO_MBGNT;
 422         GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
 423
 424         GAFR |= (GPIO_MBGNT | GPIO_MBREQ);
 425         TUCR |= TUCR_MR;
 426
 427         local_irq_restore(flags);
 428 }
 429