pinctrl: exynos: add exynos5420 SoC specific data
[deliverable/linux.git] / arch / arm / mach-shmobile / clock-r8a73a4.c
1 /*
2 * r8a73a4 clock framework support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20 #include <linux/init.h>
21 #include <linux/io.h>
22 #include <linux/kernel.h>
23 #include <linux/sh_clk.h>
24 #include <linux/clkdev.h>
25 #include <mach/common.h>
26
27 #define CPG_BASE 0xe6150000
28 #define CPG_LEN 0x270
29
30 #define MPCKCR 0xe6150080
31 #define SMSTPCR2 0xe6150138
32 #define SMSTPCR5 0xe6150144
33
34 static struct clk_mapping cpg_mapping = {
35 .phys = CPG_BASE,
36 .len = CPG_LEN,
37 };
38
39 static struct clk extalr_clk = {
40 .rate = 32768,
41 .mapping = &cpg_mapping,
42 };
43
44 static struct clk extal1_clk = {
45 .rate = 26000000,
46 .mapping = &cpg_mapping,
47 };
48
49 static struct clk extal2_clk = {
50 .rate = 48000000,
51 .mapping = &cpg_mapping,
52 };
53
54 static struct clk *main_clks[] = {
55 &extalr_clk,
56 &extal1_clk,
57 &extal2_clk,
58 };
59
60 enum {
61 MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
62 MSTP522,
63 MSTP_NR
64 };
65
66 static struct clk mstp_clks[MSTP_NR] = {
67 [MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
68 [MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
69 [MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
70 [MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
71 [MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
72 [MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */
73 [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
74 };
75
76 static struct clk_lookup lookups[] = {
77 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
78 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
79 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
80 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
81 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
82 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
83 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
84
85 /* for DT */
86 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
87 };
88
89 void __init r8a73a4_clock_init(void)
90 {
91 void __iomem *cpg_base, *reg;
92 int k, ret = 0;
93
94 /* fix MPCLK to EXTAL2 for now.
95 * this is needed until more detailed clock topology is supported
96 */
97 cpg_base = ioremap_nocache(CPG_BASE, CPG_LEN);
98 BUG_ON(!cpg_base);
99 reg = cpg_base + (MPCKCR - CPG_BASE);
100 iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */
101 iounmap(cpg_base);
102
103 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
104 ret = clk_register(main_clks[k]);
105
106 if (!ret)
107 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
108
109 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
110
111 if (!ret)
112 shmobile_clk_init();
113 else
114 panic("failed to setup r8a73a4 clocks\n");
115 }
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