arch/arm/mach-shmobile/clock-r8a73a4.c

   1 /*
   2  * r8a73a4 clock framework support
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Magnus Damm
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22 #include <linux/kernel.h>
  23 #include <linux/sh_clk.h>
  24 #include <linux/clkdev.h>
  25 #include <mach/clock.h>
  26 #include <mach/common.h>
  27
  28 #define CPG_BASE 0xe6150000
  29 #define CPG_LEN 0x270
  30
  31 #define SMSTPCR2 0xe6150138
  32 #define SMSTPCR5 0xe6150144
  33
  34 #define FRQCRA          0xE6150000
  35 #define FRQCRB          0xE6150004
  36 #define VCLKCR1         0xE6150008
  37 #define VCLKCR2         0xE615000C
  38 #define VCLKCR3         0xE615001C
  39 #define VCLKCR4         0xE6150014
  40 #define VCLKCR5         0xE6150034
  41 #define ZBCKCR          0xE6150010
  42 #define SD0CKCR         0xE6150074
  43 #define SD1CKCR         0xE6150078
  44 #define SD2CKCR         0xE615007C
  45 #define MMC0CKCR        0xE6150240
  46 #define MMC1CKCR        0xE6150244
  47 #define FSIACKCR        0xE6150018
  48 #define FSIBCKCR        0xE6150090
  49 #define MPCKCR          0xe6150080
  50 #define SPUVCKCR        0xE6150094
  51 #define HSICKCR         0xE615026C
  52 #define M4CKCR          0xE6150098
  53 #define PLLECR          0xE61500D0
  54 #define PLL1CR          0xE6150028
  55 #define PLL2CR          0xE615002C
  56 #define PLL2SCR         0xE61501F4
  57 #define PLL2HCR         0xE61501E4
  58 #define CKSCR           0xE61500C0
  59
  60 #define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base)
  61
  62 static struct clk_mapping cpg_mapping = {
  63         .phys   = CPG_BASE,
  64         .len    = CPG_LEN,
  65 };
  66
  67 static struct clk extalr_clk = {
  68         .rate   = 32768,
  69         .mapping        = &cpg_mapping,
  70 };
  71
  72 static struct clk extal1_clk = {
  73         .rate   = 26000000,
  74         .mapping        = &cpg_mapping,
  75 };
  76
  77 static struct clk extal2_clk = {
  78         .rate   = 48000000,
  79         .mapping        = &cpg_mapping,
  80 };
  81
  82 static struct sh_clk_ops followparent_clk_ops = {
  83         .recalc = followparent_recalc,
  84 };
  85
  86 static struct clk main_clk = {
  87         /* .parent will be set r8a73a4_clock_init */
  88         .ops    = &followparent_clk_ops,
  89 };
  90
  91 SH_CLK_RATIO(div2,      1, 2);
  92 SH_CLK_RATIO(div4,      1, 4);
  93
  94 SH_FIXED_RATIO_CLK(main_div2_clk,       main_clk,               div2);
  95 SH_FIXED_RATIO_CLK(extal1_div2_clk,     extal1_clk,             div2);
  96 SH_FIXED_RATIO_CLK(extal2_div2_clk,     extal2_clk,             div2);
  97 SH_FIXED_RATIO_CLK(extal2_div4_clk,     extal2_clk,             div4);
  98
  99 /* External FSIACK/FSIBCK clock */
 100 static struct clk fsiack_clk = {
 101 };
 102
 103 static struct clk fsibck_clk = {
 104 };
 105
 106 /*
 107  *              PLL clocks
 108  */
 109 static struct clk *pll_parent_main[] = {
 110         [0] = &main_clk,
 111         [1] = &main_div2_clk
 112 };
 113
 114 static struct clk *pll_parent_main_extal[8] = {
 115         [0] = &main_div2_clk,
 116         [1] = &extal2_div2_clk,
 117         [3] = &extal2_div4_clk,
 118         [4] = &main_clk,
 119         [5] = &extal2_clk,
 120 };
 121
 122 static unsigned long pll_recalc(struct clk *clk)
 123 {
 124         unsigned long mult = 1;
 125
 126         if (ioread32(CPG_MAP(PLLECR)) & (1 << clk->enable_bit))
 127                 mult = (((ioread32(clk->mapped_reg) >> 24) & 0x7f) + 1);
 128
 129         return clk->parent->rate * mult;
 130 }
 131
 132 static int pll_set_parent(struct clk *clk, struct clk *parent)
 133 {
 134         u32 val;
 135         int i, ret;
 136
 137         if (!clk->parent_table || !clk->parent_num)
 138                 return -EINVAL;
 139
 140         /* Search the parent */
 141         for (i = 0; i < clk->parent_num; i++)
 142                 if (clk->parent_table[i] == parent)
 143                         break;
 144
 145         if (i == clk->parent_num)
 146                 return -ENODEV;
 147
 148         ret = clk_reparent(clk, parent);
 149         if (ret < 0)
 150                 return ret;
 151
 152         val = ioread32(clk->mapped_reg) &
 153                 ~(((1 << clk->src_width) - 1) << clk->src_shift);
 154
 155         iowrite32(val | i << clk->src_shift, clk->mapped_reg);
 156
 157         return 0;
 158 }
 159
 160 static struct sh_clk_ops pll_clk_ops = {
 161         .recalc         = pll_recalc,
 162         .set_parent     = pll_set_parent,
 163 };
 164
 165 #define PLL_CLOCK(name, p, pt, w, s, reg, e)            \
 166         static struct clk name = {                      \
 167                 .ops            = &pll_clk_ops,         \
 168                 .flags          = CLK_ENABLE_ON_INIT,   \
 169                 .parent         = p,                    \
 170                 .parent_table   = pt,                   \
 171                 .parent_num     = ARRAY_SIZE(pt),       \
 172                 .src_width      = w,                    \
 173                 .src_shift      = s,                    \
 174                 .enable_reg     = (void __iomem *)reg,  \
 175                 .enable_bit     = e,                    \
 176                 .mapping        = &cpg_mapping,         \
 177         }
 178
 179 PLL_CLOCK(pll1_clk,  &main_clk,      pll_parent_main,       1, 7, PLL1CR,  1);
 180 PLL_CLOCK(pll2_clk,  &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR,  2);
 181 PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4);
 182 PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5);
 183
 184 SH_FIXED_RATIO_CLK(pll1_div2_clk,       pll1_clk,       div2);
 185
 186 static struct clk *main_clks[] = {
 187         &extalr_clk,
 188         &extal1_clk,
 189         &extal1_div2_clk,
 190         &extal2_clk,
 191         &extal2_div2_clk,
 192         &extal2_div4_clk,
 193         &main_clk,
 194         &main_div2_clk,
 195         &fsiack_clk,
 196         &fsibck_clk,
 197         &pll1_clk,
 198         &pll1_div2_clk,
 199         &pll2_clk,
 200         &pll2s_clk,
 201         &pll2h_clk,
 202 };
 203
 204 /* DIV4 */
 205 static void div4_kick(struct clk *clk)
 206 {
 207         unsigned long value;
 208
 209         /* set KICK bit in FRQCRB to update hardware setting */
 210         value = ioread32(CPG_MAP(FRQCRB));
 211         value |= (1 << 31);
 212         iowrite32(value, CPG_MAP(FRQCRB));
 213 }
 214
 215 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10};
 216
 217 static struct clk_div_mult_table div4_div_mult_table = {
 218         .divisors       = divisors,
 219         .nr_divisors    = ARRAY_SIZE(divisors),
 220 };
 221
 222 static struct clk_div4_table div4_table = {
 223         .div_mult_table = &div4_div_mult_table,
 224         .kick           = div4_kick,
 225 };
 226
 227 enum {
 228         DIV4_I, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
 229         DIV4_ZX, DIV4_ZS, DIV4_HP,
 230         DIV4_NR };
 231
 232 static struct clk div4_clks[DIV4_NR] = {
 233         [DIV4_I]        = SH_CLK_DIV4(&pll1_clk, FRQCRA, 20, 0x0dff, CLK_ENABLE_ON_INIT),
 234         [DIV4_M3]       = SH_CLK_DIV4(&pll1_clk, FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
 235         [DIV4_B]        = SH_CLK_DIV4(&pll1_clk, FRQCRA,  8, 0x0dff, CLK_ENABLE_ON_INIT),
 236         [DIV4_M1]       = SH_CLK_DIV4(&pll1_clk, FRQCRA,  4, 0x1dff, 0),
 237         [DIV4_M2]       = SH_CLK_DIV4(&pll1_clk, FRQCRA,  0, 0x1dff, 0),
 238         [DIV4_ZX]       = SH_CLK_DIV4(&pll1_clk, FRQCRB, 12, 0x0dff, 0),
 239         [DIV4_ZS]       = SH_CLK_DIV4(&pll1_clk, FRQCRB,  8, 0x0dff, 0),
 240         [DIV4_HP]       = SH_CLK_DIV4(&pll1_clk, FRQCRB,  4, 0x0dff, 0),
 241 };
 242
 243 enum {
 244         DIV6_ZB,
 245         DIV6_SDHI0, DIV6_SDHI1, DIV6_SDHI2,
 246         DIV6_MMC0, DIV6_MMC1,
 247         DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_VCK4, DIV6_VCK5,
 248         DIV6_FSIA, DIV6_FSIB,
 249         DIV6_MP, DIV6_M4, DIV6_HSI, DIV6_SPUV,
 250         DIV6_NR };
 251
 252 static struct clk *div6_parents[8] = {
 253         [0] = &pll1_div2_clk,
 254         [1] = &pll2s_clk,
 255         [3] = &extal2_clk,
 256         [4] = &main_div2_clk,
 257         [6] = &extalr_clk,
 258 };
 259
 260 static struct clk *fsia_parents[4] = {
 261         [0] = &pll1_div2_clk,
 262         [1] = &pll2s_clk,
 263         [2] = &fsiack_clk,
 264 };
 265
 266 static struct clk *fsib_parents[4] = {
 267         [0] = &pll1_div2_clk,
 268         [1] = &pll2s_clk,
 269         [2] = &fsibck_clk,
 270 };
 271
 272 static struct clk *mp_parents[4] = {
 273         [0] = &pll1_div2_clk,
 274         [1] = &pll2s_clk,
 275         [2] = &extal2_clk,
 276         [3] = &extal2_clk,
 277 };
 278
 279 static struct clk *m4_parents[2] = {
 280         [0] = &pll2s_clk,
 281 };
 282
 283 static struct clk *hsi_parents[4] = {
 284         [0] = &pll2h_clk,
 285         [1] = &pll1_div2_clk,
 286         [3] = &pll2s_clk,
 287 };
 288
 289 /*** FIXME ***
 290  * SH_CLK_DIV6_EXT() macro doesn't care .mapping
 291  * but, it is necessary on R-Car (= ioremap() base CPG)
 292  * The difference between
 293  * SH_CLK_DIV6_EXT() <--> SH_CLK_MAP_DIV6_EXT()
 294  * is only .mapping
 295  */
 296 #define SH_CLK_MAP_DIV6_EXT(_reg, _flags, _parents,                     \
 297                             _num_parents, _src_shift, _src_width)       \
 298 {                                                                       \
 299         .enable_reg     = (void __iomem *)_reg,                         \
 300         .enable_bit     = 0, /* unused */                               \
 301         .flags          = _flags | CLK_MASK_DIV_ON_DISABLE,             \
 302         .div_mask       = SH_CLK_DIV6_MSK,                              \
 303         .parent_table   = _parents,                                     \
 304         .parent_num     = _num_parents,                                 \
 305         .src_shift      = _src_shift,                                   \
 306         .src_width      = _src_width,                                   \
 307         .mapping        = &cpg_mapping,                                 \
 308 }
 309
 310 static struct clk div6_clks[DIV6_NR] = {
 311         [DIV6_ZB] = SH_CLK_MAP_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
 312                                 div6_parents, 2, 7, 1),
 313         [DIV6_SDHI0] = SH_CLK_MAP_DIV6_EXT(SD0CKCR, 0,
 314                                 div6_parents, 2, 6, 2),
 315         [DIV6_SDHI1] = SH_CLK_MAP_DIV6_EXT(SD1CKCR, 0,
 316                                 div6_parents, 2, 6, 2),
 317         [DIV6_SDHI2] = SH_CLK_MAP_DIV6_EXT(SD2CKCR, 0,
 318                                 div6_parents, 2, 6, 2),
 319         [DIV6_MMC0] = SH_CLK_MAP_DIV6_EXT(MMC0CKCR, 0,
 320                                 div6_parents, 2, 6, 2),
 321         [DIV6_MMC1] = SH_CLK_MAP_DIV6_EXT(MMC1CKCR, 0,
 322                                 div6_parents, 2, 6, 2),
 323         [DIV6_VCK1] = SH_CLK_MAP_DIV6_EXT(VCLKCR1, 0, /* didn't care bit[6-7] */
 324                                 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
 325         [DIV6_VCK2] = SH_CLK_MAP_DIV6_EXT(VCLKCR2, 0, /* didn't care bit[6-7] */
 326                                 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
 327         [DIV6_VCK3] = SH_CLK_MAP_DIV6_EXT(VCLKCR3, 0, /* didn't care bit[6-7] */
 328                                 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
 329         [DIV6_VCK4] = SH_CLK_MAP_DIV6_EXT(VCLKCR4, 0, /* didn't care bit[6-7] */
 330                                 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
 331         [DIV6_VCK5] = SH_CLK_MAP_DIV6_EXT(VCLKCR5, 0, /* didn't care bit[6-7] */
 332                                 div6_parents, ARRAY_SIZE(div6_parents), 12, 3),
 333         [DIV6_FSIA] = SH_CLK_MAP_DIV6_EXT(FSIACKCR, 0,
 334                                 fsia_parents, ARRAY_SIZE(fsia_parents), 6, 2),
 335         [DIV6_FSIB] = SH_CLK_MAP_DIV6_EXT(FSIBCKCR, 0,
 336                                 fsib_parents, ARRAY_SIZE(fsib_parents), 6, 2),
 337         [DIV6_MP] = SH_CLK_MAP_DIV6_EXT(MPCKCR, 0, /* it needs bit[9-11] control */
 338                                 mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
 339         /* pll2s will be selected always for M4 */
 340         [DIV6_M4] = SH_CLK_MAP_DIV6_EXT(M4CKCR, 0, /* it needs bit[9] control */
 341                                 m4_parents, ARRAY_SIZE(m4_parents), 6, 1),
 342         [DIV6_HSI] = SH_CLK_MAP_DIV6_EXT(HSICKCR, 0, /* it needs bit[9] control */
 343                                 hsi_parents, ARRAY_SIZE(hsi_parents), 6, 2),
 344         [DIV6_SPUV] = SH_CLK_MAP_DIV6_EXT(SPUVCKCR, 0,
 345                                 mp_parents, ARRAY_SIZE(mp_parents), 6, 2),
 346 };
 347
 348 /* MSTP */
 349 enum {
 350         MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
 351         MSTP522,
 352         MSTP_NR
 353 };
 354
 355 static struct clk mstp_clks[MSTP_NR] = {
 356         [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 4, 0), /* SCIFA0 */
 357         [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 3, 0), /* SCIFA1 */
 358         [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 6, 0), /* SCIFB0 */
 359         [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 7, 0), /* SCIFB1 */
 360         [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 16, 0), /* SCIFB2 */
 361         [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP],  SMSTPCR2, 17, 0), /* SCIFB3 */
 362         [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
 363 };
 364
 365 static struct clk_lookup lookups[] = {
 366         /* main clock */
 367         CLKDEV_CON_ID("extal1",                 &extal1_clk),
 368         CLKDEV_CON_ID("extal1_div2",            &extal1_div2_clk),
 369         CLKDEV_CON_ID("extal2",                 &extal2_clk),
 370         CLKDEV_CON_ID("extal2_div2",            &extal2_div2_clk),
 371         CLKDEV_CON_ID("extal2_div4",            &extal2_div4_clk),
 372         CLKDEV_CON_ID("fsiack",                 &fsiack_clk),
 373         CLKDEV_CON_ID("fsibck",                 &fsibck_clk),
 374
 375         /* pll clock */
 376         CLKDEV_CON_ID("pll1",                   &pll1_clk),
 377         CLKDEV_CON_ID("pll1_div2",              &pll1_div2_clk),
 378         CLKDEV_CON_ID("pll2",                   &pll2_clk),
 379         CLKDEV_CON_ID("pll2s",                  &pll2s_clk),
 380         CLKDEV_CON_ID("pll2h",                  &pll2h_clk),
 381
 382         /* DIV6 */
 383         CLKDEV_CON_ID("zb",                     &div6_clks[DIV6_ZB]),
 384         CLKDEV_CON_ID("sdhi0",                  &div6_clks[DIV6_SDHI0]),
 385         CLKDEV_CON_ID("sdhi1",                  &div6_clks[DIV6_SDHI1]),
 386         CLKDEV_CON_ID("sdhi2",                  &div6_clks[DIV6_SDHI2]),
 387         CLKDEV_CON_ID("mmc0",                   &div6_clks[DIV6_MMC0]),
 388         CLKDEV_CON_ID("mmc1",                   &div6_clks[DIV6_MMC1]),
 389         CLKDEV_CON_ID("vck1",                   &div6_clks[DIV6_VCK1]),
 390         CLKDEV_CON_ID("vck2",                   &div6_clks[DIV6_VCK2]),
 391         CLKDEV_CON_ID("vck3",                   &div6_clks[DIV6_VCK3]),
 392         CLKDEV_CON_ID("vck4",                   &div6_clks[DIV6_VCK4]),
 393         CLKDEV_CON_ID("vck5",                   &div6_clks[DIV6_VCK5]),
 394         CLKDEV_CON_ID("fsia",                   &div6_clks[DIV6_FSIA]),
 395         CLKDEV_CON_ID("fsib",                   &div6_clks[DIV6_FSIB]),
 396         CLKDEV_CON_ID("mp",                     &div6_clks[DIV6_MP]),
 397         CLKDEV_CON_ID("m4",                     &div6_clks[DIV6_M4]),
 398         CLKDEV_CON_ID("hsi",                    &div6_clks[DIV6_HSI]),
 399         CLKDEV_CON_ID("spuv",                   &div6_clks[DIV6_SPUV]),
 400
 401         /* MSTP */
 402         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
 403         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
 404         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
 405         CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
 406         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
 407         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
 408         CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
 409
 410         /* for DT */
 411         CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
 412 };
 413
 414 void __init r8a73a4_clock_init(void)
 415 {
 416         void __iomem *reg;
 417         int k, ret = 0;
 418         u32 ckscr;
 419
 420         reg = ioremap_nocache(CKSCR, PAGE_SIZE);
 421         BUG_ON(!reg);
 422         ckscr = ioread32(reg);
 423         iounmap(reg);
 424
 425         switch ((ckscr >> 28) & 0x3) {
 426         case 0:
 427                 main_clk.parent = &extal1_clk;
 428                 break;
 429         case 1:
 430                 main_clk.parent = &extal1_div2_clk;
 431                 break;
 432         case 2:
 433                 main_clk.parent = &extal2_clk;
 434                 break;
 435         case 3:
 436                 main_clk.parent = &extal2_div2_clk;
 437                 break;
 438         }
 439
 440         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 441                 ret = clk_register(main_clks[k]);
 442
 443         if (!ret)
 444                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 445
 446         if (!ret)
 447                 ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
 448
 449         if (!ret)
 450                 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 451
 452         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 453
 454         if (!ret)
 455                 shmobile_clk_init();
 456         else
 457                 panic("failed to setup r8a73a4 clocks\n");
 458 }