arch/arm/mach-shmobile/clock-r8a7778.c

   1 /*
   2  * r8a7778 clock framework support
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   6  *
   7  * based on r8a7779
   8  *
   9  * Copyright (C) 2011  Renesas Solutions Corp.
  10  * Copyright (C) 2011  Magnus Damm
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  24  */
  25
  26 /*
  27  *     MD      MD      MD      MD       PLLA   PLLB    EXTAL   clki    clkz
  28  *     19      18      12      11                      (HMz)   (MHz)   (MHz)
  29  *----------------------------------------------------------------------------
  30  *     1       0       0       0       x21     x21     38.00   800     800
  31  *     1       0       0       1       x24     x24     33.33   800     800
  32  *     1       0       1       0       x28     x28     28.50   800     800
  33  *     1       0       1       1       x32     x32     25.00   800     800
  34  *     1       1       0       1       x24     x21     33.33   800     700
  35  *     1       1       1       0       x28     x21     28.50   800     600
  36  *     1       1       1       1       x32     x24     25.00   800     600
  37  */
  38
  39 #include <linux/io.h>
  40 #include <linux/sh_clk.h>
  41 #include <linux/clkdev.h>
  42 #include <mach/clock.h>
  43 #include <mach/common.h>
  44
  45 #define MSTPCR0         IOMEM(0xffc80030)
  46 #define MSTPCR1         IOMEM(0xffc80034)
  47 #define MSTPCR3         IOMEM(0xffc8003c)
  48 #define MSTPSR1         IOMEM(0xffc80044)
  49 #define MSTPSR4         IOMEM(0xffc80048)
  50 #define MSTPSR6         IOMEM(0xffc8004c)
  51 #define MSTPCR4         IOMEM(0xffc80050)
  52 #define MSTPCR5         IOMEM(0xffc80054)
  53 #define MSTPCR6         IOMEM(0xffc80058)
  54 #define MODEMR          0xFFCC0020
  55
  56 #define MD(nr)  BIT(nr)
  57
  58 /* ioremap() through clock mapping mandatory to avoid
  59  * collision with ARM coherent DMA virtual memory range.
  60  */
  61
  62 static struct clk_mapping cpg_mapping = {
  63         .phys   = 0xffc80000,
  64         .len    = 0x80,
  65 };
  66
  67 static struct clk extal_clk = {
  68         /* .rate will be updated on r8a7778_clock_init() */
  69         .mapping = &cpg_mapping,
  70 };
  71
  72 /*
  73  * clock ratio of these clock will be updated
  74  * on r8a7778_clock_init()
  75  */
  76 SH_FIXED_RATIO_CLK_SET(plla_clk,        extal_clk, 1, 1);
  77 SH_FIXED_RATIO_CLK_SET(pllb_clk,        extal_clk, 1, 1);
  78 SH_FIXED_RATIO_CLK_SET(i_clk,           plla_clk,  1, 1);
  79 SH_FIXED_RATIO_CLK_SET(s_clk,           plla_clk,  1, 1);
  80 SH_FIXED_RATIO_CLK_SET(s1_clk,          plla_clk,  1, 1);
  81 SH_FIXED_RATIO_CLK_SET(s3_clk,          plla_clk,  1, 1);
  82 SH_FIXED_RATIO_CLK_SET(s4_clk,          plla_clk,  1, 1);
  83 SH_FIXED_RATIO_CLK_SET(b_clk,           plla_clk,  1, 1);
  84 SH_FIXED_RATIO_CLK_SET(out_clk,         plla_clk,  1, 1);
  85 SH_FIXED_RATIO_CLK_SET(p_clk,           plla_clk,  1, 1);
  86 SH_FIXED_RATIO_CLK_SET(g_clk,           plla_clk,  1, 1);
  87 SH_FIXED_RATIO_CLK_SET(z_clk,           pllb_clk,  1, 1);
  88
  89 static struct clk *main_clks[] = {
  90         &extal_clk,
  91         &plla_clk,
  92         &pllb_clk,
  93         &i_clk,
  94         &s_clk,
  95         &s1_clk,
  96         &s3_clk,
  97         &s4_clk,
  98         &b_clk,
  99         &out_clk,
 100         &p_clk,
 101         &g_clk,
 102         &z_clk,
 103 };
 104
 105 enum {
 106         MSTP323, MSTP322, MSTP321,
 107         MSTP114,
 108         MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
 109         MSTP016, MSTP015,
 110         MSTP_NR };
 111
 112 static struct clk mstp_clks[MSTP_NR] = {
 113         [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */
 114         [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */
 115         [MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */
 116         [MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */
 117         [MSTP026] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 26, 0), /* SCIF0 */
 118         [MSTP025] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 25, 0), /* SCIF1 */
 119         [MSTP024] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 24, 0), /* SCIF2 */
 120         [MSTP023] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 23, 0), /* SCIF3 */
 121         [MSTP022] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 22, 0), /* SCIF4 */
 122         [MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */
 123         [MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */
 124         [MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */
 125 };
 126
 127 static struct clk_lookup lookups[] = {
 128         /* MSTP32 clocks */
 129         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
 130         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
 131         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
 132         CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP114]), /* Ether */
 133         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
 134         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
 135         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
 136         CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
 137         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
 138         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
 139         CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
 140         CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */
 141 };
 142
 143 void __init r8a7778_clock_init(void)
 144 {
 145         void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
 146         u32 mode;
 147         int k, ret = 0;
 148
 149         BUG_ON(!modemr);
 150         mode = ioread32(modemr);
 151         iounmap(modemr);
 152
 153         switch (mode & (MD(19) | MD(18) | MD(12) | MD(11))) {
 154         case MD(19):
 155                 extal_clk.rate = 38000000;
 156                 SH_CLK_SET_RATIO(&plla_clk_ratio,       21, 1);
 157                 SH_CLK_SET_RATIO(&pllb_clk_ratio,       21, 1);
 158                 break;
 159         case MD(19) | MD(11):
 160                 extal_clk.rate = 33333333;
 161                 SH_CLK_SET_RATIO(&plla_clk_ratio,       24, 1);
 162                 SH_CLK_SET_RATIO(&pllb_clk_ratio,       24, 1);
 163                 break;
 164         case MD(19) | MD(12):
 165                 extal_clk.rate = 28500000;
 166                 SH_CLK_SET_RATIO(&plla_clk_ratio,       28, 1);
 167                 SH_CLK_SET_RATIO(&pllb_clk_ratio,       28, 1);
 168                 break;
 169         case MD(19) | MD(12) | MD(11):
 170                 extal_clk.rate = 25000000;
 171                 SH_CLK_SET_RATIO(&plla_clk_ratio,       32, 1);
 172                 SH_CLK_SET_RATIO(&pllb_clk_ratio,       32, 1);
 173                 break;
 174         case MD(19) | MD(18) | MD(11):
 175                 extal_clk.rate = 33333333;
 176                 SH_CLK_SET_RATIO(&plla_clk_ratio,       24, 1);
 177                 SH_CLK_SET_RATIO(&pllb_clk_ratio,       21, 1);
 178                 break;
 179         case MD(19) | MD(18) | MD(12):
 180                 extal_clk.rate = 28500000;
 181                 SH_CLK_SET_RATIO(&plla_clk_ratio,       28, 1);
 182                 SH_CLK_SET_RATIO(&pllb_clk_ratio,       21, 1);
 183                 break;
 184         case MD(19) | MD(18) | MD(12) | MD(11):
 185                 extal_clk.rate = 25000000;
 186                 SH_CLK_SET_RATIO(&plla_clk_ratio,       32, 1);
 187                 SH_CLK_SET_RATIO(&pllb_clk_ratio,       24, 1);
 188                 break;
 189         default:
 190                 BUG();
 191         }
 192
 193         if (mode & MD(1)) {
 194                 SH_CLK_SET_RATIO(&i_clk_ratio,  1, 1);
 195                 SH_CLK_SET_RATIO(&s_clk_ratio,  1, 3);
 196                 SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 6);
 197                 SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4);
 198                 SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8);
 199                 SH_CLK_SET_RATIO(&p_clk_ratio,  1, 12);
 200                 SH_CLK_SET_RATIO(&g_clk_ratio,  1, 12);
 201                 if (mode & MD(2)) {
 202                         SH_CLK_SET_RATIO(&b_clk_ratio,          1, 18);
 203                         SH_CLK_SET_RATIO(&out_clk_ratio,        1, 18);
 204                 } else {
 205                         SH_CLK_SET_RATIO(&b_clk_ratio,          1, 12);
 206                         SH_CLK_SET_RATIO(&out_clk_ratio,        1, 12);
 207                 }
 208         } else {
 209                 SH_CLK_SET_RATIO(&i_clk_ratio,  1, 1);
 210                 SH_CLK_SET_RATIO(&s_clk_ratio,  1, 4);
 211                 SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 8);
 212                 SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4);
 213                 SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8);
 214                 SH_CLK_SET_RATIO(&p_clk_ratio,  1, 16);
 215                 SH_CLK_SET_RATIO(&g_clk_ratio,  1, 12);
 216                 if (mode & MD(2)) {
 217                         SH_CLK_SET_RATIO(&b_clk_ratio,          1, 16);
 218                         SH_CLK_SET_RATIO(&out_clk_ratio,        1, 16);
 219                 } else {
 220                         SH_CLK_SET_RATIO(&b_clk_ratio,          1, 12);
 221                         SH_CLK_SET_RATIO(&out_clk_ratio,        1, 12);
 222                 }
 223         }
 224
 225         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 226                 ret = clk_register(main_clks[k]);
 227
 228         if (!ret)
 229                 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 230
 231         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 232
 233         if (!ret)
 234                 shmobile_clk_init();
 235         else
 236                 panic("failed to setup r8a7778 clocks\n");
 237 }