2 * r8a7790 clock framework support
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/sh_clk.h>
24 #include <linux/clkdev.h>
25 #include <mach/clock.h>
26 #include <mach/common.h>
29 * MD EXTAL PLL0 PLL1 PLL3
30 * 14 13 19 (MHz) *1 *1
31 *---------------------------------------------------
32 * 0 0 0 15 x 1 x172/2 x208/2 x106
33 * 0 0 1 15 x 1 x172/2 x208/2 x88
34 * 0 1 0 20 x 1 x130/2 x156/2 x80
35 * 0 1 1 20 x 1 x130/2 x156/2 x66
36 * 1 0 0 26 / 2 x200/2 x240/2 x122
37 * 1 0 1 26 / 2 x200/2 x240/2 x102
38 * 1 1 0 30 / 2 x172/2 x208/2 x106
39 * 1 1 1 30 / 2 x172/2 x208/2 x88
41 * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
42 * see "p1 / 2" on R8A7790_CLOCK_ROOT() below
45 #define MD(nr) (1 << nr)
47 #define CPG_BASE 0xe6150000
48 #define CPG_LEN 0x1000
50 #define SMSTPCR2 0xe6150138
51 #define SMSTPCR3 0xe615013c
52 #define SMSTPCR7 0xe615014c
54 #define MODEMR 0xE6160060
55 #define SDCKCR 0xE6150074
56 #define SD2CKCR 0xE6150078
57 #define SD3CKCR 0xE615007C
58 #define MMC0CKCR 0xE6150240
59 #define MMC1CKCR 0xE6150244
60 #define SSPCKCR 0xE6150248
61 #define SSPRSCKCR 0xE615024C
63 static struct clk_mapping cpg_mapping
= {
68 static struct clk extal_clk
= {
69 /* .rate will be updated on r8a7790_clock_init() */
70 .mapping
= &cpg_mapping
,
73 static struct sh_clk_ops followparent_clk_ops
= {
74 .recalc
= followparent_recalc
,
77 static struct clk main_clk
= {
78 /* .parent will be set r8a73a4_clock_init */
79 .ops
= &followparent_clk_ops
,
83 * clock ratio of these clock will be updated
84 * on r8a7790_clock_init()
86 SH_FIXED_RATIO_CLK_SET(pll1_clk
, main_clk
, 1, 1);
87 SH_FIXED_RATIO_CLK_SET(pll3_clk
, main_clk
, 1, 1);
88 SH_FIXED_RATIO_CLK_SET(lb_clk
, pll1_clk
, 1, 1);
89 SH_FIXED_RATIO_CLK_SET(qspi_clk
, pll1_clk
, 1, 1);
91 /* fixed ratio clock */
92 SH_FIXED_RATIO_CLK_SET(extal_div2_clk
, extal_clk
, 1, 2);
93 SH_FIXED_RATIO_CLK_SET(cp_clk
, extal_clk
, 1, 2);
95 SH_FIXED_RATIO_CLK_SET(pll1_div2_clk
, pll1_clk
, 1, 2);
96 SH_FIXED_RATIO_CLK_SET(zg_clk
, pll1_clk
, 1, 3);
97 SH_FIXED_RATIO_CLK_SET(zx_clk
, pll1_clk
, 1, 3);
98 SH_FIXED_RATIO_CLK_SET(zs_clk
, pll1_clk
, 1, 6);
99 SH_FIXED_RATIO_CLK_SET(hp_clk
, pll1_clk
, 1, 12);
100 SH_FIXED_RATIO_CLK_SET(i_clk
, pll1_clk
, 1, 2);
101 SH_FIXED_RATIO_CLK_SET(b_clk
, pll1_clk
, 1, 12);
102 SH_FIXED_RATIO_CLK_SET(p_clk
, pll1_clk
, 1, 24);
103 SH_FIXED_RATIO_CLK_SET(cl_clk
, pll1_clk
, 1, 48);
104 SH_FIXED_RATIO_CLK_SET(m2_clk
, pll1_clk
, 1, 8);
105 SH_FIXED_RATIO_CLK_SET(imp_clk
, pll1_clk
, 1, 4);
106 SH_FIXED_RATIO_CLK_SET(rclk_clk
, pll1_clk
, 1, (48 * 1024));
107 SH_FIXED_RATIO_CLK_SET(oscclk_clk
, pll1_clk
, 1, (12 * 1024));
109 SH_FIXED_RATIO_CLK_SET(zb3_clk
, pll3_clk
, 1, 4);
110 SH_FIXED_RATIO_CLK_SET(zb3d2_clk
, pll3_clk
, 1, 8);
111 SH_FIXED_RATIO_CLK_SET(ddr_clk
, pll3_clk
, 1, 8);
112 SH_FIXED_RATIO_CLK_SET(mp_clk
, pll1_div2_clk
, 1, 15);
114 static struct clk
*main_clks
[] = {
142 /* SDHI (DIV4) clock */
143 static int divisors
[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
145 static struct clk_div_mult_table div4_div_mult_table
= {
146 .divisors
= divisors
,
147 .nr_divisors
= ARRAY_SIZE(divisors
),
150 static struct clk_div4_table div4_table
= {
151 .div_mult_table
= &div4_div_mult_table
,
155 DIV4_SDH
, DIV4_SD0
, DIV4_SD1
, DIV4_NR
158 static struct clk div4_clks
[DIV4_NR
] = {
159 [DIV4_SDH
] = SH_CLK_DIV4(&pll1_clk
, SDCKCR
, 8, 0x0dff, CLK_ENABLE_ON_INIT
),
160 [DIV4_SD0
] = SH_CLK_DIV4(&pll1_clk
, SDCKCR
, 4, 0x1de0, CLK_ENABLE_ON_INIT
),
161 [DIV4_SD1
] = SH_CLK_DIV4(&pll1_clk
, SDCKCR
, 0, 0x1de0, CLK_ENABLE_ON_INIT
),
167 DIV6_MMC0
, DIV6_MMC1
,
168 DIV6_SSP
, DIV6_SSPRS
,
172 static struct clk div6_clks
[DIV6_NR
] = {
173 [DIV6_SD2
] = SH_CLK_DIV6(&pll1_div2_clk
, SD2CKCR
, 0),
174 [DIV6_SD3
] = SH_CLK_DIV6(&pll1_div2_clk
, SD3CKCR
, 0),
175 [DIV6_MMC0
] = SH_CLK_DIV6(&pll1_div2_clk
, MMC0CKCR
, 0),
176 [DIV6_MMC1
] = SH_CLK_DIV6(&pll1_div2_clk
, MMC1CKCR
, 0),
177 [DIV6_SSP
] = SH_CLK_DIV6(&pll1_div2_clk
, SSPCKCR
, 0),
178 [DIV6_SSPRS
] = SH_CLK_DIV6(&pll1_div2_clk
, SSPRSCKCR
, 0),
185 MSTP216
, MSTP207
, MSTP206
, MSTP204
, MSTP203
, MSTP202
,
189 static struct clk mstp_clks
[MSTP_NR
] = {
190 [MSTP721
] = SH_CLK_MSTP32(&p_clk
, SMSTPCR7
, 21, 0), /* SCIF0 */
191 [MSTP720
] = SH_CLK_MSTP32(&p_clk
, SMSTPCR7
, 20, 0), /* SCIF1 */
192 [MSTP304
] = SH_CLK_MSTP32(&cp_clk
, SMSTPCR3
, 4, 0), /* TPU0 */
193 [MSTP216
] = SH_CLK_MSTP32(&mp_clk
, SMSTPCR2
, 16, 0), /* SCIFB2 */
194 [MSTP207
] = SH_CLK_MSTP32(&mp_clk
, SMSTPCR2
, 7, 0), /* SCIFB1 */
195 [MSTP206
] = SH_CLK_MSTP32(&mp_clk
, SMSTPCR2
, 6, 0), /* SCIFB0 */
196 [MSTP204
] = SH_CLK_MSTP32(&mp_clk
, SMSTPCR2
, 4, 0), /* SCIFA0 */
197 [MSTP203
] = SH_CLK_MSTP32(&mp_clk
, SMSTPCR2
, 3, 0), /* SCIFA1 */
198 [MSTP202
] = SH_CLK_MSTP32(&mp_clk
, SMSTPCR2
, 2, 0), /* SCIFA2 */
201 static struct clk_lookup lookups
[] = {
204 CLKDEV_CON_ID("extal", &extal_clk
),
205 CLKDEV_CON_ID("extal_div2", &extal_div2_clk
),
206 CLKDEV_CON_ID("main", &main_clk
),
207 CLKDEV_CON_ID("pll1", &pll1_clk
),
208 CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk
),
209 CLKDEV_CON_ID("pll3", &pll3_clk
),
210 CLKDEV_CON_ID("zg", &zg_clk
),
211 CLKDEV_CON_ID("zx", &zx_clk
),
212 CLKDEV_CON_ID("zs", &zs_clk
),
213 CLKDEV_CON_ID("hp", &hp_clk
),
214 CLKDEV_CON_ID("i", &i_clk
),
215 CLKDEV_CON_ID("b", &b_clk
),
216 CLKDEV_CON_ID("lb", &lb_clk
),
217 CLKDEV_CON_ID("p", &p_clk
),
218 CLKDEV_CON_ID("cl", &cl_clk
),
219 CLKDEV_CON_ID("m2", &m2_clk
),
220 CLKDEV_CON_ID("imp", &imp_clk
),
221 CLKDEV_CON_ID("rclk", &rclk_clk
),
222 CLKDEV_CON_ID("oscclk", &oscclk_clk
),
223 CLKDEV_CON_ID("zb3", &zb3_clk
),
224 CLKDEV_CON_ID("zb3d2", &zb3d2_clk
),
225 CLKDEV_CON_ID("ddr", &ddr_clk
),
226 CLKDEV_CON_ID("mp", &mp_clk
),
227 CLKDEV_CON_ID("qspi", &qspi_clk
),
228 CLKDEV_CON_ID("cp", &cp_clk
),
231 CLKDEV_CON_ID("sdh", &div4_clks
[DIV4_SDH
]),
232 CLKDEV_CON_ID("sd0", &div4_clks
[DIV4_SD0
]),
233 CLKDEV_CON_ID("sd1", &div4_clks
[DIV4_SD1
]),
236 CLKDEV_CON_ID("sd2", &div6_clks
[DIV6_SD2
]),
237 CLKDEV_CON_ID("sd3", &div6_clks
[DIV6_SD3
]),
238 CLKDEV_CON_ID("mmc0", &div6_clks
[DIV6_MMC0
]),
239 CLKDEV_CON_ID("mmc1", &div6_clks
[DIV6_MMC1
]),
240 CLKDEV_CON_ID("ssp", &div6_clks
[DIV6_SSP
]),
241 CLKDEV_CON_ID("ssprs", &div6_clks
[DIV6_SSPRS
]),
244 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks
[MSTP204
]),
245 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks
[MSTP203
]),
246 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks
[MSTP206
]),
247 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks
[MSTP207
]),
248 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks
[MSTP216
]),
249 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks
[MSTP202
]),
250 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks
[MSTP721
]),
251 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks
[MSTP720
]),
254 #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
255 extal_clk.rate = e * 1000 * 1000; \
256 main_clk.parent = m; \
257 SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1); \
259 SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1); \
261 SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
264 void __init
r8a7790_clock_init(void)
266 void __iomem
*modemr
= ioremap_nocache(MODEMR
, PAGE_SIZE
);
271 mode
= ioread32(modemr
);
274 switch (mode
& (MD(14) | MD(13))) {
276 R8A7790_CLOCK_ROOT(15, &extal_clk
, 172, 208, 106, 88);
279 R8A7790_CLOCK_ROOT(20, &extal_clk
, 130, 156, 80, 66);
282 R8A7790_CLOCK_ROOT(26, &extal_div2_clk
, 200, 240, 122, 102);
284 case MD(13) | MD(14):
285 R8A7790_CLOCK_ROOT(30, &extal_div2_clk
, 172, 208, 106, 88);
290 SH_CLK_SET_RATIO(&lb_clk_ratio
, 1, 36);
292 SH_CLK_SET_RATIO(&lb_clk_ratio
, 1, 24);
294 if ((mode
& (MD(3) | MD(2) | MD(1))) == MD(2))
295 SH_CLK_SET_RATIO(&qspi_clk_ratio
, 1, 16);
297 SH_CLK_SET_RATIO(&qspi_clk_ratio
, 1, 20);
299 for (k
= 0; !ret
&& (k
< ARRAY_SIZE(main_clks
)); k
++)
300 ret
= clk_register(main_clks
[k
]);
303 ret
= sh_clk_div4_register(div4_clks
, DIV4_NR
, &div4_table
);
306 ret
= sh_clk_div6_register(div6_clks
, DIV6_NR
);
309 ret
= sh_clk_mstp_register(mstp_clks
, MSTP_NR
);
311 clkdev_add_table(lookups
, ARRAY_SIZE(lookups
));
316 panic("failed to setup r8a7790 clocks\n");