arch/arm/mach-shmobile/clock-r8a7790.c

   1 /*
   2  * r8a7790 clock framework support
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Magnus Damm
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16 #include <linux/init.h>
  17 #include <linux/io.h>
  18 #include <linux/kernel.h>
  19 #include <linux/sh_clk.h>
  20 #include <linux/clkdev.h>
  21
  22 #include "clock.h"
  23 #include "common.h"
  24 #include "r8a7790.h"
  25 #include "rcar-gen2.h"
  26
  27 /*
  28  *   MD         EXTAL           PLL0    PLL1    PLL3
  29  * 14 13 19     (MHz)           *1      *1
  30  *---------------------------------------------------
  31  * 0  0  0      15 x 1          x172/2  x208/2  x106
  32  * 0  0  1      15 x 1          x172/2  x208/2  x88
  33  * 0  1  0      20 x 1          x130/2  x156/2  x80
  34  * 0  1  1      20 x 1          x130/2  x156/2  x66
  35  * 1  0  0      26 / 2          x200/2  x240/2  x122
  36  * 1  0  1      26 / 2          x200/2  x240/2  x102
  37  * 1  1  0      30 / 2          x172/2  x208/2  x106
  38  * 1  1  1      30 / 2          x172/2  x208/2  x88
  39  *
  40  * *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
  41  *      see "p1 / 2" on R8A7790_CLOCK_ROOT() below
  42  */
  43
  44 #define CPG_BASE        0xe6150000
  45 #define CPG_LEN         0x1000
  46
  47 #define SMSTPCR1        0xe6150134
  48 #define SMSTPCR2        0xe6150138
  49 #define SMSTPCR3        0xe615013c
  50 #define SMSTPCR5        0xe6150144
  51 #define SMSTPCR7        0xe615014c
  52 #define SMSTPCR8        0xe6150990
  53 #define SMSTPCR9        0xe6150994
  54 #define SMSTPCR10       0xe6150998
  55
  56 #define MSTPSR1         IOMEM(0xe6150038)
  57 #define MSTPSR2         IOMEM(0xe6150040)
  58 #define MSTPSR3         IOMEM(0xe6150048)
  59 #define MSTPSR5         IOMEM(0xe615003c)
  60 #define MSTPSR7         IOMEM(0xe61501c4)
  61 #define MSTPSR8         IOMEM(0xe61509a0)
  62 #define MSTPSR9         IOMEM(0xe61509a4)
  63 #define MSTPSR10        IOMEM(0xe61509a8)
  64
  65 #define SDCKCR          0xE6150074
  66 #define SD2CKCR         0xE6150078
  67 #define SD3CKCR         0xE615026C
  68 #define MMC0CKCR        0xE6150240
  69 #define MMC1CKCR        0xE6150244
  70 #define SSPCKCR         0xE6150248
  71 #define SSPRSCKCR       0xE615024C
  72
  73 static struct clk_mapping cpg_mapping = {
  74         .phys   = CPG_BASE,
  75         .len    = CPG_LEN,
  76 };
  77
  78 static struct clk extal_clk = {
  79         /* .rate will be updated on r8a7790_clock_init() */
  80         .mapping        = &cpg_mapping,
  81 };
  82
  83 static struct sh_clk_ops followparent_clk_ops = {
  84         .recalc = followparent_recalc,
  85 };
  86
  87 static struct clk main_clk = {
  88         /* .parent will be set r8a7790_clock_init */
  89         .ops    = &followparent_clk_ops,
  90 };
  91
  92 static struct clk audio_clk_a = {
  93 };
  94
  95 static struct clk audio_clk_b = {
  96 };
  97
  98 static struct clk audio_clk_c = {
  99 };
 100
 101 /*
 102  * clock ratio of these clock will be updated
 103  * on r8a7790_clock_init()
 104  */
 105 SH_FIXED_RATIO_CLK_SET(pll1_clk,                main_clk,       1, 1);
 106 SH_FIXED_RATIO_CLK_SET(pll3_clk,                main_clk,       1, 1);
 107 SH_FIXED_RATIO_CLK_SET(lb_clk,                  pll1_clk,       1, 1);
 108 SH_FIXED_RATIO_CLK_SET(qspi_clk,                pll1_clk,       1, 1);
 109
 110 /* fixed ratio clock */
 111 SH_FIXED_RATIO_CLK_SET(extal_div2_clk,          extal_clk,      1, 2);
 112 SH_FIXED_RATIO_CLK_SET(cp_clk,                  extal_clk,      1, 2);
 113
 114 SH_FIXED_RATIO_CLK_SET(pll1_div2_clk,           pll1_clk,       1, 2);
 115 SH_FIXED_RATIO_CLK_SET(zg_clk,                  pll1_clk,       1, 3);
 116 SH_FIXED_RATIO_CLK_SET(zx_clk,                  pll1_clk,       1, 3);
 117 SH_FIXED_RATIO_CLK_SET(zs_clk,                  pll1_clk,       1, 6);
 118 SH_FIXED_RATIO_CLK_SET(hp_clk,                  pll1_clk,       1, 12);
 119 SH_FIXED_RATIO_CLK_SET(i_clk,                   pll1_clk,       1, 2);
 120 SH_FIXED_RATIO_CLK_SET(b_clk,                   pll1_clk,       1, 12);
 121 SH_FIXED_RATIO_CLK_SET(p_clk,                   pll1_clk,       1, 24);
 122 SH_FIXED_RATIO_CLK_SET(cl_clk,                  pll1_clk,       1, 48);
 123 SH_FIXED_RATIO_CLK_SET(m2_clk,                  pll1_clk,       1, 8);
 124 SH_FIXED_RATIO_CLK_SET(imp_clk,                 pll1_clk,       1, 4);
 125 SH_FIXED_RATIO_CLK_SET(rclk_clk,                pll1_clk,       1, (48 * 1024));
 126 SH_FIXED_RATIO_CLK_SET(oscclk_clk,              pll1_clk,       1, (12 * 1024));
 127
 128 SH_FIXED_RATIO_CLK_SET(zb3_clk,                 pll3_clk,       1, 4);
 129 SH_FIXED_RATIO_CLK_SET(zb3d2_clk,               pll3_clk,       1, 8);
 130 SH_FIXED_RATIO_CLK_SET(ddr_clk,                 pll3_clk,       1, 8);
 131 SH_FIXED_RATIO_CLK_SET(mp_clk,                  pll1_div2_clk,  1, 15);
 132
 133 static struct clk *main_clks[] = {
 134         &audio_clk_a,
 135         &audio_clk_b,
 136         &audio_clk_c,
 137         &extal_clk,
 138         &extal_div2_clk,
 139         &main_clk,
 140         &pll1_clk,
 141         &pll1_div2_clk,
 142         &pll3_clk,
 143         &lb_clk,
 144         &qspi_clk,
 145         &zg_clk,
 146         &zx_clk,
 147         &zs_clk,
 148         &hp_clk,
 149         &i_clk,
 150         &b_clk,
 151         &p_clk,
 152         &cl_clk,
 153         &m2_clk,
 154         &imp_clk,
 155         &rclk_clk,
 156         &oscclk_clk,
 157         &zb3_clk,
 158         &zb3d2_clk,
 159         &ddr_clk,
 160         &mp_clk,
 161         &cp_clk,
 162 };
 163
 164 /* SDHI (DIV4) clock */
 165 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
 166
 167 static struct clk_div_mult_table div4_div_mult_table = {
 168         .divisors = divisors,
 169         .nr_divisors = ARRAY_SIZE(divisors),
 170 };
 171
 172 static struct clk_div4_table div4_table = {
 173         .div_mult_table = &div4_div_mult_table,
 174 };
 175
 176 enum {
 177         DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR
 178 };
 179
 180 static struct clk div4_clks[DIV4_NR] = {
 181         [DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
 182         [DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
 183         [DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1df0, CLK_ENABLE_ON_INIT),
 184 };
 185
 186 /* DIV6 clocks */
 187 enum {
 188         DIV6_SD2, DIV6_SD3,
 189         DIV6_MMC0, DIV6_MMC1,
 190         DIV6_SSP, DIV6_SSPRS,
 191         DIV6_NR
 192 };
 193
 194 static struct clk div6_clks[DIV6_NR] = {
 195         [DIV6_SD2]      = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
 196         [DIV6_SD3]      = SH_CLK_DIV6(&pll1_div2_clk, SD3CKCR, 0),
 197         [DIV6_MMC0]     = SH_CLK_DIV6(&pll1_div2_clk, MMC0CKCR, 0),
 198         [DIV6_MMC1]     = SH_CLK_DIV6(&pll1_div2_clk, MMC1CKCR, 0),
 199         [DIV6_SSP]      = SH_CLK_DIV6(&pll1_div2_clk, SSPCKCR, 0),
 200         [DIV6_SSPRS]    = SH_CLK_DIV6(&pll1_div2_clk, SSPRSCKCR, 0),
 201 };
 202
 203 /* MSTP */
 204 enum {
 205         MSTP1017, /* parent of SCU */
 206
 207         MSTP1031, MSTP1030,
 208         MSTP1029, MSTP1028, MSTP1027, MSTP1026, MSTP1025, MSTP1024, MSTP1023, MSTP1022,
 209         MSTP1015, MSTP1014, MSTP1013, MSTP1012, MSTP1011, MSTP1010,
 210         MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005,
 211         MSTP931, MSTP930, MSTP929, MSTP928,
 212         MSTP917,
 213         MSTP815, MSTP814,
 214         MSTP813,
 215         MSTP811, MSTP810, MSTP809, MSTP808,
 216         MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
 217         MSTP717, MSTP716,
 218         MSTP704, MSTP703,
 219         MSTP522,
 220         MSTP502, MSTP501,
 221         MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
 222         MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
 223         MSTP124,
 224         MSTP_NR
 225 };
 226
 227 static struct clk mstp_clks[MSTP_NR] = {
 228         [MSTP1031] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 31, MSTPSR10, 0), /* SCU0 */
 229         [MSTP1030] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 30, MSTPSR10, 0), /* SCU1 */
 230         [MSTP1029] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 29, MSTPSR10, 0), /* SCU2 */
 231         [MSTP1028] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 28, MSTPSR10, 0), /* SCU3 */
 232         [MSTP1027] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 27, MSTPSR10, 0), /* SCU4 */
 233         [MSTP1026] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 26, MSTPSR10, 0), /* SCU5 */
 234         [MSTP1025] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 25, MSTPSR10, 0), /* SCU6 */
 235         [MSTP1024] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 24, MSTPSR10, 0), /* SCU7 */
 236         [MSTP1023] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 23, MSTPSR10, 0), /* SCU8 */
 237         [MSTP1022] = SH_CLK_MSTP32_STS(&mstp_clks[MSTP1017], SMSTPCR10, 22, MSTPSR10, 0), /* SCU9 */
 238         [MSTP1017] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 17, MSTPSR10, 0), /* SCU */
 239         [MSTP1015] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 15, MSTPSR10, 0), /* SSI0 */
 240         [MSTP1014] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 14, MSTPSR10, 0), /* SSI1 */
 241         [MSTP1013] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 13, MSTPSR10, 0), /* SSI2 */
 242         [MSTP1012] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 12, MSTPSR10, 0), /* SSI3 */
 243         [MSTP1011] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 11, MSTPSR10, 0), /* SSI4 */
 244         [MSTP1010] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 10, MSTPSR10, 0), /* SSI5 */
 245         [MSTP1009] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 9, MSTPSR10, 0), /* SSI6 */
 246         [MSTP1008] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 8, MSTPSR10, 0), /* SSI7 */
 247         [MSTP1007] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 7, MSTPSR10, 0), /* SSI8 */
 248         [MSTP1006] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 6, MSTPSR10, 0), /* SSI9 */
 249         [MSTP1005] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 5, MSTPSR10, 0), /* SSI ALL */
 250         [MSTP931] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
 251         [MSTP930] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
 252         [MSTP929] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
 253         [MSTP928] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
 254         [MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
 255         [MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
 256         [MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
 257         [MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
 258         [MSTP811] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 11, MSTPSR8, 0), /* VIN0 */
 259         [MSTP810] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8, 10, MSTPSR8, 0), /* VIN1 */
 260         [MSTP809] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8,  9, MSTPSR8, 0), /* VIN2 */
 261         [MSTP808] = SH_CLK_MSTP32_STS(&zg_clk, SMSTPCR8,  8, MSTPSR8, 0), /* VIN3 */
 262         [MSTP726] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 26, MSTPSR7, 0), /* LVDS0 */
 263         [MSTP725] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 25, MSTPSR7, 0), /* LVDS1 */
 264         [MSTP724] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 24, MSTPSR7, 0), /* DU0 */
 265         [MSTP723] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 23, MSTPSR7, 0), /* DU1 */
 266         [MSTP722] = SH_CLK_MSTP32_STS(&zx_clk, SMSTPCR7, 22, MSTPSR7, 0), /* DU2 */
 267         [MSTP721] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 21, MSTPSR7, 0), /* SCIF0 */
 268         [MSTP720] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 20, MSTPSR7, 0), /* SCIF1 */
 269         [MSTP717] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 17, MSTPSR7, 0), /* HSCIF0 */
 270         [MSTP716] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR7, 16, MSTPSR7, 0), /* HSCIF1 */
 271         [MSTP704] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 4, MSTPSR7, 0), /* HSUSB */
 272         [MSTP703] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR7, 3, MSTPSR7, 0), /* EHCI */
 273         [MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
 274         [MSTP502] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 2, MSTPSR5, 0), /* Audio-DMAC low */
 275         [MSTP501] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR5, 1, MSTPSR5, 0), /* Audio-DMAC hi */
 276         [MSTP315] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, MSTPSR3, 0), /* MMC0 */
 277         [MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */
 278         [MSTP313] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD1], SMSTPCR3, 13, MSTPSR3, 0), /* SDHI1 */
 279         [MSTP312] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD2], SMSTPCR3, 12, MSTPSR3, 0), /* SDHI2 */
 280         [MSTP311] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD3], SMSTPCR3, 11, MSTPSR3, 0), /* SDHI3 */
 281         [MSTP305] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, MSTPSR3, 0), /* MMC1 */
 282         [MSTP304] = SH_CLK_MSTP32_STS(&cp_clk, SMSTPCR3, 4, MSTPSR3, 0), /* TPU0 */
 283         [MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */
 284         [MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */
 285         [MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */
 286         [MSTP204] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 4, MSTPSR2, 0), /* SCIFA0 */
 287         [MSTP203] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 3, MSTPSR2, 0), /* SCIFA1 */
 288         [MSTP202] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 2, MSTPSR2, 0), /* SCIFA2 */
 289         [MSTP124] = SH_CLK_MSTP32_STS(&rclk_clk, SMSTPCR1, 24, MSTPSR1, 0), /* CMT0 */
 290 };
 291
 292 static struct clk_lookup lookups[] = {
 293
 294         /* main clocks */
 295         CLKDEV_CON_ID("extal",          &extal_clk),
 296         CLKDEV_CON_ID("extal_div2",     &extal_div2_clk),
 297         CLKDEV_CON_ID("main",           &main_clk),
 298         CLKDEV_CON_ID("pll1",           &pll1_clk),
 299         CLKDEV_CON_ID("pll1_div2",      &pll1_div2_clk),
 300         CLKDEV_CON_ID("pll3",           &pll3_clk),
 301         CLKDEV_CON_ID("zg",             &zg_clk),
 302         CLKDEV_CON_ID("zx",             &zx_clk),
 303         CLKDEV_CON_ID("zs",             &zs_clk),
 304         CLKDEV_CON_ID("hp",             &hp_clk),
 305         CLKDEV_CON_ID("i",              &i_clk),
 306         CLKDEV_CON_ID("b",              &b_clk),
 307         CLKDEV_CON_ID("lb",             &lb_clk),
 308         CLKDEV_CON_ID("p",              &p_clk),
 309         CLKDEV_CON_ID("cl",             &cl_clk),
 310         CLKDEV_CON_ID("m2",             &m2_clk),
 311         CLKDEV_CON_ID("imp",            &imp_clk),
 312         CLKDEV_CON_ID("rclk",           &rclk_clk),
 313         CLKDEV_CON_ID("oscclk",         &oscclk_clk),
 314         CLKDEV_CON_ID("zb3",            &zb3_clk),
 315         CLKDEV_CON_ID("zb3d2",          &zb3d2_clk),
 316         CLKDEV_CON_ID("ddr",            &ddr_clk),
 317         CLKDEV_CON_ID("mp",             &mp_clk),
 318         CLKDEV_CON_ID("qspi",           &qspi_clk),
 319         CLKDEV_CON_ID("cp",             &cp_clk),
 320
 321         /* DIV4 */
 322         CLKDEV_CON_ID("sdh",            &div4_clks[DIV4_SDH]),
 323
 324         /* DIV6 */
 325         CLKDEV_CON_ID("ssp",            &div6_clks[DIV6_SSP]),
 326         CLKDEV_CON_ID("ssprs",          &div6_clks[DIV6_SSPRS]),
 327
 328         /* MSTP */
 329         CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP1005]),
 330         CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
 331         CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
 332         CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
 333         CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
 334         CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
 335         CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
 336         CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
 337         CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
 338         CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
 339         CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
 340         CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
 341         CLKDEV_DEV_ID("i2c-rcar_gen2.1", &mstp_clks[MSTP930]),
 342         CLKDEV_DEV_ID("i2c-rcar_gen2.2", &mstp_clks[MSTP929]),
 343         CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
 344         CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
 345         CLKDEV_DEV_ID("r8a7790-vin.0", &mstp_clks[MSTP811]),
 346         CLKDEV_DEV_ID("r8a7790-vin.1", &mstp_clks[MSTP810]),
 347         CLKDEV_DEV_ID("r8a7790-vin.2", &mstp_clks[MSTP809]),
 348         CLKDEV_DEV_ID("r8a7790-vin.3", &mstp_clks[MSTP808]),
 349         CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
 350         CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP502]),
 351         CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP501]),
 352         CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
 353         CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
 354         CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
 355         CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
 356         CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
 357         CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
 358         CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
 359         CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
 360         CLKDEV_DEV_ID("pci-rcar-gen2.0", &mstp_clks[MSTP703]),
 361         CLKDEV_DEV_ID("pci-rcar-gen2.1", &mstp_clks[MSTP703]),
 362         CLKDEV_DEV_ID("pci-rcar-gen2.2", &mstp_clks[MSTP703]),
 363         CLKDEV_DEV_ID("sata-r8a7790.0", &mstp_clks[MSTP815]),
 364         CLKDEV_DEV_ID("sata-r8a7790.1", &mstp_clks[MSTP814]),
 365
 366         /* ICK */
 367         CLKDEV_ICK_ID("fck", "sh-cmt-48-gen2.0", &mstp_clks[MSTP124]),
 368         CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
 369         CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
 370         CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
 371         CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
 372         CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
 373         CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
 374         CLKDEV_ICK_ID("clk_a", "rcar_sound", &audio_clk_a),
 375         CLKDEV_ICK_ID("clk_b", "rcar_sound", &audio_clk_b),
 376         CLKDEV_ICK_ID("clk_c", "rcar_sound", &audio_clk_c),
 377         CLKDEV_ICK_ID("clk_i", "rcar_sound", &m2_clk),
 378         CLKDEV_ICK_ID("src.0", "rcar_sound", &mstp_clks[MSTP1031]),
 379         CLKDEV_ICK_ID("src.1", "rcar_sound", &mstp_clks[MSTP1030]),
 380         CLKDEV_ICK_ID("src.2", "rcar_sound", &mstp_clks[MSTP1029]),
 381         CLKDEV_ICK_ID("src.3", "rcar_sound", &mstp_clks[MSTP1028]),
 382         CLKDEV_ICK_ID("src.4", "rcar_sound", &mstp_clks[MSTP1027]),
 383         CLKDEV_ICK_ID("src.5", "rcar_sound", &mstp_clks[MSTP1026]),
 384         CLKDEV_ICK_ID("src.6", "rcar_sound", &mstp_clks[MSTP1025]),
 385         CLKDEV_ICK_ID("src.7", "rcar_sound", &mstp_clks[MSTP1024]),
 386         CLKDEV_ICK_ID("src.8", "rcar_sound", &mstp_clks[MSTP1023]),
 387         CLKDEV_ICK_ID("src.9", "rcar_sound", &mstp_clks[MSTP1022]),
 388         CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]),
 389         CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]),
 390         CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]),
 391         CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP1012]),
 392         CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP1011]),
 393         CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP1010]),
 394         CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP1009]),
 395         CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP1008]),
 396         CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP1007]),
 397         CLKDEV_ICK_ID("ssi.9", "rcar_sound", &mstp_clks[MSTP1006]),
 398
 399 };
 400
 401 #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31)              \
 402         extal_clk.rate  = e * 1000 * 1000;                      \
 403         main_clk.parent = m;                                    \
 404         SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1);           \
 405         if (mode & MD(19))                                      \
 406                 SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1);      \
 407         else                                                    \
 408                 SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
 409
 410
 411 void __init r8a7790_clock_init(void)
 412 {
 413         u32 mode = rcar_gen2_read_mode_pins();
 414         int k, ret = 0;
 415
 416         switch (mode & (MD(14) | MD(13))) {
 417         case 0:
 418                 R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
 419                 break;
 420         case MD(13):
 421                 R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
 422                 break;
 423         case MD(14):
 424                 R8A7790_CLOCK_ROOT(26 / 2, &extal_div2_clk, 200, 240, 122, 102);
 425                 break;
 426         case MD(13) | MD(14):
 427                 R8A7790_CLOCK_ROOT(30 / 2, &extal_div2_clk, 172, 208, 106, 88);
 428                 break;
 429         }
 430
 431         if (mode & (MD(18)))
 432                 SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36);
 433         else
 434                 SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24);
 435
 436         if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
 437                 SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
 438         else
 439                 SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
 440
 441         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 442                 ret = clk_register(main_clks[k]);
 443
 444         if (!ret)
 445                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 446
 447         if (!ret)
 448                 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
 449
 450         if (!ret)
 451                 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
 452
 453         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 454
 455         if (!ret)
 456                 shmobile_clk_init();
 457         else
 458                 panic("failed to setup r8a7790 clocks\n");
 459 }