2 * sh7372 Power management support
4 * Copyright (C) 2011 Magnus Damm
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/suspend.h>
13 #include <linux/cpuidle.h>
14 #include <linux/module.h>
15 #include <linux/list.h>
16 #include <linux/err.h>
17 #include <linux/slab.h>
18 #include <linux/pm_clock.h>
19 #include <linux/platform_device.h>
20 #include <linux/delay.h>
21 #include <linux/irq.h>
22 #include <linux/bitrev.h>
23 #include <linux/console.h>
25 #include <asm/cpuidle.h>
27 #include <asm/tlbflush.h>
28 #include <asm/suspend.h>
31 #include "pm-rmobile.h"
35 #define DBGREG1 IOMEM(0xe6100020)
36 #define DBGREG9 IOMEM(0xe6100040)
39 #define SYSTBCR IOMEM(0xe6150024)
40 #define MSTPSR0 IOMEM(0xe6150030)
41 #define MSTPSR1 IOMEM(0xe6150038)
42 #define MSTPSR2 IOMEM(0xe6150040)
43 #define MSTPSR3 IOMEM(0xe6150048)
44 #define MSTPSR4 IOMEM(0xe615004c)
45 #define PLLC01STPCR IOMEM(0xe61500c8)
48 #define SBAR IOMEM(0xe6180020)
49 #define WUPRMSK IOMEM(0xe6180028)
50 #define WUPSMSK IOMEM(0xe618002c)
51 #define WUPSMSK2 IOMEM(0xe6180048)
52 #define WUPSFAC IOMEM(0xe6180098)
53 #define IRQCR IOMEM(0xe618022c)
54 #define IRQCR2 IOMEM(0xe6180238)
55 #define IRQCR3 IOMEM(0xe6180244)
56 #define IRQCR4 IOMEM(0xe6180248)
57 #define PDNSEL IOMEM(0xe6180254)
60 #define ICR1A IOMEM(0xe6900000)
61 #define ICR2A IOMEM(0xe6900004)
62 #define ICR3A IOMEM(0xe6900008)
63 #define ICR4A IOMEM(0xe690000c)
64 #define INTMSK00A IOMEM(0xe6900040)
65 #define INTMSK10A IOMEM(0xe6900044)
66 #define INTMSK20A IOMEM(0xe6900048)
67 #define INTMSK30A IOMEM(0xe690004c)
70 /* FIXME: pointing where? */
71 #define SMFRAM 0xe6a70000
74 #define APARMBAREA IOMEM(0xe6f10020)
78 #define PM_DOMAIN_ON_OFF_LATENCY_NS 250000
80 static int sh7372_a4r_pd_suspend(void)
82 sh7372_intcs_suspend();
83 __raw_writel(0x300fffff, WUPRMSK
); /* avoid wakeup */
87 static bool a4s_suspend_ready
;
89 static int sh7372_a4s_pd_suspend(void)
92 * The A4S domain contains the CPU core and therefore it should
93 * only be turned off if the CPU is not in use. This may happen
94 * during system suspend, when SYSC is going to be used for generating
95 * resume signals and a4s_suspend_ready is set to let
96 * sh7372_enter_suspend() know that it can turn A4S off.
98 a4s_suspend_ready
= true;
102 static void sh7372_a4s_pd_resume(void)
104 a4s_suspend_ready
= false;
107 static int sh7372_a3sp_pd_suspend(void)
110 * Serial consoles make use of SCIF hardware located in A3SP,
111 * keep such power domain on if "no_console_suspend" is set.
113 return console_suspend_enabled
? 0 : -EBUSY
;
116 static struct rmobile_pm_domain sh7372_pm_domains
[] = {
118 .genpd
.name
= "A4LC",
119 .genpd
.power_on_latency_ns
= PM_DOMAIN_ON_OFF_LATENCY_NS
,
120 .genpd
.power_off_latency_ns
= PM_DOMAIN_ON_OFF_LATENCY_NS
,
124 .genpd
.name
= "A4MP",
125 .genpd
.power_on_latency_ns
= PM_DOMAIN_ON_OFF_LATENCY_NS
,
126 .genpd
.power_off_latency_ns
= PM_DOMAIN_ON_OFF_LATENCY_NS
,
131 .genpd
.power_on_latency_ns
= PM_DOMAIN_ON_OFF_LATENCY_NS
,
132 .genpd
.power_off_latency_ns
= PM_DOMAIN_ON_OFF_LATENCY_NS
,
137 .genpd
.power_on_latency_ns
= PM_DOMAIN_ON_OFF_LATENCY_NS
,
138 .genpd
.power_off_latency_ns
= PM_DOMAIN_ON_OFF_LATENCY_NS
,
140 .suspend
= sh7372_a4r_pd_suspend
,
141 .resume
= sh7372_intcs_resume
,
144 .genpd
.name
= "A3RV",
145 .genpd
.power_on_latency_ns
= PM_DOMAIN_ON_OFF_LATENCY_NS
,
146 .genpd
.power_off_latency_ns
= PM_DOMAIN_ON_OFF_LATENCY_NS
,
150 .genpd
.name
= "A3RI",
151 .genpd
.power_on_latency_ns
= PM_DOMAIN_ON_OFF_LATENCY_NS
,
152 .genpd
.power_off_latency_ns
= PM_DOMAIN_ON_OFF_LATENCY_NS
,
157 .genpd
.power_on_latency_ns
= PM_DOMAIN_ON_OFF_LATENCY_NS
,
158 .genpd
.power_off_latency_ns
= PM_DOMAIN_ON_OFF_LATENCY_NS
,
160 .gov
= &pm_domain_always_on_gov
,
162 .suspend
= sh7372_a4s_pd_suspend
,
163 .resume
= sh7372_a4s_pd_resume
,
166 .genpd
.name
= "A3SP",
167 .genpd
.power_on_latency_ns
= PM_DOMAIN_ON_OFF_LATENCY_NS
,
168 .genpd
.power_off_latency_ns
= PM_DOMAIN_ON_OFF_LATENCY_NS
,
170 .gov
= &pm_domain_always_on_gov
,
172 .suspend
= sh7372_a3sp_pd_suspend
,
175 .genpd
.name
= "A3SG",
176 .genpd
.power_on_latency_ns
= PM_DOMAIN_ON_OFF_LATENCY_NS
,
177 .genpd
.power_off_latency_ns
= PM_DOMAIN_ON_OFF_LATENCY_NS
,
182 void __init
sh7372_init_pm_domains(void)
184 rmobile_init_domains(sh7372_pm_domains
, ARRAY_SIZE(sh7372_pm_domains
));
185 pm_genpd_add_subdomain_names("A4LC", "A3RV");
186 pm_genpd_add_subdomain_names("A4R", "A4LC");
187 pm_genpd_add_subdomain_names("A4S", "A3SG");
188 pm_genpd_add_subdomain_names("A4S", "A3SP");
191 #endif /* CONFIG_PM */
193 #if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
194 static void sh7372_set_reset_vector(unsigned long address
)
196 /* set reset vector, translate 4k */
197 __raw_writel(address
, SBAR
);
198 __raw_writel(0, APARMBAREA
);
201 static void sh7372_enter_sysc(int pllc0_on
, unsigned long sleep_mode
)
204 __raw_writel(0, PLLC01STPCR
);
206 __raw_writel(1 << 28, PLLC01STPCR
);
208 __raw_readl(WUPSFAC
); /* read wakeup int. factor before sleep */
209 cpu_suspend(sleep_mode
, sh7372_do_idle_sysc
);
210 __raw_readl(WUPSFAC
); /* read wakeup int. factor after wakeup */
212 /* disable reset vector translation */
213 __raw_writel(0, SBAR
);
216 static int sh7372_sysc_valid(unsigned long *mskp
, unsigned long *msk2p
)
218 unsigned long mstpsr0
, mstpsr1
, mstpsr2
, mstpsr3
, mstpsr4
;
219 unsigned long msk
, msk2
;
221 /* check active clocks to determine potential wakeup sources */
223 mstpsr0
= __raw_readl(MSTPSR0
);
224 if ((mstpsr0
& 0x00000003) != 0x00000003) {
225 pr_debug("sh7372 mstpsr0 0x%08lx\n", mstpsr0
);
229 mstpsr1
= __raw_readl(MSTPSR1
);
230 if ((mstpsr1
& 0xff079b7f) != 0xff079b7f) {
231 pr_debug("sh7372 mstpsr1 0x%08lx\n", mstpsr1
);
235 mstpsr2
= __raw_readl(MSTPSR2
);
236 if ((mstpsr2
& 0x000741ff) != 0x000741ff) {
237 pr_debug("sh7372 mstpsr2 0x%08lx\n", mstpsr2
);
241 mstpsr3
= __raw_readl(MSTPSR3
);
242 if ((mstpsr3
& 0x1a60f010) != 0x1a60f010) {
243 pr_debug("sh7372 mstpsr3 0x%08lx\n", mstpsr3
);
247 mstpsr4
= __raw_readl(MSTPSR4
);
248 if ((mstpsr4
& 0x00008cf0) != 0x00008cf0) {
249 pr_debug("sh7372 mstpsr4 0x%08lx\n", mstpsr4
);
256 /* make bitmaps of limited number of wakeup sources */
258 if ((mstpsr2
& (1 << 23)) == 0) /* SPU2 */
261 if ((mstpsr2
& (1 << 12)) == 0) /* MFI_MFIM */
264 if ((mstpsr4
& (1 << 3)) == 0) /* KEYSC */
267 if ((mstpsr1
& (1 << 24)) == 0) /* CMT0 */
270 if ((mstpsr3
& (1 << 29)) == 0) /* CMT1 */
273 if ((mstpsr4
& (1 << 0)) == 0) /* CMT2 */
276 if ((mstpsr2
& (1 << 13)) == 0) /* MFI_MFIS */
285 static void sh7372_icr_to_irqcr(unsigned long icr
, u16
*irqcr1p
, u16
*irqcr2p
)
287 u16 tmp
, irqcr1
, irqcr2
;
293 /* convert INTCA ICR register layout to SYSC IRQCR+IRQCR2 */
294 for (k
= 0; k
<= 7; k
++) {
295 tmp
= (icr
>> ((7 - k
) * 4)) & 0xf;
296 irqcr1
|= (tmp
& 0x03) << (k
* 2);
297 irqcr2
|= (tmp
>> 2) << (k
* 2);
304 static void sh7372_setup_sysc(unsigned long msk
, unsigned long msk2
)
306 u16 irqcrx_low
, irqcrx_high
, irqcry_low
, irqcry_high
;
309 /* read IRQ0A -> IRQ15A mask */
310 tmp
= bitrev8(__raw_readb(INTMSK00A
));
311 tmp
|= bitrev8(__raw_readb(INTMSK10A
)) << 8;
313 /* setup WUPSMSK from clocks and external IRQ mask */
314 msk
= (~msk
& 0xc030000f) | (tmp
<< 4);
315 __raw_writel(msk
, WUPSMSK
);
317 /* propage level/edge trigger for external IRQ 0->15 */
318 sh7372_icr_to_irqcr(__raw_readl(ICR1A
), &irqcrx_low
, &irqcry_low
);
319 sh7372_icr_to_irqcr(__raw_readl(ICR2A
), &irqcrx_high
, &irqcry_high
);
320 __raw_writel((irqcrx_high
<< 16) | irqcrx_low
, IRQCR
);
321 __raw_writel((irqcry_high
<< 16) | irqcry_low
, IRQCR2
);
323 /* read IRQ16A -> IRQ31A mask */
324 tmp
= bitrev8(__raw_readb(INTMSK20A
));
325 tmp
|= bitrev8(__raw_readb(INTMSK30A
)) << 8;
327 /* setup WUPSMSK2 from clocks and external IRQ mask */
328 msk2
= (~msk2
& 0x00030000) | tmp
;
329 __raw_writel(msk2
, WUPSMSK2
);
331 /* propage level/edge trigger for external IRQ 16->31 */
332 sh7372_icr_to_irqcr(__raw_readl(ICR3A
), &irqcrx_low
, &irqcry_low
);
333 sh7372_icr_to_irqcr(__raw_readl(ICR4A
), &irqcrx_high
, &irqcry_high
);
334 __raw_writel((irqcrx_high
<< 16) | irqcrx_low
, IRQCR3
);
335 __raw_writel((irqcry_high
<< 16) | irqcry_low
, IRQCR4
);
338 static void sh7372_enter_a3sm_common(int pllc0_on
)
340 /* use INTCA together with SYSC for wakeup */
341 sh7372_setup_sysc(1 << 0, 0);
342 sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc
));
343 sh7372_enter_sysc(pllc0_on
, 1 << 12);
346 static void sh7372_enter_a4s_common(int pllc0_on
)
348 sh7372_intca_suspend();
349 sh7372_set_reset_vector(SMFRAM
);
350 sh7372_enter_sysc(pllc0_on
, 1 << 10);
351 sh7372_intca_resume();
354 static void sh7372_pm_setup_smfram(void)
356 /* pass physical address of cpu_resume() to assembly resume code */
357 sh7372_cpu_resume
= virt_to_phys(cpu_resume
);
359 memcpy((void *)SMFRAM
, sh7372_resume_core_standby_sysc
, 0x100);
362 static inline void sh7372_pm_setup_smfram(void) {}
363 #endif /* CONFIG_SUSPEND || CONFIG_CPU_IDLE */
365 #ifdef CONFIG_CPU_IDLE
366 static int sh7372_do_idle_core_standby(unsigned long unused
)
368 cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */
372 static int sh7372_enter_core_standby(struct cpuidle_device
*dev
,
373 struct cpuidle_driver
*drv
, int index
)
375 sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc
));
377 /* enter sleep mode with SYSTBCR to 0x10 */
378 __raw_writel(0x10, SYSTBCR
);
379 cpu_suspend(0, sh7372_do_idle_core_standby
);
380 __raw_writel(0, SYSTBCR
);
382 /* disable reset vector translation */
383 __raw_writel(0, SBAR
);
388 static int sh7372_enter_a3sm_pll_on(struct cpuidle_device
*dev
,
389 struct cpuidle_driver
*drv
, int index
)
391 sh7372_enter_a3sm_common(1);
395 static int sh7372_enter_a3sm_pll_off(struct cpuidle_device
*dev
,
396 struct cpuidle_driver
*drv
, int index
)
398 sh7372_enter_a3sm_common(0);
402 static int sh7372_enter_a4s(struct cpuidle_device
*dev
,
403 struct cpuidle_driver
*drv
, int index
)
405 unsigned long msk
, msk2
;
407 if (!sh7372_sysc_valid(&msk
, &msk2
))
408 return sh7372_enter_a3sm_pll_off(dev
, drv
, index
);
410 sh7372_setup_sysc(msk
, msk2
);
411 sh7372_enter_a4s_common(0);
415 static struct cpuidle_driver sh7372_cpuidle_driver
= {
416 .name
= "sh7372_cpuidle",
417 .owner
= THIS_MODULE
,
419 .safe_state_index
= 0, /* C1 */
420 .states
[0] = ARM_CPUIDLE_WFI_STATE
,
423 .desc
= "Core Standby Mode",
425 .target_residency
= 20 + 10,
426 .enter
= sh7372_enter_core_standby
,
430 .desc
= "A3SM PLL ON",
432 .target_residency
= 30 + 20,
433 .enter
= sh7372_enter_a3sm_pll_on
,
437 .desc
= "A3SM PLL OFF",
439 .target_residency
= 30 + 120,
440 .enter
= sh7372_enter_a3sm_pll_off
,
444 .desc
= "A4S PLL OFF",
446 .target_residency
= 30 + 240,
447 .enter
= sh7372_enter_a4s
,
452 static void __init
sh7372_cpuidle_init(void)
454 shmobile_cpuidle_set_driver(&sh7372_cpuidle_driver
);
457 static void __init
sh7372_cpuidle_init(void) {}
460 #ifdef CONFIG_SUSPEND
461 static int sh7372_enter_suspend(suspend_state_t suspend_state
)
463 unsigned long msk
, msk2
;
465 /* check active clocks to determine potential wakeup sources */
466 if (sh7372_sysc_valid(&msk
, &msk2
) && a4s_suspend_ready
) {
467 /* convert INTC mask/sense to SYSC mask/sense */
468 sh7372_setup_sysc(msk
, msk2
);
470 /* enter A4S sleep with PLLC0 off */
471 pr_debug("entering A4S\n");
472 sh7372_enter_a4s_common(0);
476 /* default to enter A3SM sleep with PLLC0 off */
477 pr_debug("entering A3SM\n");
478 sh7372_enter_a3sm_common(0);
483 * sh7372_pm_notifier_fn - SH7372 PM notifier routine.
485 * @pm_event: Event being handled.
488 static int sh7372_pm_notifier_fn(struct notifier_block
*notifier
,
489 unsigned long pm_event
, void *unused
)
492 case PM_SUSPEND_PREPARE
:
494 * This is necessary, because the A4R domain has to be "on"
495 * when suspend_device_irqs() and resume_device_irqs() are
496 * executed during system suspend and resume, respectively, so
497 * that those functions don't crash while accessing the INTCS.
499 pm_genpd_name_poweron("A4R");
501 case PM_POST_SUSPEND
:
502 pm_genpd_poweroff_unused();
509 static void sh7372_suspend_init(void)
511 shmobile_suspend_ops
.enter
= sh7372_enter_suspend
;
512 pm_notifier(sh7372_pm_notifier_fn
, 0);
515 static void sh7372_suspend_init(void) {}
518 void __init
sh7372_pm_init(void)
520 /* enable DBG hardware block to kick SYSC */
521 __raw_writel(0x0000a500, DBGREG9
);
522 __raw_writel(0x0000a501, DBGREG9
);
523 __raw_writel(0x00000000, DBGREG1
);
525 /* do not convert A3SM, A3SP, A3SG, A4R power down into A4S */
526 __raw_writel(0, PDNSEL
);
528 sh7372_pm_setup_smfram();
530 sh7372_suspend_init();
531 sh7372_cpuidle_init();
534 void __init
sh7372_pm_init_late(void)
536 shmobile_init_late();
537 pm_genpd_name_attach_cpuidle("A4S", 4);