arch/arm/mach-shmobile/setup-r8a73a4.c

   1 /*
   2  * r8a73a4 processor support
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Magnus Damm
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/irq.h>
  21 #include <linux/kernel.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/platform_data/irq-renesas-irqc.h>
  24 #include <linux/serial_sci.h>
  25 #include <linux/sh_timer.h>
  26 #include <mach/common.h>
  27 #include <mach/irqs.h>
  28 #include <mach/r8a73a4.h>
  29 #include <asm/mach/arch.h>
  30
  31 static const struct resource pfc_resources[] = {
  32         DEFINE_RES_MEM(0xe6050000, 0x9000),
  33 };
  34
  35 void __init r8a73a4_pinmux_init(void)
  36 {
  37         platform_device_register_simple("pfc-r8a73a4", -1, pfc_resources,
  38                                         ARRAY_SIZE(pfc_resources));
  39 }
  40
  41 #define SCIF_COMMON(scif_type, baseaddr, irq)                   \
  42         .type           = scif_type,                            \
  43         .mapbase        = baseaddr,                             \
  44         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,      \
  45         .scbrr_algo_id  = SCBRR_ALGO_4,                         \
  46         .irqs           = SCIx_IRQ_MUXED(irq)
  47
  48 #define SCIFA_DATA(index, baseaddr, irq)                \
  49 [index] = {                                             \
  50         SCIF_COMMON(PORT_SCIFA, baseaddr, irq),         \
  51         .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0,      \
  52 }
  53
  54 #define SCIFB_DATA(index, baseaddr, irq)        \
  55 [index] = {                                     \
  56         SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
  57         .scscr = SCSCR_RE | SCSCR_TE,           \
  58 }
  59
  60 enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 };
  61
  62 static const struct plat_sci_port scif[] = {
  63         SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
  64         SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
  65         SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
  66         SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
  67         SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
  68         SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */
  69 };
  70
  71 static inline void r8a73a4_register_scif(int idx)
  72 {
  73         platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
  74                                       sizeof(struct plat_sci_port));
  75 }
  76
  77 static const struct renesas_irqc_config irqc0_data = {
  78         .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
  79 };
  80
  81 static const struct resource irqc0_resources[] = {
  82         DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
  83         DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
  84         DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
  85         DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
  86         DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
  87         DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */
  88         DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */
  89         DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */
  90         DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */
  91         DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */
  92         DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */
  93         DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */
  94         DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */
  95         DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */
  96         DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */
  97         DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */
  98         DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */
  99         DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */
 100         DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */
 101         DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */
 102         DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */
 103         DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */
 104         DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */
 105         DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */
 106         DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */
 107         DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */
 108         DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */
 109         DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */
 110         DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */
 111         DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */
 112         DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */
 113         DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */
 114         DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */
 115 };
 116
 117 static const struct renesas_irqc_config irqc1_data = {
 118         .irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */
 119 };
 120
 121 static const struct resource irqc1_resources[] = {
 122         DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */
 123         DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */
 124         DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */
 125         DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */
 126         DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */
 127         DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */
 128         DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */
 129         DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */
 130         DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */
 131         DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */
 132         DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */
 133         DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */
 134         DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */
 135         DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */
 136         DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */
 137         DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */
 138         DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */
 139         DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */
 140         DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */
 141         DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */
 142         DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */
 143         DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */
 144         DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */
 145         DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */
 146         DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */
 147         DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */
 148         DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */
 149 };
 150
 151 #define r8a73a4_register_irqc(idx)                                      \
 152         platform_device_register_resndata(&platform_bus, "renesas_irqc", \
 153                                           idx, irqc##idx##_resources,   \
 154                                           ARRAY_SIZE(irqc##idx##_resources), \
 155                                           &irqc##idx##_data,            \
 156                                           sizeof(struct renesas_irqc_config))
 157
 158 /* Thermal0 -> Thermal2 */
 159 static const struct resource thermal0_resources[] = {
 160         DEFINE_RES_MEM(0xe61f0000, 0x14),
 161         DEFINE_RES_MEM(0xe61f0100, 0x38),
 162         DEFINE_RES_MEM(0xe61f0200, 0x38),
 163         DEFINE_RES_MEM(0xe61f0300, 0x38),
 164         DEFINE_RES_IRQ(gic_spi(69)),
 165 };
 166
 167 #define r8a73a4_register_thermal()                                      \
 168         platform_device_register_simple("rcar_thermal", -1,             \
 169                                         thermal0_resources,             \
 170                                         ARRAY_SIZE(thermal0_resources))
 171
 172 static struct sh_timer_config cmt10_platform_data = {
 173         .name = "CMT10",
 174         .timer_bit = 0,
 175         .clockevent_rating = 80,
 176 };
 177
 178 static struct resource cmt10_resources[] = {
 179         DEFINE_RES_MEM(0xe6130010, 0x0c),
 180         DEFINE_RES_MEM(0xe6130000, 0x04),
 181         DEFINE_RES_IRQ(gic_spi(120)), /* CMT1_0 */
 182 };
 183
 184 #define r8a7790_register_cmt(idx)                                       \
 185         platform_device_register_resndata(&platform_bus, "sh_cmt",      \
 186                                           idx, cmt##idx##_resources,    \
 187                                           ARRAY_SIZE(cmt##idx##_resources), \
 188                                           &cmt##idx##_platform_data,    \
 189                                           sizeof(struct sh_timer_config))
 190
 191 void __init r8a73a4_add_dt_devices(void)
 192 {
 193         r8a73a4_register_scif(SCIFA0);
 194         r8a73a4_register_scif(SCIFA1);
 195         r8a73a4_register_scif(SCIFB0);
 196         r8a73a4_register_scif(SCIFB1);
 197         r8a73a4_register_scif(SCIFB2);
 198         r8a73a4_register_scif(SCIFB3);
 199         r8a7790_register_cmt(10);
 200 }
 201
 202 void __init r8a73a4_add_standard_devices(void)
 203 {
 204         r8a73a4_add_dt_devices();
 205         r8a73a4_register_irqc(0);
 206         r8a73a4_register_irqc(1);
 207         r8a73a4_register_thermal();
 208 }
 209
 210 void __init r8a73a4_init_delay(void)
 211 {
 212 #ifndef CONFIG_ARM_ARCH_TIMER
 213         shmobile_setup_delay(1500, 2, 4); /* Cortex-A15 @ 1500MHz */
 214 #endif
 215 }
 216
 217 #ifdef CONFIG_USE_OF
 218
 219 static const char *r8a73a4_boards_compat_dt[] __initdata = {
 220         "renesas,r8a73a4",
 221         NULL,
 222 };
 223
 224 DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
 225         .init_early     = r8a73a4_init_delay,
 226         .dt_compat      = r8a73a4_boards_compat_dt,
 227 MACHINE_END
 228 #endif /* CONFIG_USE_OF */