arch/arm/mach-shmobile/setup-r8a7790.c

   1 /*
   2  * r8a7790 processor support
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Magnus Damm
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/irq.h>
  18 #include <linux/kernel.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/platform_data/gpio-rcar.h>
  21 #include <linux/platform_data/irq-renesas-irqc.h>
  22 #include <linux/serial_sci.h>
  23 #include <linux/sh_dma.h>
  24 #include <linux/sh_timer.h>
  25
  26 #include <asm/mach/arch.h>
  27
  28 #include "common.h"
  29 #include "dma-register.h"
  30 #include "irqs.h"
  31 #include "r8a7790.h"
  32 #include "rcar-gen2.h"
  33
  34 /* Audio-DMAC */
  35 #define AUDIO_DMAC_SLAVE(_id, _addr, t, r)                      \
  36 {                                                               \
  37         .slave_id       = AUDIO_DMAC_SLAVE_## _id ##_TX,        \
  38         .addr           = _addr + 0x8,                          \
  39         .chcr           = CHCR_TX(XMIT_SZ_32BIT),               \
  40         .mid_rid        = t,                                    \
  41 }, {                                                            \
  42         .slave_id       = AUDIO_DMAC_SLAVE_## _id ##_RX,        \
  43         .addr           = _addr + 0xc,                          \
  44         .chcr           = CHCR_RX(XMIT_SZ_32BIT),               \
  45         .mid_rid        = r,                                    \
  46 }
  47
  48 static const struct sh_dmae_slave_config r8a7790_audio_dmac_slaves[] = {
  49         AUDIO_DMAC_SLAVE(SSI0, 0xec241000, 0x01, 0x02),
  50         AUDIO_DMAC_SLAVE(SSI1, 0xec241040, 0x03, 0x04),
  51         AUDIO_DMAC_SLAVE(SSI2, 0xec241080, 0x05, 0x06),
  52         AUDIO_DMAC_SLAVE(SSI3, 0xec2410c0, 0x07, 0x08),
  53         AUDIO_DMAC_SLAVE(SSI4, 0xec241100, 0x09, 0x0a),
  54         AUDIO_DMAC_SLAVE(SSI5, 0xec241140, 0x0b, 0x0c),
  55         AUDIO_DMAC_SLAVE(SSI6, 0xec241180, 0x0d, 0x0e),
  56         AUDIO_DMAC_SLAVE(SSI7, 0xec2411c0, 0x0f, 0x10),
  57         AUDIO_DMAC_SLAVE(SSI8, 0xec241200, 0x11, 0x12),
  58         AUDIO_DMAC_SLAVE(SSI9, 0xec241240, 0x13, 0x14),
  59 };
  60
  61 #define DMAE_CHANNEL(a, b)                      \
  62 {                                               \
  63         .offset         = (a) - 0x20,           \
  64         .dmars          = (a) - 0x20 + 0x40,    \
  65         .chclr_bit      = (b),                  \
  66         .chclr_offset   = 0x80 - 0x20,          \
  67 }
  68
  69 static const struct sh_dmae_channel r8a7790_audio_dmac_channels[] = {
  70         DMAE_CHANNEL(0x8000, 0),
  71         DMAE_CHANNEL(0x8080, 1),
  72         DMAE_CHANNEL(0x8100, 2),
  73         DMAE_CHANNEL(0x8180, 3),
  74         DMAE_CHANNEL(0x8200, 4),
  75         DMAE_CHANNEL(0x8280, 5),
  76         DMAE_CHANNEL(0x8300, 6),
  77         DMAE_CHANNEL(0x8380, 7),
  78         DMAE_CHANNEL(0x8400, 8),
  79         DMAE_CHANNEL(0x8480, 9),
  80         DMAE_CHANNEL(0x8500, 10),
  81         DMAE_CHANNEL(0x8580, 11),
  82         DMAE_CHANNEL(0x8600, 12),
  83 };
  84
  85 static struct sh_dmae_pdata r8a7790_audio_dmac_platform_data = {
  86         .slave          = r8a7790_audio_dmac_slaves,
  87         .slave_num      = ARRAY_SIZE(r8a7790_audio_dmac_slaves),
  88         .channel        = r8a7790_audio_dmac_channels,
  89         .channel_num    = ARRAY_SIZE(r8a7790_audio_dmac_channels),
  90         .ts_low_shift   = TS_LOW_SHIFT,
  91         .ts_low_mask    = TS_LOW_BIT << TS_LOW_SHIFT,
  92         .ts_high_shift  = TS_HI_SHIFT,
  93         .ts_high_mask   = TS_HI_BIT << TS_HI_SHIFT,
  94         .ts_shift       = dma_ts_shift,
  95         .ts_shift_num   = ARRAY_SIZE(dma_ts_shift),
  96         .dmaor_init     = DMAOR_DME,
  97         .chclr_present  = 1,
  98         .chclr_bitwise  = 1,
  99 };
 100
 101 static struct resource r8a7790_audio_dmac_resources[] = {
 102         /* Channel registers and DMAOR for low */
 103         DEFINE_RES_MEM(0xec700020, 0x8663 - 0x20),
 104         DEFINE_RES_IRQ(gic_spi(346)),
 105         DEFINE_RES_NAMED(gic_spi(320), 13, NULL, IORESOURCE_IRQ),
 106
 107         /* Channel registers and DMAOR for hi */
 108         DEFINE_RES_MEM(0xec720020, 0x8663 - 0x20), /* hi */
 109         DEFINE_RES_IRQ(gic_spi(347)),
 110         DEFINE_RES_NAMED(gic_spi(333), 13, NULL, IORESOURCE_IRQ),
 111 };
 112
 113 #define r8a7790_register_audio_dmac(id)                         \
 114         platform_device_register_resndata(                      \
 115                 NULL, "sh-dma-engine", id,                      \
 116                 &r8a7790_audio_dmac_resources[id * 3],  3,      \
 117                 &r8a7790_audio_dmac_platform_data,              \
 118                 sizeof(r8a7790_audio_dmac_platform_data))
 119
 120 static const struct resource pfc_resources[] __initconst = {
 121         DEFINE_RES_MEM(0xe6060000, 0x250),
 122 };
 123
 124 #define r8a7790_register_pfc()                                          \
 125         platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, \
 126                                         ARRAY_SIZE(pfc_resources))
 127
 128 #define R8A7790_GPIO(idx)                                               \
 129 static const struct resource r8a7790_gpio##idx##_resources[] __initconst = { \
 130         DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50),              \
 131         DEFINE_RES_IRQ(gic_spi(4 + (idx))),                             \
 132 };                                                                      \
 133                                                                         \
 134 static const struct gpio_rcar_config                                    \
 135 r8a7790_gpio##idx##_platform_data __initconst = {                       \
 136         .gpio_base      = 32 * (idx),                                   \
 137         .irq_base       = 0,                                            \
 138         .number_of_pins = 32,                                           \
 139         .pctl_name      = "pfc-r8a7790",                                \
 140         .has_both_edge_trigger = 1,                                     \
 141 };                                                                      \
 142
 143 R8A7790_GPIO(0);
 144 R8A7790_GPIO(1);
 145 R8A7790_GPIO(2);
 146 R8A7790_GPIO(3);
 147 R8A7790_GPIO(4);
 148 R8A7790_GPIO(5);
 149
 150 #define r8a7790_register_gpio(idx)                                      \
 151         platform_device_register_resndata(NULL, "gpio_rcar", idx,       \
 152                 r8a7790_gpio##idx##_resources,                          \
 153                 ARRAY_SIZE(r8a7790_gpio##idx##_resources),              \
 154                 &r8a7790_gpio##idx##_platform_data,                     \
 155                 sizeof(r8a7790_gpio##idx##_platform_data))
 156
 157 static struct resource i2c_resources[] __initdata = {
 158         /* I2C0 */
 159         DEFINE_RES_MEM(0xE6508000, 0x40),
 160         DEFINE_RES_IRQ(gic_spi(287)),
 161         /* I2C1 */
 162         DEFINE_RES_MEM(0xE6518000, 0x40),
 163         DEFINE_RES_IRQ(gic_spi(288)),
 164         /* I2C2 */
 165         DEFINE_RES_MEM(0xE6530000, 0x40),
 166         DEFINE_RES_IRQ(gic_spi(286)),
 167         /* I2C3 */
 168         DEFINE_RES_MEM(0xE6540000, 0x40),
 169         DEFINE_RES_IRQ(gic_spi(290)),
 170
 171 };
 172
 173 #define r8a7790_register_i2c(idx)               \
 174         platform_device_register_simple(        \
 175                 "i2c-rcar_gen2", idx,           \
 176                 i2c_resources + (2 * idx), 2);  \
 177
 178 void __init r8a7790_pinmux_init(void)
 179 {
 180         r8a7790_register_pfc();
 181         r8a7790_register_gpio(0);
 182         r8a7790_register_gpio(1);
 183         r8a7790_register_gpio(2);
 184         r8a7790_register_gpio(3);
 185         r8a7790_register_gpio(4);
 186         r8a7790_register_gpio(5);
 187 }
 188
 189 #define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq)         \
 190 static struct plat_sci_port scif##index##_platform_data = {             \
 191         .type           = scif_type,                                    \
 192         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,              \
 193         .scscr          = _scscr,                                       \
 194 };                                                                      \
 195                                                                         \
 196 static struct resource scif##index##_resources[] = {                    \
 197         DEFINE_RES_MEM(baseaddr, 0x100),                                \
 198         DEFINE_RES_IRQ(irq),                                            \
 199 }
 200
 201 #define R8A7790_SCIF(index, baseaddr, irq)                              \
 202         __R8A7790_SCIF(PORT_SCIF, SCSCR_RE | SCSCR_TE,                  \
 203                        index, baseaddr, irq)
 204
 205 #define R8A7790_SCIFA(index, baseaddr, irq)                             \
 206         __R8A7790_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0,    \
 207                        index, baseaddr, irq)
 208
 209 #define R8A7790_SCIFB(index, baseaddr, irq)                             \
 210         __R8A7790_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE,                 \
 211                        index, baseaddr, irq)
 212
 213 #define R8A7790_HSCIF(index, baseaddr, irq)                             \
 214         __R8A7790_SCIF(PORT_HSCIF, SCSCR_RE | SCSCR_TE,                 \
 215                        index, baseaddr, irq)
 216
 217 R8A7790_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
 218 R8A7790_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
 219 R8A7790_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
 220 R8A7790_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
 221 R8A7790_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
 222 R8A7790_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */
 223 R8A7790_SCIF(6,  0xe6e60000, gic_spi(152)); /* SCIF0 */
 224 R8A7790_SCIF(7,  0xe6e68000, gic_spi(153)); /* SCIF1 */
 225 R8A7790_HSCIF(8, 0xe62c0000, gic_spi(154)); /* HSCIF0 */
 226 R8A7790_HSCIF(9, 0xe62c8000, gic_spi(155)); /* HSCIF1 */
 227
 228 #define r8a7790_register_scif(index)                                           \
 229         platform_device_register_resndata(NULL, "sh-sci", index,               \
 230                                           scif##index##_resources,             \
 231                                           ARRAY_SIZE(scif##index##_resources), \
 232                                           &scif##index##_platform_data,        \
 233                                           sizeof(scif##index##_platform_data))
 234
 235 static const struct renesas_irqc_config irqc0_data __initconst = {
 236         .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
 237 };
 238
 239 static const struct resource irqc0_resources[] __initconst = {
 240         DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
 241         DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
 242         DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
 243         DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
 244         DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
 245 };
 246
 247 #define r8a7790_register_irqc(idx)                                      \
 248         platform_device_register_resndata(NULL, "renesas_irqc",         \
 249                                           idx, irqc##idx##_resources,   \
 250                                           ARRAY_SIZE(irqc##idx##_resources), \
 251                                           &irqc##idx##_data,            \
 252                                           sizeof(struct renesas_irqc_config))
 253
 254 static const struct resource thermal_resources[] __initconst = {
 255         DEFINE_RES_MEM(0xe61f0000, 0x14),
 256         DEFINE_RES_MEM(0xe61f0100, 0x38),
 257         DEFINE_RES_IRQ(gic_spi(69)),
 258 };
 259
 260 #define r8a7790_register_thermal()                                      \
 261         platform_device_register_simple("rcar_thermal", -1,             \
 262                                         thermal_resources,              \
 263                                         ARRAY_SIZE(thermal_resources))
 264
 265 static struct sh_timer_config cmt0_platform_data = {
 266         .channels_mask = 0x60,
 267 };
 268
 269 static struct resource cmt0_resources[] = {
 270         DEFINE_RES_MEM(0xffca0000, 0x1004),
 271         DEFINE_RES_IRQ(gic_spi(142)),
 272 };
 273
 274 #define r8a7790_register_cmt(idx)                                       \
 275         platform_device_register_resndata(NULL, "sh-cmt-48-gen2",       \
 276                                           idx, cmt##idx##_resources,    \
 277                                           ARRAY_SIZE(cmt##idx##_resources), \
 278                                           &cmt##idx##_platform_data,    \
 279                                           sizeof(struct sh_timer_config))
 280
 281 void __init r8a7790_add_standard_devices(void)
 282 {
 283         r8a7790_register_scif(0);
 284         r8a7790_register_scif(1);
 285         r8a7790_register_scif(2);
 286         r8a7790_register_scif(3);
 287         r8a7790_register_scif(4);
 288         r8a7790_register_scif(5);
 289         r8a7790_register_scif(6);
 290         r8a7790_register_scif(7);
 291         r8a7790_register_scif(8);
 292         r8a7790_register_scif(9);
 293         r8a7790_register_cmt(0);
 294         r8a7790_register_irqc(0);
 295         r8a7790_register_thermal();
 296         r8a7790_register_i2c(0);
 297         r8a7790_register_i2c(1);
 298         r8a7790_register_i2c(2);
 299         r8a7790_register_i2c(3);
 300         r8a7790_register_audio_dmac(0);
 301         r8a7790_register_audio_dmac(1);
 302 }
 303
 304 #ifdef CONFIG_USE_OF
 305
 306 static const char * const r8a7790_boards_compat_dt[] __initconst = {
 307         "renesas,r8a7790",
 308         NULL,
 309 };
 310
 311 DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
 312         .smp            = smp_ops(r8a7790_smp_ops),
 313         .init_early     = shmobile_init_delay,
 314         .init_time      = rcar_gen2_timer_init,
 315         .init_late      = shmobile_init_late,
 316         .reserve        = rcar_gen2_reserve,
 317         .dt_compat      = r8a7790_boards_compat_dt,
 318 MACHINE_END
 319 #endif /* CONFIG_USE_OF */