arch/arm/mach-shmobile/setup-r8a7790.c

   1 /*
   2  * r8a7790 processor support
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Magnus Damm
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20
  21 #include <linux/irq.h>
  22 #include <linux/irqchip.h>
  23 #include <linux/kernel.h>
  24 #include <linux/of_platform.h>
  25 #include <linux/serial_sci.h>
  26 #include <linux/platform_data/gpio-rcar.h>
  27 #include <linux/platform_data/irq-renesas-irqc.h>
  28 #include <mach/common.h>
  29 #include <mach/irqs.h>
  30 #include <mach/r8a7790.h>
  31 #include <asm/mach/arch.h>
  32
  33 static const struct resource pfc_resources[] = {
  34         DEFINE_RES_MEM(0xe6060000, 0x250),
  35 };
  36
  37 #define R8A7790_GPIO(idx)                                               \
  38 static struct resource r8a7790_gpio##idx##_resources[] = {              \
  39         DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50),              \
  40         DEFINE_RES_IRQ(gic_spi(4 + (idx))),                             \
  41 };                                                                      \
  42                                                                         \
  43 static struct gpio_rcar_config r8a7790_gpio##idx##_platform_data = {    \
  44         .gpio_base      = 32 * (idx),                                   \
  45         .irq_base       = 0,                                            \
  46         .number_of_pins = 32,                                           \
  47         .pctl_name      = "pfc-r8a7790",                                \
  48 };                                                                      \
  49
  50 R8A7790_GPIO(0);
  51 R8A7790_GPIO(1);
  52 R8A7790_GPIO(2);
  53 R8A7790_GPIO(3);
  54 R8A7790_GPIO(4);
  55 R8A7790_GPIO(5);
  56
  57 #define r8a7790_register_gpio(idx)                                      \
  58         platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \
  59                 r8a7790_gpio##idx##_resources,                          \
  60                 ARRAY_SIZE(r8a7790_gpio##idx##_resources),              \
  61                 &r8a7790_gpio##idx##_platform_data,                     \
  62                 sizeof(r8a7790_gpio##idx##_platform_data))
  63
  64 void __init r8a7790_pinmux_init(void)
  65 {
  66         platform_device_register_simple("pfc-r8a7790", -1, pfc_resources,
  67                                         ARRAY_SIZE(pfc_resources));
  68         r8a7790_register_gpio(0);
  69         r8a7790_register_gpio(1);
  70         r8a7790_register_gpio(2);
  71         r8a7790_register_gpio(3);
  72         r8a7790_register_gpio(4);
  73         r8a7790_register_gpio(5);
  74 }
  75
  76 #define SCIF_COMMON(scif_type, baseaddr, irq)                   \
  77         .type           = scif_type,                            \
  78         .mapbase        = baseaddr,                             \
  79         .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,      \
  80         .irqs           = SCIx_IRQ_MUXED(irq)
  81
  82 #define SCIFA_DATA(index, baseaddr, irq)                \
  83 [index] = {                                             \
  84         SCIF_COMMON(PORT_SCIFA, baseaddr, irq),         \
  85         .scbrr_algo_id  = SCBRR_ALGO_4,                 \
  86         .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0,      \
  87 }
  88
  89 #define SCIFB_DATA(index, baseaddr, irq)        \
  90 [index] = {                                     \
  91         SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
  92         .scbrr_algo_id  = SCBRR_ALGO_4,         \
  93         .scscr = SCSCR_RE | SCSCR_TE,           \
  94 }
  95
  96 #define SCIF_DATA(index, baseaddr, irq)         \
  97 [index] = {                                             \
  98         SCIF_COMMON(PORT_SCIF, baseaddr, irq),          \
  99         .scbrr_algo_id  = SCBRR_ALGO_2,                 \
 100         .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,      \
 101 }
 102
 103 enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1 };
 104
 105 static const struct plat_sci_port scif[] = {
 106         SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
 107         SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
 108         SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
 109         SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
 110         SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
 111         SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
 112         SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */
 113         SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */
 114 };
 115
 116 static inline void r8a7790_register_scif(int idx)
 117 {
 118         platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx],
 119                                       sizeof(struct plat_sci_port));
 120 }
 121
 122 static struct renesas_irqc_config irqc0_data = {
 123         .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
 124 };
 125
 126 static struct resource irqc0_resources[] = {
 127         DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
 128         DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
 129         DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
 130         DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
 131         DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
 132 };
 133
 134 #define r8a7790_register_irqc(idx)                                      \
 135         platform_device_register_resndata(&platform_bus, "renesas_irqc", \
 136                                           idx, irqc##idx##_resources,   \
 137                                           ARRAY_SIZE(irqc##idx##_resources), \
 138                                           &irqc##idx##_data,            \
 139                                           sizeof(struct renesas_irqc_config))
 140
 141 void __init r8a7790_add_standard_devices(void)
 142 {
 143         r8a7790_register_scif(SCIFA0);
 144         r8a7790_register_scif(SCIFA1);
 145         r8a7790_register_scif(SCIFB0);
 146         r8a7790_register_scif(SCIFB1);
 147         r8a7790_register_scif(SCIFB2);
 148         r8a7790_register_scif(SCIFA2);
 149         r8a7790_register_scif(SCIF0);
 150         r8a7790_register_scif(SCIF1);
 151         r8a7790_register_irqc(0);
 152 }
 153
 154 void __init r8a7790_timer_init(void)
 155 {
 156         void __iomem *cntcr;
 157
 158         /* make sure arch timer is started by setting bit 0 of CNTCT */
 159         cntcr = ioremap(0xe6080000, PAGE_SIZE);
 160         iowrite32(1, cntcr);
 161         iounmap(cntcr);
 162
 163         shmobile_timer_init();
 164 }
 165
 166 #ifdef CONFIG_USE_OF
 167 void __init r8a7790_add_standard_devices_dt(void)
 168 {
 169         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 170 }
 171
 172 static const char *r8a7790_boards_compat_dt[] __initdata = {
 173         "renesas,r8a7790",
 174         NULL,
 175 };
 176
 177 DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
 178         .init_irq       = irqchip_init,
 179         .init_machine   = r8a7790_add_standard_devices_dt,
 180         .init_time      = r8a7790_timer_init,
 181         .dt_compat      = r8a7790_boards_compat_dt,
 182 MACHINE_END
 183 #endif /* CONFIG_USE_OF */