2 * r8a7791 processor support
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Renesas Solutions Corp.
6 * Copyright (C) 2013 Magnus Damm
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <linux/irq.h>
23 #include <linux/kernel.h>
24 #include <linux/of_platform.h>
25 #include <linux/platform_data/irq-renesas-irqc.h>
26 #include <linux/serial_sci.h>
27 #include <linux/sh_timer.h>
28 #include <mach/common.h>
29 #include <mach/irqs.h>
30 #include <mach/r8a7791.h>
31 #include <mach/rcar-gen2.h>
32 #include <asm/mach/arch.h>
34 #define SCIF_COMMON(scif_type, baseaddr, irq) \
36 .mapbase = baseaddr, \
37 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
38 .irqs = SCIx_IRQ_MUXED(irq)
40 #define SCIFA_DATA(index, baseaddr, irq) \
42 SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \
43 .scbrr_algo_id = SCBRR_ALGO_4, \
44 .scscr = SCSCR_RE | SCSCR_TE, \
47 #define SCIFB_DATA(index, baseaddr, irq) \
49 SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \
50 .scbrr_algo_id = SCBRR_ALGO_4, \
51 .scscr = SCSCR_RE | SCSCR_TE, \
54 #define SCIF_DATA(index, baseaddr, irq) \
56 SCIF_COMMON(PORT_SCIF, baseaddr, irq), \
57 .scbrr_algo_id = SCBRR_ALGO_2, \
58 .scscr = SCSCR_RE | SCSCR_TE, \
61 #define HSCIF_DATA(index, baseaddr, irq) \
63 SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \
64 .scbrr_algo_id = SCBRR_ALGO_6, \
65 .scscr = SCSCR_RE | SCSCR_TE, \
68 enum { SCIFA0
, SCIFA1
, SCIFB0
, SCIFB1
, SCIFB2
, SCIFA2
, SCIF0
, SCIF1
,
69 SCIF2
, SCIF3
, SCIF4
, SCIF5
, SCIFA3
, SCIFA4
, SCIFA5
};
71 static const struct plat_sci_port scif
[] __initconst
= {
72 SCIFA_DATA(SCIFA0
, 0xe6c40000, gic_spi(144)), /* SCIFA0 */
73 SCIFA_DATA(SCIFA1
, 0xe6c50000, gic_spi(145)), /* SCIFA1 */
74 SCIFB_DATA(SCIFB0
, 0xe6c20000, gic_spi(148)), /* SCIFB0 */
75 SCIFB_DATA(SCIFB1
, 0xe6c30000, gic_spi(149)), /* SCIFB1 */
76 SCIFB_DATA(SCIFB2
, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */
77 SCIFA_DATA(SCIFA2
, 0xe6c60000, gic_spi(151)), /* SCIFA2 */
78 SCIF_DATA(SCIF0
, 0xe6e60000, gic_spi(152)), /* SCIF0 */
79 SCIF_DATA(SCIF1
, 0xe6e68000, gic_spi(153)), /* SCIF1 */
80 SCIF_DATA(SCIF2
, 0xe6e58000, gic_spi(22)), /* SCIF2 */
81 SCIF_DATA(SCIF3
, 0xe6ea8000, gic_spi(23)), /* SCIF3 */
82 SCIF_DATA(SCIF4
, 0xe6ee0000, gic_spi(24)), /* SCIF4 */
83 SCIF_DATA(SCIF5
, 0xe6ee8000, gic_spi(25)), /* SCIF5 */
84 SCIFA_DATA(SCIFA3
, 0xe6c70000, gic_spi(29)), /* SCIFA3 */
85 SCIFA_DATA(SCIFA4
, 0xe6c78000, gic_spi(30)), /* SCIFA4 */
86 SCIFA_DATA(SCIFA5
, 0xe6c80000, gic_spi(31)), /* SCIFA5 */
89 static inline void r8a7791_register_scif(int idx
)
91 platform_device_register_data(&platform_bus
, "sh-sci", idx
, &scif
[idx
],
92 sizeof(struct plat_sci_port
));
95 static const struct sh_timer_config cmt00_platform_data __initconst
= {
98 .clockevent_rating
= 80,
101 static const struct resource cmt00_resources
[] __initconst
= {
102 DEFINE_RES_MEM(0xffca0510, 0x0c),
103 DEFINE_RES_MEM(0xffca0500, 0x04),
104 DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
107 #define r8a7791_register_cmt(idx) \
108 platform_device_register_resndata(&platform_bus, "sh_cmt", \
109 idx, cmt##idx##_resources, \
110 ARRAY_SIZE(cmt##idx##_resources), \
111 &cmt##idx##_platform_data, \
112 sizeof(struct sh_timer_config))
114 static struct renesas_irqc_config irqc0_data
= {
115 .irq_base
= irq_pin(0), /* IRQ0 -> IRQ9 */
118 static struct resource irqc0_resources
[] = {
119 DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
120 DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
121 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
122 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
123 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
124 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ4 */
125 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ5 */
126 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ6 */
127 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ7 */
128 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ8 */
129 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ9 */
132 #define r8a7791_register_irqc(idx) \
133 platform_device_register_resndata(&platform_bus, "renesas_irqc", \
134 idx, irqc##idx##_resources, \
135 ARRAY_SIZE(irqc##idx##_resources), \
137 sizeof(struct renesas_irqc_config))
139 void __init
r8a7791_add_dt_devices(void)
141 r8a7791_register_scif(SCIFA0
);
142 r8a7791_register_scif(SCIFA1
);
143 r8a7791_register_scif(SCIFB0
);
144 r8a7791_register_scif(SCIFB1
);
145 r8a7791_register_scif(SCIFB2
);
146 r8a7791_register_scif(SCIFA2
);
147 r8a7791_register_scif(SCIF0
);
148 r8a7791_register_scif(SCIF1
);
149 r8a7791_register_scif(SCIF2
);
150 r8a7791_register_scif(SCIF3
);
151 r8a7791_register_scif(SCIF4
);
152 r8a7791_register_scif(SCIF5
);
153 r8a7791_register_scif(SCIFA3
);
154 r8a7791_register_scif(SCIFA4
);
155 r8a7791_register_scif(SCIFA5
);
156 r8a7791_register_cmt(00);
159 void __init
r8a7791_add_standard_devices(void)
161 r8a7791_add_dt_devices();
162 r8a7791_register_irqc(0);
165 void __init
r8a7791_init_early(void)
167 #ifndef CONFIG_ARM_ARCH_TIMER
168 shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
173 static const char *r8a7791_boards_compat_dt
[] __initdata
= {
178 DT_MACHINE_START(R8A7791_DT
, "Generic R8A7791 (Flattened Device Tree)")
179 .smp
= smp_ops(r8a7791_smp_ops
),
180 .init_early
= r8a7791_init_early
,
181 .init_time
= rcar_gen2_timer_init
,
182 .dt_compat
= r8a7791_boards_compat_dt
,
184 #endif /* CONFIG_USE_OF */