arch/arm/mach-shmobile/setup-rcar-gen2.c

   1 /*
   2  * R-Car Generation 2 support
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Magnus Damm
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20
  21 #include <linux/clocksource.h>
  22 #include <linux/io.h>
  23 #include <linux/kernel.h>
  24 #include <mach/common.h>
  25 #include <mach/rcar-gen2.h>
  26 #include <asm/mach/arch.h>
  27
  28 #define MODEMR 0xe6160060
  29
  30 u32 __init rcar_gen2_read_mode_pins(void)
  31 {
  32         void __iomem *modemr = ioremap_nocache(MODEMR, 4);
  33         u32 mode;
  34
  35         BUG_ON(!modemr);
  36         mode = ioread32(modemr);
  37         iounmap(modemr);
  38
  39         return mode;
  40 }
  41
  42 #define CNTCR 0
  43 #define CNTFID0 0x20
  44
  45 void __init rcar_gen2_timer_init(void)
  46 {
  47 #ifdef CONFIG_ARM_ARCH_TIMER
  48         u32 mode = rcar_gen2_read_mode_pins();
  49         void __iomem *base;
  50         int extal_mhz = 0;
  51         u32 freq;
  52
  53         /* At Linux boot time the r8a7790 arch timer comes up
  54          * with the counter disabled. Moreover, it may also report
  55          * a potentially incorrect fixed 13 MHz frequency. To be
  56          * correct these registers need to be updated to use the
  57          * frequency EXTAL / 2 which can be determined by the MD pins.
  58          */
  59
  60         switch (mode & (MD(14) | MD(13))) {
  61         case 0:
  62                 extal_mhz = 15;
  63                 break;
  64         case MD(13):
  65                 extal_mhz = 20;
  66                 break;
  67         case MD(14):
  68                 extal_mhz = 26;
  69                 break;
  70         case MD(13) | MD(14):
  71                 extal_mhz = 30;
  72                 break;
  73         }
  74
  75         /* The arch timer frequency equals EXTAL / 2 */
  76         freq = extal_mhz * (1000000 / 2);
  77
  78         /* Remap "armgcnt address map" space */
  79         base = ioremap(0xe6080000, PAGE_SIZE);
  80
  81         /* Update registers with correct frequency */
  82         iowrite32(freq, base + CNTFID0);
  83         asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
  84
  85         /* make sure arch timer is started by setting bit 0 of CNTCR */
  86         iowrite32(1, base + CNTCR);
  87         iounmap(base);
  88 #endif /* CONFIG_ARM_ARCH_TIMER */
  89
  90         clocksource_of_init();
  91 }