2 * sh73a0 processor support
4 * Copyright (C) 2010 Takashi Yoshii
5 * Copyright (C) 2010 Magnus Damm
6 * Copyright (C) 2008 Yoshihiro Shimoda
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/platform_device.h>
26 #include <linux/of_platform.h>
27 #include <linux/delay.h>
28 #include <linux/input.h>
30 #include <linux/serial_sci.h>
31 #include <linux/sh_dma.h>
32 #include <linux/sh_intc.h>
33 #include <linux/sh_timer.h>
34 #include <linux/platform_data/sh_ipmmu.h>
35 #include <linux/platform_data/irq-renesas-intc-irqpin.h>
36 #include <mach/dma-register.h>
37 #include <mach/irqs.h>
38 #include <mach/sh73a0.h>
39 #include <mach/common.h>
40 #include <asm/mach-types.h>
41 #include <asm/mach/map.h>
42 #include <asm/mach/arch.h>
43 #include <asm/mach/time.h>
45 static struct map_desc sh73a0_io_desc
[] __initdata
= {
46 /* create a 1:1 entity map for 0xe6xxxxxx
47 * used by CPGA, INTC and PFC.
50 .virtual = 0xe6000000,
51 .pfn
= __phys_to_pfn(0xe6000000),
53 .type
= MT_DEVICE_NONSHARED
57 void __init
sh73a0_map_io(void)
59 iotable_init(sh73a0_io_desc
, ARRAY_SIZE(sh73a0_io_desc
));
63 static struct resource pfc_resources
[] __initdata
= {
64 DEFINE_RES_MEM(0xe6050000, 0x8000),
65 DEFINE_RES_MEM(0xe605801c, 0x000c),
68 void __init
sh73a0_pinmux_init(void)
70 platform_device_register_simple("pfc-sh73a0", -1, pfc_resources
,
71 ARRAY_SIZE(pfc_resources
));
75 #define SH73A0_SCIF(scif_type, index, baseaddr, irq) \
76 static struct plat_sci_port scif##index##_platform_data = { \
78 .flags = UPF_BOOT_AUTOCONF, \
79 .scscr = SCSCR_RE | SCSCR_TE, \
82 static struct resource scif##index##_resources[] = { \
83 DEFINE_RES_MEM(baseaddr, 0x100), \
84 DEFINE_RES_IRQ(irq), \
87 static struct platform_device scif##index##_device = { \
90 .resource = scif##index##_resources, \
91 .num_resources = ARRAY_SIZE(scif##index##_resources), \
93 .platform_data = &scif##index##_platform_data, \
97 SH73A0_SCIF(PORT_SCIFA
, 0, 0xe6c40000, gic_spi(72));
98 SH73A0_SCIF(PORT_SCIFA
, 1, 0xe6c50000, gic_spi(73));
99 SH73A0_SCIF(PORT_SCIFA
, 2, 0xe6c60000, gic_spi(74));
100 SH73A0_SCIF(PORT_SCIFA
, 3, 0xe6c70000, gic_spi(75));
101 SH73A0_SCIF(PORT_SCIFA
, 4, 0xe6c80000, gic_spi(78));
102 SH73A0_SCIF(PORT_SCIFA
, 5, 0xe6cb0000, gic_spi(79));
103 SH73A0_SCIF(PORT_SCIFA
, 6, 0xe6cc0000, gic_spi(156));
104 SH73A0_SCIF(PORT_SCIFA
, 7, 0xe6cd0000, gic_spi(143));
105 SH73A0_SCIF(PORT_SCIFB
, 8, 0xe6c30000, gic_spi(80));
107 static struct sh_timer_config cmt10_platform_data
= {
109 .channel_offset
= 0x10,
111 .clockevent_rating
= 80,
112 .clocksource_rating
= 125,
115 static struct resource cmt10_resources
[] = {
120 .flags
= IORESOURCE_MEM
,
123 .start
= gic_spi(65),
124 .flags
= IORESOURCE_IRQ
,
128 static struct platform_device cmt10_device
= {
132 .platform_data
= &cmt10_platform_data
,
134 .resource
= cmt10_resources
,
135 .num_resources
= ARRAY_SIZE(cmt10_resources
),
139 static struct sh_timer_config tmu00_platform_data
= {
141 .channel_offset
= 0x4,
143 .clockevent_rating
= 200,
146 static struct resource tmu00_resources
[] = {
147 [0] = DEFINE_RES_MEM(0xfff60008, 0xc),
149 .start
= intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
150 .flags
= IORESOURCE_IRQ
,
154 static struct platform_device tmu00_device
= {
158 .platform_data
= &tmu00_platform_data
,
160 .resource
= tmu00_resources
,
161 .num_resources
= ARRAY_SIZE(tmu00_resources
),
164 static struct sh_timer_config tmu01_platform_data
= {
166 .channel_offset
= 0x10,
168 .clocksource_rating
= 200,
171 static struct resource tmu01_resources
[] = {
172 [0] = DEFINE_RES_MEM(0xfff60014, 0xc),
174 .start
= intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
175 .flags
= IORESOURCE_IRQ
,
179 static struct platform_device tmu01_device
= {
183 .platform_data
= &tmu01_platform_data
,
185 .resource
= tmu01_resources
,
186 .num_resources
= ARRAY_SIZE(tmu01_resources
),
189 static struct resource i2c0_resources
[] = {
190 [0] = DEFINE_RES_MEM(0xe6820000, 0x426),
192 .start
= gic_spi(167),
194 .flags
= IORESOURCE_IRQ
,
198 static struct resource i2c1_resources
[] = {
199 [0] = DEFINE_RES_MEM(0xe6822000, 0x426),
201 .start
= gic_spi(51),
203 .flags
= IORESOURCE_IRQ
,
207 static struct resource i2c2_resources
[] = {
208 [0] = DEFINE_RES_MEM(0xe6824000, 0x426),
210 .start
= gic_spi(171),
212 .flags
= IORESOURCE_IRQ
,
216 static struct resource i2c3_resources
[] = {
217 [0] = DEFINE_RES_MEM(0xe6826000, 0x426),
219 .start
= gic_spi(183),
221 .flags
= IORESOURCE_IRQ
,
225 static struct resource i2c4_resources
[] = {
226 [0] = DEFINE_RES_MEM(0xe6828000, 0x426),
228 .start
= gic_spi(187),
230 .flags
= IORESOURCE_IRQ
,
234 static struct platform_device i2c0_device
= {
235 .name
= "i2c-sh_mobile",
237 .resource
= i2c0_resources
,
238 .num_resources
= ARRAY_SIZE(i2c0_resources
),
241 static struct platform_device i2c1_device
= {
242 .name
= "i2c-sh_mobile",
244 .resource
= i2c1_resources
,
245 .num_resources
= ARRAY_SIZE(i2c1_resources
),
248 static struct platform_device i2c2_device
= {
249 .name
= "i2c-sh_mobile",
251 .resource
= i2c2_resources
,
252 .num_resources
= ARRAY_SIZE(i2c2_resources
),
255 static struct platform_device i2c3_device
= {
256 .name
= "i2c-sh_mobile",
258 .resource
= i2c3_resources
,
259 .num_resources
= ARRAY_SIZE(i2c3_resources
),
262 static struct platform_device i2c4_device
= {
263 .name
= "i2c-sh_mobile",
265 .resource
= i2c4_resources
,
266 .num_resources
= ARRAY_SIZE(i2c4_resources
),
269 static const struct sh_dmae_slave_config sh73a0_dmae_slaves
[] = {
271 .slave_id
= SHDMA_SLAVE_SCIF0_TX
,
273 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
276 .slave_id
= SHDMA_SLAVE_SCIF0_RX
,
278 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
281 .slave_id
= SHDMA_SLAVE_SCIF1_TX
,
283 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
286 .slave_id
= SHDMA_SLAVE_SCIF1_RX
,
288 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
291 .slave_id
= SHDMA_SLAVE_SCIF2_TX
,
293 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
296 .slave_id
= SHDMA_SLAVE_SCIF2_RX
,
298 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
301 .slave_id
= SHDMA_SLAVE_SCIF3_TX
,
303 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
306 .slave_id
= SHDMA_SLAVE_SCIF3_RX
,
308 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
311 .slave_id
= SHDMA_SLAVE_SCIF4_TX
,
313 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
316 .slave_id
= SHDMA_SLAVE_SCIF4_RX
,
318 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
321 .slave_id
= SHDMA_SLAVE_SCIF5_TX
,
323 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
326 .slave_id
= SHDMA_SLAVE_SCIF5_RX
,
328 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
331 .slave_id
= SHDMA_SLAVE_SCIF6_TX
,
333 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
336 .slave_id
= SHDMA_SLAVE_SCIF6_RX
,
338 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
341 .slave_id
= SHDMA_SLAVE_SCIF7_TX
,
343 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
346 .slave_id
= SHDMA_SLAVE_SCIF7_RX
,
348 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
351 .slave_id
= SHDMA_SLAVE_SCIF8_TX
,
353 .chcr
= CHCR_TX(XMIT_SZ_8BIT
),
356 .slave_id
= SHDMA_SLAVE_SCIF8_RX
,
358 .chcr
= CHCR_RX(XMIT_SZ_8BIT
),
361 .slave_id
= SHDMA_SLAVE_SDHI0_TX
,
363 .chcr
= CHCR_TX(XMIT_SZ_16BIT
),
366 .slave_id
= SHDMA_SLAVE_SDHI0_RX
,
368 .chcr
= CHCR_RX(XMIT_SZ_16BIT
),
371 .slave_id
= SHDMA_SLAVE_SDHI1_TX
,
373 .chcr
= CHCR_TX(XMIT_SZ_16BIT
),
376 .slave_id
= SHDMA_SLAVE_SDHI1_RX
,
378 .chcr
= CHCR_RX(XMIT_SZ_16BIT
),
381 .slave_id
= SHDMA_SLAVE_SDHI2_TX
,
383 .chcr
= CHCR_TX(XMIT_SZ_16BIT
),
386 .slave_id
= SHDMA_SLAVE_SDHI2_RX
,
388 .chcr
= CHCR_RX(XMIT_SZ_16BIT
),
391 .slave_id
= SHDMA_SLAVE_MMCIF_TX
,
393 .chcr
= CHCR_TX(XMIT_SZ_32BIT
),
396 .slave_id
= SHDMA_SLAVE_MMCIF_RX
,
398 .chcr
= CHCR_RX(XMIT_SZ_32BIT
),
403 #define DMAE_CHANNEL(_offset) \
405 .offset = _offset - 0x20, \
406 .dmars = _offset - 0x20 + 0x40, \
409 static const struct sh_dmae_channel sh73a0_dmae_channels
[] = {
410 DMAE_CHANNEL(0x8000),
411 DMAE_CHANNEL(0x8080),
412 DMAE_CHANNEL(0x8100),
413 DMAE_CHANNEL(0x8180),
414 DMAE_CHANNEL(0x8200),
415 DMAE_CHANNEL(0x8280),
416 DMAE_CHANNEL(0x8300),
417 DMAE_CHANNEL(0x8380),
418 DMAE_CHANNEL(0x8400),
419 DMAE_CHANNEL(0x8480),
420 DMAE_CHANNEL(0x8500),
421 DMAE_CHANNEL(0x8580),
422 DMAE_CHANNEL(0x8600),
423 DMAE_CHANNEL(0x8680),
424 DMAE_CHANNEL(0x8700),
425 DMAE_CHANNEL(0x8780),
426 DMAE_CHANNEL(0x8800),
427 DMAE_CHANNEL(0x8880),
428 DMAE_CHANNEL(0x8900),
429 DMAE_CHANNEL(0x8980),
432 static struct sh_dmae_pdata sh73a0_dmae_platform_data
= {
433 .slave
= sh73a0_dmae_slaves
,
434 .slave_num
= ARRAY_SIZE(sh73a0_dmae_slaves
),
435 .channel
= sh73a0_dmae_channels
,
436 .channel_num
= ARRAY_SIZE(sh73a0_dmae_channels
),
437 .ts_low_shift
= TS_LOW_SHIFT
,
438 .ts_low_mask
= TS_LOW_BIT
<< TS_LOW_SHIFT
,
439 .ts_high_shift
= TS_HI_SHIFT
,
440 .ts_high_mask
= TS_HI_BIT
<< TS_HI_SHIFT
,
441 .ts_shift
= dma_ts_shift
,
442 .ts_shift_num
= ARRAY_SIZE(dma_ts_shift
),
443 .dmaor_init
= DMAOR_DME
,
446 static struct resource sh73a0_dmae_resources
[] = {
447 DEFINE_RES_MEM(0xfe000020, 0x89e0),
450 .start
= gic_spi(129),
452 .flags
= IORESOURCE_IRQ
,
455 /* IRQ for channels 0-19 */
456 .start
= gic_spi(109),
458 .flags
= IORESOURCE_IRQ
,
462 static struct platform_device dma0_device
= {
463 .name
= "sh-dma-engine",
465 .resource
= sh73a0_dmae_resources
,
466 .num_resources
= ARRAY_SIZE(sh73a0_dmae_resources
),
468 .platform_data
= &sh73a0_dmae_platform_data
,
473 static const struct sh_dmae_slave_config sh73a0_mpdma_slaves
[] = {
475 .slave_id
= SHDMA_SLAVE_FSI2A_RX
,
477 .chcr
= CHCR_RX(XMIT_SZ_32BIT
),
478 .mid_rid
= 0xd6, /* CHECK ME */
480 .slave_id
= SHDMA_SLAVE_FSI2A_TX
,
482 .chcr
= CHCR_TX(XMIT_SZ_32BIT
),
483 .mid_rid
= 0xd5, /* CHECK ME */
485 .slave_id
= SHDMA_SLAVE_FSI2C_RX
,
487 .chcr
= CHCR_RX(XMIT_SZ_32BIT
),
488 .mid_rid
= 0xda, /* CHECK ME */
490 .slave_id
= SHDMA_SLAVE_FSI2C_TX
,
492 .chcr
= CHCR_TX(XMIT_SZ_32BIT
),
493 .mid_rid
= 0xd9, /* CHECK ME */
495 .slave_id
= SHDMA_SLAVE_FSI2B_RX
,
497 .chcr
= CHCR_RX(XMIT_SZ_32BIT
),
498 .mid_rid
= 0x8e, /* CHECK ME */
500 .slave_id
= SHDMA_SLAVE_FSI2B_TX
,
502 .chcr
= CHCR_RX(XMIT_SZ_32BIT
),
503 .mid_rid
= 0x8d, /* CHECK ME */
505 .slave_id
= SHDMA_SLAVE_FSI2D_RX
,
507 .chcr
= CHCR_RX(XMIT_SZ_32BIT
),
508 .mid_rid
= 0x9a, /* CHECK ME */
512 #define MPDMA_CHANNEL(a, b, c) \
517 .chclr_offset = (0x220 - 0x20) + a \
520 static const struct sh_dmae_channel sh73a0_mpdma_channels
[] = {
521 MPDMA_CHANNEL(0x00, 0, 0),
522 MPDMA_CHANNEL(0x10, 0, 8),
523 MPDMA_CHANNEL(0x20, 4, 0),
524 MPDMA_CHANNEL(0x30, 4, 8),
525 MPDMA_CHANNEL(0x50, 8, 0),
526 MPDMA_CHANNEL(0x70, 8, 8),
529 static struct sh_dmae_pdata sh73a0_mpdma_platform_data
= {
530 .slave
= sh73a0_mpdma_slaves
,
531 .slave_num
= ARRAY_SIZE(sh73a0_mpdma_slaves
),
532 .channel
= sh73a0_mpdma_channels
,
533 .channel_num
= ARRAY_SIZE(sh73a0_mpdma_channels
),
534 .ts_low_shift
= TS_LOW_SHIFT
,
535 .ts_low_mask
= TS_LOW_BIT
<< TS_LOW_SHIFT
,
536 .ts_high_shift
= TS_HI_SHIFT
,
537 .ts_high_mask
= TS_HI_BIT
<< TS_HI_SHIFT
,
538 .ts_shift
= dma_ts_shift
,
539 .ts_shift_num
= ARRAY_SIZE(dma_ts_shift
),
540 .dmaor_init
= DMAOR_DME
,
544 /* Resource order important! */
545 static struct resource sh73a0_mpdma_resources
[] = {
546 /* Channel registers and DMAOR */
547 DEFINE_RES_MEM(0xec618020, 0x270),
549 DEFINE_RES_MEM(0xec619000, 0xc),
552 .start
= gic_spi(181),
554 .flags
= IORESOURCE_IRQ
,
557 /* IRQ for channels 0-5 */
558 .start
= gic_spi(175),
560 .flags
= IORESOURCE_IRQ
,
564 static struct platform_device mpdma0_device
= {
565 .name
= "sh-dma-engine",
567 .resource
= sh73a0_mpdma_resources
,
568 .num_resources
= ARRAY_SIZE(sh73a0_mpdma_resources
),
570 .platform_data
= &sh73a0_mpdma_platform_data
,
574 static struct resource pmu_resources
[] = {
576 .start
= gic_spi(55),
578 .flags
= IORESOURCE_IRQ
,
581 .start
= gic_spi(56),
583 .flags
= IORESOURCE_IRQ
,
587 static struct platform_device pmu_device
= {
590 .num_resources
= ARRAY_SIZE(pmu_resources
),
591 .resource
= pmu_resources
,
594 /* an IPMMU module for ICB */
595 static struct resource ipmmu_resources
[] = {
596 DEFINE_RES_MEM(0xfe951000, 0x100),
599 static const char * const ipmmu_dev_names
[] = {
600 "sh_mobile_lcdc_fb.0",
603 static struct shmobile_ipmmu_platform_data ipmmu_platform_data
= {
604 .dev_names
= ipmmu_dev_names
,
605 .num_dev_names
= ARRAY_SIZE(ipmmu_dev_names
),
608 static struct platform_device ipmmu_device
= {
612 .platform_data
= &ipmmu_platform_data
,
614 .resource
= ipmmu_resources
,
615 .num_resources
= ARRAY_SIZE(ipmmu_resources
),
618 static struct renesas_intc_irqpin_config irqpin0_platform_data
= {
619 .irq_base
= irq_pin(0), /* IRQ0 -> IRQ7 */
622 static struct resource irqpin0_resources
[] = {
623 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
624 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
625 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
626 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
627 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
628 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ0 */
629 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ1 */
630 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ2 */
631 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ3 */
632 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ4 */
633 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ5 */
634 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ6 */
635 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ7 */
638 static struct platform_device irqpin0_device
= {
639 .name
= "renesas_intc_irqpin",
641 .resource
= irqpin0_resources
,
642 .num_resources
= ARRAY_SIZE(irqpin0_resources
),
644 .platform_data
= &irqpin0_platform_data
,
648 static struct renesas_intc_irqpin_config irqpin1_platform_data
= {
649 .irq_base
= irq_pin(8), /* IRQ8 -> IRQ15 */
650 .control_parent
= true, /* Disable spurious IRQ10 */
653 static struct resource irqpin1_resources
[] = {
654 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
655 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
656 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
657 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
658 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
659 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ8 */
660 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ9 */
661 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ10 */
662 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ11 */
663 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ12 */
664 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ13 */
665 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ14 */
666 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ15 */
669 static struct platform_device irqpin1_device
= {
670 .name
= "renesas_intc_irqpin",
672 .resource
= irqpin1_resources
,
673 .num_resources
= ARRAY_SIZE(irqpin1_resources
),
675 .platform_data
= &irqpin1_platform_data
,
679 static struct renesas_intc_irqpin_config irqpin2_platform_data
= {
680 .irq_base
= irq_pin(16), /* IRQ16 -> IRQ23 */
683 static struct resource irqpin2_resources
[] = {
684 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
685 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI20A */
686 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ20A */
687 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK20A */
688 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR20A */
689 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ16 */
690 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ17 */
691 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ18 */
692 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ19 */
693 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ20 */
694 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ21 */
695 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ22 */
696 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ23 */
699 static struct platform_device irqpin2_device
= {
700 .name
= "renesas_intc_irqpin",
702 .resource
= irqpin2_resources
,
703 .num_resources
= ARRAY_SIZE(irqpin2_resources
),
705 .platform_data
= &irqpin2_platform_data
,
709 static struct renesas_intc_irqpin_config irqpin3_platform_data
= {
710 .irq_base
= irq_pin(24), /* IRQ24 -> IRQ31 */
713 static struct resource irqpin3_resources
[] = {
714 DEFINE_RES_MEM(0xe690000c, 4), /* ICR4A */
715 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
716 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
717 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
718 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
719 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ24 */
720 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ25 */
721 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ26 */
722 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ27 */
723 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ28 */
724 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ29 */
725 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ30 */
726 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ31 */
729 static struct platform_device irqpin3_device
= {
730 .name
= "renesas_intc_irqpin",
732 .resource
= irqpin3_resources
,
733 .num_resources
= ARRAY_SIZE(irqpin3_resources
),
735 .platform_data
= &irqpin3_platform_data
,
739 static struct platform_device
*sh73a0_devices_dt
[] __initdata
= {
752 static struct platform_device
*sh73a0_early_devices
[] __initdata
= {
758 static struct platform_device
*sh73a0_late_devices
[] __initdata
= {
773 #define SRCR2 IOMEM(0xe61580b0)
775 void __init
sh73a0_add_standard_devices(void)
777 /* Clear software reset bit on SY-DMAC module */
778 __raw_writel(__raw_readl(SRCR2
) & ~(1 << 18), SRCR2
);
780 platform_add_devices(sh73a0_devices_dt
,
781 ARRAY_SIZE(sh73a0_devices_dt
));
782 platform_add_devices(sh73a0_early_devices
,
783 ARRAY_SIZE(sh73a0_early_devices
));
784 platform_add_devices(sh73a0_late_devices
,
785 ARRAY_SIZE(sh73a0_late_devices
));
788 void __init
sh73a0_init_delay(void)
790 shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
793 /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */
794 void __init __weak
sh73a0_register_twd(void) { }
796 void __init
sh73a0_earlytimer_init(void)
800 shmobile_earlytimer_init();
801 sh73a0_register_twd();
804 void __init
sh73a0_add_early_devices(void)
806 early_platform_add_devices(sh73a0_devices_dt
,
807 ARRAY_SIZE(sh73a0_devices_dt
));
808 early_platform_add_devices(sh73a0_early_devices
,
809 ARRAY_SIZE(sh73a0_early_devices
));
811 /* setup early console here as well */
812 shmobile_setup_console();
817 void __init
sh73a0_add_standard_devices_dt(void)
819 struct platform_device_info devinfo
= { .name
= "cpufreq-cpu0", .id
= -1, };
821 /* clocks are setup late during boot in the case of DT */
824 platform_add_devices(sh73a0_devices_dt
,
825 ARRAY_SIZE(sh73a0_devices_dt
));
826 of_platform_populate(NULL
, of_default_bus_match_table
, NULL
, NULL
);
828 /* Instantiate cpufreq-cpu0 */
829 platform_device_register_full(&devinfo
);
832 static const char *sh73a0_boards_compat_dt
[] __initdata
= {
837 DT_MACHINE_START(SH73A0_DT
, "Generic SH73A0 (Flattened Device Tree)")
838 .smp
= smp_ops(sh73a0_smp_ops
),
839 .map_io
= sh73a0_map_io
,
840 .init_early
= sh73a0_init_delay
,
841 .nr_irqs
= NR_IRQS_LEGACY
,
842 .init_machine
= sh73a0_add_standard_devices_dt
,
843 .dt_compat
= sh73a0_boards_compat_dt
,
845 #endif /* CONFIG_USE_OF */