arch/arm/mach-spear3xx/spear320.c

   1 /*
   2  * arch/arm/mach-spear3xx/spear320.c
   3  *
   4  * SPEAr320 machine source file
   5  *
   6  * Copyright (C) 2009 ST Microelectronics
   7  * Viresh Kumar<viresh.kumar@st.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include <linux/ptrace.h>
  15 #include <asm/irq.h>
  16 #include <mach/generic.h>
  17 #include <mach/spear.h>
  18 #include <plat/shirq.h>
  19
  20 /* pad multiplexing support */
  21 /* muxing registers */
  22 #define PAD_MUX_CONFIG_REG      0x0C
  23 #define MODE_CONFIG_REG         0x10
  24
  25 /* modes */
  26 #define AUTO_NET_SMII_MODE      (1 << 0)
  27 #define AUTO_NET_MII_MODE       (1 << 1)
  28 #define AUTO_EXP_MODE           (1 << 2)
  29 #define SMALL_PRINTERS_MODE     (1 << 3)
  30 #define ALL_MODES               0xF
  31
  32 struct pmx_mode auto_net_smii_mode = {
  33         .id = AUTO_NET_SMII_MODE,
  34         .name = "Automation Networking SMII Mode",
  35         .mask = 0x00,
  36 };
  37
  38 struct pmx_mode auto_net_mii_mode = {
  39         .id = AUTO_NET_MII_MODE,
  40         .name = "Automation Networking MII Mode",
  41         .mask = 0x01,
  42 };
  43
  44 struct pmx_mode auto_exp_mode = {
  45         .id = AUTO_EXP_MODE,
  46         .name = "Automation Expanded Mode",
  47         .mask = 0x02,
  48 };
  49
  50 struct pmx_mode small_printers_mode = {
  51         .id = SMALL_PRINTERS_MODE,
  52         .name = "Small Printers Mode",
  53         .mask = 0x03,
  54 };
  55
  56 /* devices */
  57 struct pmx_dev_mode pmx_clcd_modes[] = {
  58         {
  59                 .ids = AUTO_NET_SMII_MODE,
  60                 .mask = 0x0,
  61         },
  62 };
  63
  64 struct pmx_dev pmx_clcd = {
  65         .name = "clcd",
  66         .modes = pmx_clcd_modes,
  67         .mode_count = ARRAY_SIZE(pmx_clcd_modes),
  68         .enb_on_reset = 1,
  69 };
  70
  71 struct pmx_dev_mode pmx_emi_modes[] = {
  72         {
  73                 .ids = AUTO_EXP_MODE,
  74                 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
  75         },
  76 };
  77
  78 struct pmx_dev pmx_emi = {
  79         .name = "emi",
  80         .modes = pmx_emi_modes,
  81         .mode_count = ARRAY_SIZE(pmx_emi_modes),
  82         .enb_on_reset = 1,
  83 };
  84
  85 struct pmx_dev_mode pmx_fsmc_modes[] = {
  86         {
  87                 .ids = ALL_MODES,
  88                 .mask = 0x0,
  89         },
  90 };
  91
  92 struct pmx_dev pmx_fsmc = {
  93         .name = "fsmc",
  94         .modes = pmx_fsmc_modes,
  95         .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
  96         .enb_on_reset = 1,
  97 };
  98
  99 struct pmx_dev_mode pmx_spp_modes[] = {
 100         {
 101                 .ids = SMALL_PRINTERS_MODE,
 102                 .mask = 0x0,
 103         },
 104 };
 105
 106 struct pmx_dev pmx_spp = {
 107         .name = "spp",
 108         .modes = pmx_spp_modes,
 109         .mode_count = ARRAY_SIZE(pmx_spp_modes),
 110         .enb_on_reset = 1,
 111 };
 112
 113 struct pmx_dev_mode pmx_sdio_modes[] = {
 114         {
 115                 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
 116                         SMALL_PRINTERS_MODE,
 117                 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
 118         },
 119 };
 120
 121 struct pmx_dev pmx_sdio = {
 122         .name = "sdio",
 123         .modes = pmx_sdio_modes,
 124         .mode_count = ARRAY_SIZE(pmx_sdio_modes),
 125         .enb_on_reset = 1,
 126 };
 127
 128 struct pmx_dev_mode pmx_i2s_modes[] = {
 129         {
 130                 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
 131                 .mask = PMX_UART0_MODEM_MASK,
 132         },
 133 };
 134
 135 struct pmx_dev pmx_i2s = {
 136         .name = "i2s",
 137         .modes = pmx_i2s_modes,
 138         .mode_count = ARRAY_SIZE(pmx_i2s_modes),
 139         .enb_on_reset = 1,
 140 };
 141
 142 struct pmx_dev_mode pmx_uart1_modes[] = {
 143         {
 144                 .ids = ALL_MODES,
 145                 .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
 146         },
 147 };
 148
 149 struct pmx_dev pmx_uart1 = {
 150         .name = "uart1",
 151         .modes = pmx_uart1_modes,
 152         .mode_count = ARRAY_SIZE(pmx_uart1_modes),
 153         .enb_on_reset = 1,
 154 };
 155
 156 struct pmx_dev_mode pmx_uart1_modem_modes[] = {
 157         {
 158                 .ids = AUTO_EXP_MODE,
 159                 .mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
 160                         PMX_SSP_CS_MASK,
 161         }, {
 162                 .ids = SMALL_PRINTERS_MODE,
 163                 .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK |
 164                         PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK,
 165         },
 166 };
 167
 168 struct pmx_dev pmx_uart1_modem = {
 169         .name = "uart1_modem",
 170         .modes = pmx_uart1_modem_modes,
 171         .mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
 172         .enb_on_reset = 1,
 173 };
 174
 175 struct pmx_dev_mode pmx_uart2_modes[] = {
 176         {
 177                 .ids = ALL_MODES,
 178                 .mask = PMX_FIRDA_MASK,
 179         },
 180 };
 181
 182 struct pmx_dev pmx_uart2 = {
 183         .name = "uart2",
 184         .modes = pmx_uart2_modes,
 185         .mode_count = ARRAY_SIZE(pmx_uart2_modes),
 186         .enb_on_reset = 1,
 187 };
 188
 189 struct pmx_dev_mode pmx_touchscreen_modes[] = {
 190         {
 191                 .ids = AUTO_NET_SMII_MODE,
 192                 .mask = PMX_SSP_CS_MASK,
 193         },
 194 };
 195
 196 struct pmx_dev pmx_touchscreen = {
 197         .name = "touchscreen",
 198         .modes = pmx_touchscreen_modes,
 199         .mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
 200         .enb_on_reset = 1,
 201 };
 202
 203 struct pmx_dev_mode pmx_can_modes[] = {
 204         {
 205                 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
 206                 .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
 207                         PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK,
 208         },
 209 };
 210
 211 struct pmx_dev pmx_can = {
 212         .name = "can",
 213         .modes = pmx_can_modes,
 214         .mode_count = ARRAY_SIZE(pmx_can_modes),
 215         .enb_on_reset = 1,
 216 };
 217
 218 struct pmx_dev_mode pmx_sdio_led_modes[] = {
 219         {
 220                 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
 221                 .mask = PMX_SSP_CS_MASK,
 222         },
 223 };
 224
 225 struct pmx_dev pmx_sdio_led = {
 226         .name = "sdio_led",
 227         .modes = pmx_sdio_led_modes,
 228         .mode_count = ARRAY_SIZE(pmx_sdio_led_modes),
 229         .enb_on_reset = 1,
 230 };
 231
 232 struct pmx_dev_mode pmx_pwm0_modes[] = {
 233         {
 234                 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
 235                 .mask = PMX_UART0_MODEM_MASK,
 236         }, {
 237                 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
 238                 .mask = PMX_MII_MASK,
 239         },
 240 };
 241
 242 struct pmx_dev pmx_pwm0 = {
 243         .name = "pwm0",
 244         .modes = pmx_pwm0_modes,
 245         .mode_count = ARRAY_SIZE(pmx_pwm0_modes),
 246         .enb_on_reset = 1,
 247 };
 248
 249 struct pmx_dev_mode pmx_pwm1_modes[] = {
 250         {
 251                 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
 252                 .mask = PMX_UART0_MODEM_MASK,
 253         }, {
 254                 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
 255                 .mask = PMX_MII_MASK,
 256         },
 257 };
 258
 259 struct pmx_dev pmx_pwm1 = {
 260         .name = "pwm1",
 261         .modes = pmx_pwm1_modes,
 262         .mode_count = ARRAY_SIZE(pmx_pwm1_modes),
 263         .enb_on_reset = 1,
 264 };
 265
 266 struct pmx_dev_mode pmx_pwm2_modes[] = {
 267         {
 268                 .ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
 269                 .mask = PMX_SSP_CS_MASK,
 270         }, {
 271                 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
 272                 .mask = PMX_MII_MASK,
 273         },
 274 };
 275
 276 struct pmx_dev pmx_pwm2 = {
 277         .name = "pwm2",
 278         .modes = pmx_pwm2_modes,
 279         .mode_count = ARRAY_SIZE(pmx_pwm2_modes),
 280         .enb_on_reset = 1,
 281 };
 282
 283 struct pmx_dev_mode pmx_pwm3_modes[] = {
 284         {
 285                 .ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
 286                 .mask = PMX_MII_MASK,
 287         },
 288 };
 289
 290 struct pmx_dev pmx_pwm3 = {
 291         .name = "pwm3",
 292         .modes = pmx_pwm3_modes,
 293         .mode_count = ARRAY_SIZE(pmx_pwm3_modes),
 294         .enb_on_reset = 1,
 295 };
 296
 297 struct pmx_dev_mode pmx_ssp1_modes[] = {
 298         {
 299                 .ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
 300                 .mask = PMX_MII_MASK,
 301         },
 302 };
 303
 304 struct pmx_dev pmx_ssp1 = {
 305         .name = "ssp1",
 306         .modes = pmx_ssp1_modes,
 307         .mode_count = ARRAY_SIZE(pmx_ssp1_modes),
 308         .enb_on_reset = 1,
 309 };
 310
 311 struct pmx_dev_mode pmx_ssp2_modes[] = {
 312         {
 313                 .ids = AUTO_NET_SMII_MODE,
 314                 .mask = PMX_MII_MASK,
 315         },
 316 };
 317
 318 struct pmx_dev pmx_ssp2 = {
 319         .name = "ssp2",
 320         .modes = pmx_ssp2_modes,
 321         .mode_count = ARRAY_SIZE(pmx_ssp2_modes),
 322         .enb_on_reset = 1,
 323 };
 324
 325 struct pmx_dev_mode pmx_mii1_modes[] = {
 326         {
 327                 .ids = AUTO_NET_MII_MODE,
 328                 .mask = 0x0,
 329         },
 330 };
 331
 332 struct pmx_dev pmx_mii1 = {
 333         .name = "mii1",
 334         .modes = pmx_mii1_modes,
 335         .mode_count = ARRAY_SIZE(pmx_mii1_modes),
 336         .enb_on_reset = 1,
 337 };
 338
 339 struct pmx_dev_mode pmx_smii0_modes[] = {
 340         {
 341                 .ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
 342                 .mask = PMX_MII_MASK,
 343         },
 344 };
 345
 346 struct pmx_dev pmx_smii0 = {
 347         .name = "smii0",
 348         .modes = pmx_smii0_modes,
 349         .mode_count = ARRAY_SIZE(pmx_smii0_modes),
 350         .enb_on_reset = 1,
 351 };
 352
 353 struct pmx_dev_mode pmx_smii1_modes[] = {
 354         {
 355                 .ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
 356                 .mask = PMX_MII_MASK,
 357         },
 358 };
 359
 360 struct pmx_dev pmx_smii1 = {
 361         .name = "smii1",
 362         .modes = pmx_smii1_modes,
 363         .mode_count = ARRAY_SIZE(pmx_smii1_modes),
 364         .enb_on_reset = 1,
 365 };
 366
 367 struct pmx_dev_mode pmx_i2c1_modes[] = {
 368         {
 369                 .ids = AUTO_EXP_MODE,
 370                 .mask = 0x0,
 371         },
 372 };
 373
 374 struct pmx_dev pmx_i2c1 = {
 375         .name = "i2c1",
 376         .modes = pmx_i2c1_modes,
 377         .mode_count = ARRAY_SIZE(pmx_i2c1_modes),
 378         .enb_on_reset = 1,
 379 };
 380
 381 /* pmx driver structure */
 382 struct pmx_driver pmx_driver = {
 383         .mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
 384         .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
 385 };
 386
 387 /* Add spear320 specific devices here */
 388
 389 /* spear3xx shared irq */
 390 struct shirq_dev_config shirq_ras1_config[] = {
 391         {
 392                 .virq = VIRQ_EMI,
 393                 .status_mask = EMI_IRQ_MASK,
 394                 .clear_mask = EMI_IRQ_MASK,
 395         }, {
 396                 .virq = VIRQ_CLCD,
 397                 .status_mask = CLCD_IRQ_MASK,
 398                 .clear_mask = CLCD_IRQ_MASK,
 399         }, {
 400                 .virq = VIRQ_SPP,
 401                 .status_mask = SPP_IRQ_MASK,
 402                 .clear_mask = SPP_IRQ_MASK,
 403         },
 404 };
 405
 406 struct spear_shirq shirq_ras1 = {
 407         .irq = IRQ_GEN_RAS_1,
 408         .dev_config = shirq_ras1_config,
 409         .dev_count = ARRAY_SIZE(shirq_ras1_config),
 410         .regs = {
 411                 .enb_reg = -1,
 412                 .status_reg = INT_STS_MASK_REG,
 413                 .status_reg_mask = SHIRQ_RAS1_MASK,
 414                 .clear_reg = INT_CLR_MASK_REG,
 415                 .reset_to_clear = 1,
 416         },
 417 };
 418
 419 struct shirq_dev_config shirq_ras3_config[] = {
 420         {
 421                 .virq = VIRQ_PLGPIO,
 422                 .enb_mask = GPIO_IRQ_MASK,
 423                 .status_mask = GPIO_IRQ_MASK,
 424                 .clear_mask = GPIO_IRQ_MASK,
 425         }, {
 426                 .virq = VIRQ_I2S_PLAY,
 427                 .enb_mask = I2S_PLAY_IRQ_MASK,
 428                 .status_mask = I2S_PLAY_IRQ_MASK,
 429                 .clear_mask = I2S_PLAY_IRQ_MASK,
 430         }, {
 431                 .virq = VIRQ_I2S_REC,
 432                 .enb_mask = I2S_REC_IRQ_MASK,
 433                 .status_mask = I2S_REC_IRQ_MASK,
 434                 .clear_mask = I2S_REC_IRQ_MASK,
 435         },
 436 };
 437
 438 struct spear_shirq shirq_ras3 = {
 439         .irq = IRQ_GEN_RAS_3,
 440         .dev_config = shirq_ras3_config,
 441         .dev_count = ARRAY_SIZE(shirq_ras3_config),
 442         .regs = {
 443                 .enb_reg = INT_ENB_MASK_REG,
 444                 .reset_to_enb = 1,
 445                 .status_reg = INT_STS_MASK_REG,
 446                 .status_reg_mask = SHIRQ_RAS3_MASK,
 447                 .clear_reg = INT_CLR_MASK_REG,
 448                 .reset_to_clear = 1,
 449         },
 450 };
 451
 452 struct shirq_dev_config shirq_intrcomm_ras_config[] = {
 453         {
 454                 .virq = VIRQ_CANU,
 455                 .status_mask = CAN_U_IRQ_MASK,
 456                 .clear_mask = CAN_U_IRQ_MASK,
 457         }, {
 458                 .virq = VIRQ_CANL,
 459                 .status_mask = CAN_L_IRQ_MASK,
 460                 .clear_mask = CAN_L_IRQ_MASK,
 461         }, {
 462                 .virq = VIRQ_UART1,
 463                 .status_mask = UART1_IRQ_MASK,
 464                 .clear_mask = UART1_IRQ_MASK,
 465         }, {
 466                 .virq = VIRQ_UART2,
 467                 .status_mask = UART2_IRQ_MASK,
 468                 .clear_mask = UART2_IRQ_MASK,
 469         }, {
 470                 .virq = VIRQ_SSP1,
 471                 .status_mask = SSP1_IRQ_MASK,
 472                 .clear_mask = SSP1_IRQ_MASK,
 473         }, {
 474                 .virq = VIRQ_SSP2,
 475                 .status_mask = SSP2_IRQ_MASK,
 476                 .clear_mask = SSP2_IRQ_MASK,
 477         }, {
 478                 .virq = VIRQ_SMII0,
 479                 .status_mask = SMII0_IRQ_MASK,
 480                 .clear_mask = SMII0_IRQ_MASK,
 481         }, {
 482                 .virq = VIRQ_MII1_SMII1,
 483                 .status_mask = MII1_SMII1_IRQ_MASK,
 484                 .clear_mask = MII1_SMII1_IRQ_MASK,
 485         }, {
 486                 .virq = VIRQ_WAKEUP_SMII0,
 487                 .status_mask = WAKEUP_SMII0_IRQ_MASK,
 488                 .clear_mask = WAKEUP_SMII0_IRQ_MASK,
 489         }, {
 490                 .virq = VIRQ_WAKEUP_MII1_SMII1,
 491                 .status_mask = WAKEUP_MII1_SMII1_IRQ_MASK,
 492                 .clear_mask = WAKEUP_MII1_SMII1_IRQ_MASK,
 493         }, {
 494                 .virq = VIRQ_I2C,
 495                 .status_mask = I2C1_IRQ_MASK,
 496                 .clear_mask = I2C1_IRQ_MASK,
 497         },
 498 };
 499
 500 struct spear_shirq shirq_intrcomm_ras = {
 501         .irq = IRQ_INTRCOMM_RAS_ARM,
 502         .dev_config = shirq_intrcomm_ras_config,
 503         .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
 504         .regs = {
 505                 .enb_reg = -1,
 506                 .status_reg = INT_STS_MASK_REG,
 507                 .status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK,
 508                 .clear_reg = INT_CLR_MASK_REG,
 509                 .reset_to_clear = 1,
 510         },
 511 };
 512
 513 /* spear320 routines */
 514 void __init spear320_init(void)
 515 {
 516         void __iomem *base;
 517         int ret = 0;
 518
 519         /* call spear3xx family common init function */
 520         spear3xx_init();
 521
 522         /* shared irq registration */
 523         base = ioremap(SPEAR320_SOC_CONFIG_BASE, SPEAR320_SOC_CONFIG_SIZE);
 524         if (base) {
 525                 /* shirq 1 */
 526                 shirq_ras1.regs.base = base;
 527                 ret = spear_shirq_register(&shirq_ras1);
 528                 if (ret)
 529                         printk(KERN_ERR "Error registering Shared IRQ 1\n");
 530
 531                 /* shirq 3 */
 532                 shirq_ras3.regs.base = base;
 533                 ret = spear_shirq_register(&shirq_ras3);
 534                 if (ret)
 535                         printk(KERN_ERR "Error registering Shared IRQ 3\n");
 536
 537                 /* shirq 4 */
 538                 shirq_intrcomm_ras.regs.base = base;
 539                 ret = spear_shirq_register(&shirq_intrcomm_ras);
 540                 if (ret)
 541                         printk(KERN_ERR "Error registering Shared IRQ 4\n");
 542         }
 543 }
 544
 545 void spear320_pmx_init(void)
 546 {
 547         spear_pmx_init(&pmx_driver, SPEAR320_SOC_CONFIG_BASE,
 548                         SPEAR320_SOC_CONFIG_SIZE);
 549 }