arch/arm/mach-tegra/reset.c

   1 /*
   2  * arch/arm/mach-tegra/reset.c
   3  *
   4  * Copyright (C) 2011,2012 NVIDIA Corporation.
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/bitops.h>
  18 #include <linux/cpumask.h>
  19 #include <linux/init.h>
  20 #include <linux/io.h>
  21
  22 #include <soc/tegra/fuse.h>
  23
  24 #include <asm/cacheflush.h>
  25 #include <asm/firmware.h>
  26 #include <asm/hardware/cache-l2x0.h>
  27
  28 #include "iomap.h"
  29 #include "irammap.h"
  30 #include "reset.h"
  31 #include "sleep.h"
  32
  33 #define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \
  34                                 TEGRA_IRAM_RESET_HANDLER_OFFSET)
  35
  36 static bool is_enabled;
  37
  38 static void __init tegra_cpu_reset_handler_set(const u32 reset_address)
  39 {
  40         void __iomem *evp_cpu_reset =
  41                 IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100);
  42         void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE);
  43         u32 reg;
  44
  45         /*
  46          * NOTE: This must be the one and only write to the EVP CPU reset
  47          *       vector in the entire system.
  48          */
  49         writel(reset_address, evp_cpu_reset);
  50         wmb();
  51         reg = readl(evp_cpu_reset);
  52
  53         /*
  54          * Prevent further modifications to the physical reset vector.
  55          *  NOTE: Has no effect on chips prior to Tegra30.
  56          */
  57         reg = readl(sb_ctrl);
  58         reg |= 2;
  59         writel(reg, sb_ctrl);
  60         wmb();
  61 }
  62
  63 static void __init tegra_cpu_reset_handler_enable(void)
  64 {
  65         void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE);
  66         const u32 reset_address = TEGRA_IRAM_RESET_BASE +
  67                                                 tegra_cpu_reset_handler_offset;
  68         int err;
  69
  70         BUG_ON(is_enabled);
  71         BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE);
  72
  73         memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start,
  74                         tegra_cpu_reset_handler_size);
  75
  76         err = call_firmware_op(set_cpu_boot_addr, 0, reset_address);
  77         switch (err) {
  78         case -ENOSYS:
  79                 tegra_cpu_reset_handler_set(reset_address);
  80                 /* pass-through */
  81         case 0:
  82                 is_enabled = true;
  83                 break;
  84         default:
  85                 pr_crit("Cannot set CPU reset handler: %d\n", err);
  86                 BUG();
  87         }
  88 }
  89
  90 void __init tegra_cpu_reset_handler_init(void)
  91 {
  92
  93 #ifdef CONFIG_SMP
  94         __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
  95                 *((u32 *)cpu_possible_mask);
  96         __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
  97                 virt_to_phys((void *)secondary_startup);
  98 #endif
  99
 100 #ifdef CONFIG_PM_SLEEP
 101         __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] =
 102                 TEGRA_IRAM_LPx_RESUME_AREA;
 103         __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] =
 104                 virt_to_phys((void *)tegra_resume);
 105 #endif
 106
 107         tegra_cpu_reset_handler_enable();
 108 }