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ARM: tegra: clock: Convert global lock to a lock per clock
[deliverable/linux.git] / arch / arm / mach-tegra / tegra2_clocks.c
1 /*
2 * arch/arm/mach-tegra/tegra2_clocks.c
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/list.h>
23 #include <linux/spinlock.h>
24 #include <linux/delay.h>
25 #include <linux/io.h>
26 #include <linux/clkdev.h>
27 #include <linux/clk.h>
28
29 #include <mach/iomap.h>
30 #include <mach/suspend.h>
31
32 #include "clock.h"
33 #include "fuse.h"
34
35 #define RST_DEVICES 0x004
36 #define RST_DEVICES_SET 0x300
37 #define RST_DEVICES_CLR 0x304
38 #define RST_DEVICES_NUM 3
39
40 #define CLK_OUT_ENB 0x010
41 #define CLK_OUT_ENB_SET 0x320
42 #define CLK_OUT_ENB_CLR 0x324
43 #define CLK_OUT_ENB_NUM 3
44
45 #define CLK_MASK_ARM 0x44
46 #define MISC_CLK_ENB 0x48
47
48 #define OSC_CTRL 0x50
49 #define OSC_CTRL_OSC_FREQ_MASK (3<<30)
50 #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
51 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
52 #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
53 #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
54 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
55
56 #define OSC_FREQ_DET 0x58
57 #define OSC_FREQ_DET_TRIG (1<<31)
58
59 #define OSC_FREQ_DET_STATUS 0x5C
60 #define OSC_FREQ_DET_BUSY (1<<31)
61 #define OSC_FREQ_DET_CNT_MASK 0xFFFF
62
63 #define PERIPH_CLK_SOURCE_I2S1 0x100
64 #define PERIPH_CLK_SOURCE_EMC 0x19c
65 #define PERIPH_CLK_SOURCE_OSC 0x1fc
66 #define PERIPH_CLK_SOURCE_NUM \
67 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
68
69 #define PERIPH_CLK_SOURCE_MASK (3<<30)
70 #define PERIPH_CLK_SOURCE_SHIFT 30
71 #define PERIPH_CLK_SOURCE_ENABLE (1<<28)
72 #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
73 #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
74 #define PERIPH_CLK_SOURCE_DIV_SHIFT 0
75
76 #define PLL_BASE 0x0
77 #define PLL_BASE_BYPASS (1<<31)
78 #define PLL_BASE_ENABLE (1<<30)
79 #define PLL_BASE_REF_ENABLE (1<<29)
80 #define PLL_BASE_OVERRIDE (1<<28)
81 #define PLL_BASE_DIVP_MASK (0x7<<20)
82 #define PLL_BASE_DIVP_SHIFT 20
83 #define PLL_BASE_DIVN_MASK (0x3FF<<8)
84 #define PLL_BASE_DIVN_SHIFT 8
85 #define PLL_BASE_DIVM_MASK (0x1F)
86 #define PLL_BASE_DIVM_SHIFT 0
87
88 #define PLL_OUT_RATIO_MASK (0xFF<<8)
89 #define PLL_OUT_RATIO_SHIFT 8
90 #define PLL_OUT_OVERRIDE (1<<2)
91 #define PLL_OUT_CLKEN (1<<1)
92 #define PLL_OUT_RESET_DISABLE (1<<0)
93
94 #define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
95
96 #define PLL_MISC_DCCON_SHIFT 20
97 #define PLL_MISC_CPCON_SHIFT 8
98 #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
99 #define PLL_MISC_LFCON_SHIFT 4
100 #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
101 #define PLL_MISC_VCOCON_SHIFT 0
102 #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
103
104 #define PLLU_BASE_POST_DIV (1<<20)
105
106 #define PLLD_MISC_CLKENABLE (1<<30)
107 #define PLLD_MISC_DIV_RST (1<<23)
108 #define PLLD_MISC_DCCON_SHIFT 12
109
110 #define PLLE_MISC_READY (1 << 15)
111
112 #define PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4)
113 #define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8)
114 #define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32))
115
116 #define SUPER_CLK_MUX 0x00
117 #define SUPER_STATE_SHIFT 28
118 #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
119 #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
120 #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
121 #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
122 #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
123 #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
124 #define SUPER_SOURCE_MASK 0xF
125 #define SUPER_FIQ_SOURCE_SHIFT 12
126 #define SUPER_IRQ_SOURCE_SHIFT 8
127 #define SUPER_RUN_SOURCE_SHIFT 4
128 #define SUPER_IDLE_SOURCE_SHIFT 0
129
130 #define SUPER_CLK_DIVIDER 0x04
131
132 #define BUS_CLK_DISABLE (1<<3)
133 #define BUS_CLK_DIV_MASK 0x3
134
135 #define PMC_CTRL 0x0
136 #define PMC_CTRL_BLINK_ENB (1 << 7)
137
138 #define PMC_DPD_PADS_ORIDE 0x1c
139 #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
140
141 #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
142 #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
143 #define PMC_BLINK_TIMER_ENB (1 << 15)
144 #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
145 #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
146
147 static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
148 static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
149
150 /*
151 * Some clocks share a register with other clocks. Any clock op that
152 * non-atomically modifies a register used by another clock must lock
153 * clock_register_lock first.
154 */
155 static DEFINE_SPINLOCK(clock_register_lock);
156
157 #define clk_writel(value, reg) \
158 __raw_writel(value, (u32)reg_clk_base + (reg))
159 #define clk_readl(reg) \
160 __raw_readl((u32)reg_clk_base + (reg))
161 #define pmc_writel(value, reg) \
162 __raw_writel(value, (u32)reg_pmc_base + (reg))
163 #define pmc_readl(reg) \
164 __raw_readl((u32)reg_pmc_base + (reg))
165
166 unsigned long clk_measure_input_freq(void)
167 {
168 u32 clock_autodetect;
169 clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
170 do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
171 clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
172 if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
173 return 12000000;
174 } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
175 return 13000000;
176 } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
177 return 19200000;
178 } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
179 return 26000000;
180 } else {
181 pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect);
182 BUG();
183 return 0;
184 }
185 }
186
187 static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
188 {
189 s64 divider_u71 = parent_rate * 2;
190 divider_u71 += rate - 1;
191 do_div(divider_u71, rate);
192
193 if (divider_u71 - 2 < 0)
194 return 0;
195
196 if (divider_u71 - 2 > 255)
197 return -EINVAL;
198
199 return divider_u71 - 2;
200 }
201
202 static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
203 {
204 s64 divider_u16;
205
206 divider_u16 = parent_rate;
207 divider_u16 += rate - 1;
208 do_div(divider_u16, rate);
209
210 if (divider_u16 - 1 < 0)
211 return 0;
212
213 if (divider_u16 - 1 > 255)
214 return -EINVAL;
215
216 return divider_u16 - 1;
217 }
218
219 /* clk_m functions */
220 static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
221 {
222 u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK;
223
224 c->rate = clk_measure_input_freq();
225 switch (c->rate) {
226 case 12000000:
227 auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
228 break;
229 case 13000000:
230 auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
231 break;
232 case 19200000:
233 auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
234 break;
235 case 26000000:
236 auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
237 break;
238 default:
239 pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
240 BUG();
241 }
242 clk_writel(auto_clock_control, OSC_CTRL);
243 return c->rate;
244 }
245
246 static void tegra2_clk_m_init(struct clk *c)
247 {
248 pr_debug("%s on clock %s\n", __func__, c->name);
249 tegra2_clk_m_autodetect_rate(c);
250 }
251
252 static int tegra2_clk_m_enable(struct clk *c)
253 {
254 pr_debug("%s on clock %s\n", __func__, c->name);
255 return 0;
256 }
257
258 static void tegra2_clk_m_disable(struct clk *c)
259 {
260 pr_debug("%s on clock %s\n", __func__, c->name);
261 BUG();
262 }
263
264 static struct clk_ops tegra_clk_m_ops = {
265 .init = tegra2_clk_m_init,
266 .enable = tegra2_clk_m_enable,
267 .disable = tegra2_clk_m_disable,
268 };
269
270 void tegra2_periph_reset_assert(struct clk *c)
271 {
272 BUG_ON(!c->ops->reset);
273 c->ops->reset(c, true);
274 }
275
276 void tegra2_periph_reset_deassert(struct clk *c)
277 {
278 BUG_ON(!c->ops->reset);
279 c->ops->reset(c, false);
280 }
281
282 /* super clock functions */
283 /* "super clocks" on tegra have two-stage muxes and a clock skipping
284 * super divider. We will ignore the clock skipping divider, since we
285 * can't lower the voltage when using the clock skip, but we can if we
286 * lower the PLL frequency.
287 */
288 static void tegra2_super_clk_init(struct clk *c)
289 {
290 u32 val;
291 int source;
292 int shift;
293 const struct clk_mux_sel *sel;
294 val = clk_readl(c->reg + SUPER_CLK_MUX);
295 c->state = ON;
296 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
297 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
298 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
299 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
300 source = (val >> shift) & SUPER_SOURCE_MASK;
301 for (sel = c->inputs; sel->input != NULL; sel++) {
302 if (sel->value == source)
303 break;
304 }
305 BUG_ON(sel->input == NULL);
306 c->parent = sel->input;
307 }
308
309 static int tegra2_super_clk_enable(struct clk *c)
310 {
311 clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
312 return 0;
313 }
314
315 static void tegra2_super_clk_disable(struct clk *c)
316 {
317 pr_debug("%s on clock %s\n", __func__, c->name);
318
319 /* oops - don't disable the CPU clock! */
320 BUG();
321 }
322
323 static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
324 {
325 u32 val;
326 const struct clk_mux_sel *sel;
327 int shift;
328
329 val = clk_readl(c->reg + SUPER_CLK_MUX);;
330 BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
331 ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
332 shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
333 SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
334 for (sel = c->inputs; sel->input != NULL; sel++) {
335 if (sel->input == p) {
336 val &= ~(SUPER_SOURCE_MASK << shift);
337 val |= sel->value << shift;
338
339 if (c->refcnt)
340 clk_enable(p);
341
342 clk_writel(val, c->reg);
343
344 if (c->refcnt && c->parent)
345 clk_disable(c->parent);
346
347 clk_reparent(c, p);
348 return 0;
349 }
350 }
351 return -EINVAL;
352 }
353
354 static struct clk_ops tegra_super_ops = {
355 .init = tegra2_super_clk_init,
356 .enable = tegra2_super_clk_enable,
357 .disable = tegra2_super_clk_disable,
358 .set_parent = tegra2_super_clk_set_parent,
359 };
360
361 /* virtual cpu clock functions */
362 /* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
363 To change the frequency of these clocks, the parent pll may need to be
364 reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
365 and then the clock moved back to the pll. To hide this sequence, a virtual
366 clock handles it.
367 */
368 static void tegra2_cpu_clk_init(struct clk *c)
369 {
370 }
371
372 static int tegra2_cpu_clk_enable(struct clk *c)
373 {
374 return 0;
375 }
376
377 static void tegra2_cpu_clk_disable(struct clk *c)
378 {
379 pr_debug("%s on clock %s\n", __func__, c->name);
380
381 /* oops - don't disable the CPU clock! */
382 BUG();
383 }
384
385 static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate)
386 {
387 int ret;
388 ret = clk_set_parent(c->parent, c->u.cpu.backup);
389 if (ret) {
390 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.backup->name);
391 return ret;
392 }
393
394 if (rate == clk_get_rate(c->u.cpu.backup))
395 goto out;
396
397 ret = clk_set_rate(c->u.cpu.main, rate);
398 if (ret) {
399 pr_err("Failed to change cpu pll to %lu\n", rate);
400 return ret;
401 }
402
403 ret = clk_set_parent(c->parent, c->u.cpu.main);
404 if (ret) {
405 pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.main->name);
406 return ret;
407 }
408
409 out:
410 return 0;
411 }
412
413 static struct clk_ops tegra_cpu_ops = {
414 .init = tegra2_cpu_clk_init,
415 .enable = tegra2_cpu_clk_enable,
416 .disable = tegra2_cpu_clk_disable,
417 .set_rate = tegra2_cpu_clk_set_rate,
418 };
419
420 /* bus clock functions */
421 static void tegra2_bus_clk_init(struct clk *c)
422 {
423 u32 val = clk_readl(c->reg);
424 c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
425 c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
426 c->mul = 1;
427 }
428
429 static int tegra2_bus_clk_enable(struct clk *c)
430 {
431 u32 val;
432 unsigned long flags;
433
434 spin_lock_irqsave(&clock_register_lock, flags);
435
436 val = clk_readl(c->reg);
437 val &= ~(BUS_CLK_DISABLE << c->reg_shift);
438 clk_writel(val, c->reg);
439
440 spin_unlock_irqrestore(&clock_register_lock, flags);
441
442 return 0;
443 }
444
445 static void tegra2_bus_clk_disable(struct clk *c)
446 {
447 u32 val;
448 unsigned long flags;
449
450 spin_lock_irqsave(&clock_register_lock, flags);
451
452 val = clk_readl(c->reg);
453 val |= BUS_CLK_DISABLE << c->reg_shift;
454 clk_writel(val, c->reg);
455
456 spin_unlock_irqrestore(&clock_register_lock, flags);
457 }
458
459 static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
460 {
461 u32 val;
462 unsigned long parent_rate = clk_get_rate(c->parent);
463 unsigned long flags;
464 int ret = -EINVAL;
465 int i;
466
467 spin_lock_irqsave(&clock_register_lock, flags);
468
469 val = clk_readl(c->reg);
470 for (i = 1; i <= 4; i++) {
471 if (rate == parent_rate / i) {
472 val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
473 val |= (i - 1) << c->reg_shift;
474 clk_writel(val, c->reg);
475 c->div = i;
476 c->mul = 1;
477 ret = 0;
478 break;
479 }
480 }
481
482 spin_unlock_irqrestore(&clock_register_lock, flags);
483
484 return ret;
485 }
486
487 static struct clk_ops tegra_bus_ops = {
488 .init = tegra2_bus_clk_init,
489 .enable = tegra2_bus_clk_enable,
490 .disable = tegra2_bus_clk_disable,
491 .set_rate = tegra2_bus_clk_set_rate,
492 };
493
494 /* Blink output functions */
495
496 static void tegra2_blink_clk_init(struct clk *c)
497 {
498 u32 val;
499
500 val = pmc_readl(PMC_CTRL);
501 c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
502 c->mul = 1;
503 val = pmc_readl(c->reg);
504
505 if (val & PMC_BLINK_TIMER_ENB) {
506 unsigned int on_off;
507
508 on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
509 PMC_BLINK_TIMER_DATA_ON_MASK;
510 val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
511 val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
512 on_off += val;
513 /* each tick in the blink timer is 4 32KHz clocks */
514 c->div = on_off * 4;
515 } else {
516 c->div = 1;
517 }
518 }
519
520 static int tegra2_blink_clk_enable(struct clk *c)
521 {
522 u32 val;
523
524 val = pmc_readl(PMC_DPD_PADS_ORIDE);
525 pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
526
527 val = pmc_readl(PMC_CTRL);
528 pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
529
530 return 0;
531 }
532
533 static void tegra2_blink_clk_disable(struct clk *c)
534 {
535 u32 val;
536
537 val = pmc_readl(PMC_CTRL);
538 pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
539
540 val = pmc_readl(PMC_DPD_PADS_ORIDE);
541 pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
542 }
543
544 static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate)
545 {
546 unsigned long parent_rate = clk_get_rate(c->parent);
547 if (rate >= parent_rate) {
548 c->div = 1;
549 pmc_writel(0, c->reg);
550 } else {
551 unsigned int on_off;
552 u32 val;
553
554 on_off = DIV_ROUND_UP(parent_rate / 8, rate);
555 c->div = on_off * 8;
556
557 val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
558 PMC_BLINK_TIMER_DATA_ON_SHIFT;
559 on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
560 on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
561 val |= on_off;
562 val |= PMC_BLINK_TIMER_ENB;
563 pmc_writel(val, c->reg);
564 }
565
566 return 0;
567 }
568
569 static struct clk_ops tegra_blink_clk_ops = {
570 .init = &tegra2_blink_clk_init,
571 .enable = &tegra2_blink_clk_enable,
572 .disable = &tegra2_blink_clk_disable,
573 .set_rate = &tegra2_blink_clk_set_rate,
574 };
575
576 /* PLL Functions */
577 static int tegra2_pll_clk_wait_for_lock(struct clk *c)
578 {
579 udelay(c->u.pll.lock_delay);
580
581 return 0;
582 }
583
584 static void tegra2_pll_clk_init(struct clk *c)
585 {
586 u32 val = clk_readl(c->reg + PLL_BASE);
587
588 c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
589
590 if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
591 pr_warning("Clock %s has unknown fixed frequency\n", c->name);
592 c->mul = 1;
593 c->div = 1;
594 } else if (val & PLL_BASE_BYPASS) {
595 c->mul = 1;
596 c->div = 1;
597 } else {
598 c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
599 c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
600 if (c->flags & PLLU)
601 c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
602 else
603 c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
604 }
605 }
606
607 static int tegra2_pll_clk_enable(struct clk *c)
608 {
609 u32 val;
610 pr_debug("%s on clock %s\n", __func__, c->name);
611
612 val = clk_readl(c->reg + PLL_BASE);
613 val &= ~PLL_BASE_BYPASS;
614 val |= PLL_BASE_ENABLE;
615 clk_writel(val, c->reg + PLL_BASE);
616
617 tegra2_pll_clk_wait_for_lock(c);
618
619 return 0;
620 }
621
622 static void tegra2_pll_clk_disable(struct clk *c)
623 {
624 u32 val;
625 pr_debug("%s on clock %s\n", __func__, c->name);
626
627 val = clk_readl(c->reg);
628 val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
629 clk_writel(val, c->reg);
630 }
631
632 static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
633 {
634 u32 val;
635 unsigned long input_rate;
636 const struct clk_pll_freq_table *sel;
637
638 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
639
640 input_rate = clk_get_rate(c->parent);
641 for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
642 if (sel->input_rate == input_rate && sel->output_rate == rate) {
643 c->mul = sel->n;
644 c->div = sel->m * sel->p;
645
646 val = clk_readl(c->reg + PLL_BASE);
647 if (c->flags & PLL_FIXED)
648 val |= PLL_BASE_OVERRIDE;
649 val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
650 PLL_BASE_DIVM_MASK);
651 val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
652 (sel->n << PLL_BASE_DIVN_SHIFT);
653 BUG_ON(sel->p < 1 || sel->p > 2);
654 if (c->flags & PLLU) {
655 if (sel->p == 1)
656 val |= PLLU_BASE_POST_DIV;
657 } else {
658 if (sel->p == 2)
659 val |= 1 << PLL_BASE_DIVP_SHIFT;
660 }
661 clk_writel(val, c->reg + PLL_BASE);
662
663 if (c->flags & PLL_HAS_CPCON) {
664 val = clk_readl(c->reg + PLL_MISC(c));
665 val &= ~PLL_MISC_CPCON_MASK;
666 val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
667 clk_writel(val, c->reg + PLL_MISC(c));
668 }
669
670 if (c->state == ON)
671 tegra2_pll_clk_enable(c);
672
673 return 0;
674 }
675 }
676 return -EINVAL;
677 }
678
679 static struct clk_ops tegra_pll_ops = {
680 .init = tegra2_pll_clk_init,
681 .enable = tegra2_pll_clk_enable,
682 .disable = tegra2_pll_clk_disable,
683 .set_rate = tegra2_pll_clk_set_rate,
684 };
685
686 static void tegra2_pllx_clk_init(struct clk *c)
687 {
688 tegra2_pll_clk_init(c);
689
690 if (tegra_sku_id() == 7)
691 c->max_rate = 750000000;
692 }
693
694 static struct clk_ops tegra_pllx_ops = {
695 .init = tegra2_pllx_clk_init,
696 .enable = tegra2_pll_clk_enable,
697 .disable = tegra2_pll_clk_disable,
698 .set_rate = tegra2_pll_clk_set_rate,
699 };
700
701 static int tegra2_plle_clk_enable(struct clk *c)
702 {
703 u32 val;
704
705 pr_debug("%s on clock %s\n", __func__, c->name);
706
707 mdelay(1);
708
709 val = clk_readl(c->reg + PLL_BASE);
710 if (!(val & PLLE_MISC_READY))
711 return -EBUSY;
712
713 val = clk_readl(c->reg + PLL_BASE);
714 val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
715 clk_writel(val, c->reg + PLL_BASE);
716
717 return 0;
718 }
719
720 static struct clk_ops tegra_plle_ops = {
721 .init = tegra2_pll_clk_init,
722 .enable = tegra2_plle_clk_enable,
723 .set_rate = tegra2_pll_clk_set_rate,
724 };
725
726 /* Clock divider ops */
727 static void tegra2_pll_div_clk_init(struct clk *c)
728 {
729 u32 val = clk_readl(c->reg);
730 u32 divu71;
731 val >>= c->reg_shift;
732 c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
733 if (!(val & PLL_OUT_RESET_DISABLE))
734 c->state = OFF;
735
736 if (c->flags & DIV_U71) {
737 divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
738 c->div = (divu71 + 2);
739 c->mul = 2;
740 } else if (c->flags & DIV_2) {
741 c->div = 2;
742 c->mul = 1;
743 } else {
744 c->div = 1;
745 c->mul = 1;
746 }
747 }
748
749 static int tegra2_pll_div_clk_enable(struct clk *c)
750 {
751 u32 val;
752 u32 new_val;
753 unsigned long flags;
754
755 pr_debug("%s: %s\n", __func__, c->name);
756 if (c->flags & DIV_U71) {
757 spin_lock_irqsave(&clock_register_lock, flags);
758 val = clk_readl(c->reg);
759 new_val = val >> c->reg_shift;
760 new_val &= 0xFFFF;
761
762 new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
763
764 val &= ~(0xFFFF << c->reg_shift);
765 val |= new_val << c->reg_shift;
766 clk_writel(val, c->reg);
767 spin_unlock_irqrestore(&clock_register_lock, flags);
768 return 0;
769 } else if (c->flags & DIV_2) {
770 BUG_ON(!(c->flags & PLLD));
771 spin_lock_irqsave(&clock_register_lock, flags);
772 val = clk_readl(c->reg);
773 val &= ~PLLD_MISC_DIV_RST;
774 clk_writel(val, c->reg);
775 spin_unlock_irqrestore(&clock_register_lock, flags);
776 return 0;
777 }
778 return -EINVAL;
779 }
780
781 static void tegra2_pll_div_clk_disable(struct clk *c)
782 {
783 u32 val;
784 u32 new_val;
785 unsigned long flags;
786
787 pr_debug("%s: %s\n", __func__, c->name);
788 if (c->flags & DIV_U71) {
789 spin_lock_irqsave(&clock_register_lock, flags);
790 val = clk_readl(c->reg);
791 new_val = val >> c->reg_shift;
792 new_val &= 0xFFFF;
793
794 new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
795
796 val &= ~(0xFFFF << c->reg_shift);
797 val |= new_val << c->reg_shift;
798 clk_writel(val, c->reg);
799 spin_unlock_irqrestore(&clock_register_lock, flags);
800 } else if (c->flags & DIV_2) {
801 BUG_ON(!(c->flags & PLLD));
802 spin_lock_irqsave(&clock_register_lock, flags);
803 val = clk_readl(c->reg);
804 val |= PLLD_MISC_DIV_RST;
805 clk_writel(val, c->reg);
806 spin_unlock_irqrestore(&clock_register_lock, flags);
807 }
808 }
809
810 static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
811 {
812 u32 val;
813 u32 new_val;
814 int divider_u71;
815 unsigned long parent_rate = clk_get_rate(c->parent);
816 unsigned long flags;
817
818 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
819 if (c->flags & DIV_U71) {
820 divider_u71 = clk_div71_get_divider(parent_rate, rate);
821 if (divider_u71 >= 0) {
822 spin_lock_irqsave(&clock_register_lock, flags);
823 val = clk_readl(c->reg);
824 new_val = val >> c->reg_shift;
825 new_val &= 0xFFFF;
826 if (c->flags & DIV_U71_FIXED)
827 new_val |= PLL_OUT_OVERRIDE;
828 new_val &= ~PLL_OUT_RATIO_MASK;
829 new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
830
831 val &= ~(0xFFFF << c->reg_shift);
832 val |= new_val << c->reg_shift;
833 clk_writel(val, c->reg);
834 c->div = divider_u71 + 2;
835 c->mul = 2;
836 spin_unlock_irqrestore(&clock_register_lock, flags);
837 return 0;
838 }
839 } else if (c->flags & DIV_2) {
840 if (parent_rate == rate * 2)
841 return 0;
842 }
843 return -EINVAL;
844 }
845
846 static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
847 {
848 int divider;
849 unsigned long parent_rate = clk_get_rate(c->parent);
850 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
851
852 if (c->flags & DIV_U71) {
853 divider = clk_div71_get_divider(parent_rate, rate);
854 if (divider < 0)
855 return divider;
856 return parent_rate * 2 / (divider + 2);
857 } else if (c->flags & DIV_2) {
858 return parent_rate / 2;
859 }
860 return -EINVAL;
861 }
862
863 static struct clk_ops tegra_pll_div_ops = {
864 .init = tegra2_pll_div_clk_init,
865 .enable = tegra2_pll_div_clk_enable,
866 .disable = tegra2_pll_div_clk_disable,
867 .set_rate = tegra2_pll_div_clk_set_rate,
868 .round_rate = tegra2_pll_div_clk_round_rate,
869 };
870
871 /* Periph clk ops */
872
873 static void tegra2_periph_clk_init(struct clk *c)
874 {
875 u32 val = clk_readl(c->reg);
876 const struct clk_mux_sel *mux = 0;
877 const struct clk_mux_sel *sel;
878 if (c->flags & MUX) {
879 for (sel = c->inputs; sel->input != NULL; sel++) {
880 if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value)
881 mux = sel;
882 }
883 BUG_ON(!mux);
884
885 c->parent = mux->input;
886 } else {
887 c->parent = c->inputs[0].input;
888 }
889
890 if (c->flags & DIV_U71) {
891 u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
892 c->div = divu71 + 2;
893 c->mul = 2;
894 } else if (c->flags & DIV_U16) {
895 u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
896 c->div = divu16 + 1;
897 c->mul = 1;
898 } else {
899 c->div = 1;
900 c->mul = 1;
901 }
902
903 c->state = ON;
904 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
905 PERIPH_CLK_TO_ENB_BIT(c)))
906 c->state = OFF;
907 if (!(c->flags & PERIPH_NO_RESET))
908 if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
909 PERIPH_CLK_TO_ENB_BIT(c))
910 c->state = OFF;
911 }
912
913 static int tegra2_periph_clk_enable(struct clk *c)
914 {
915 u32 val;
916 pr_debug("%s on clock %s\n", __func__, c->name);
917
918 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
919 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
920 if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
921 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
922 RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
923 if (c->flags & PERIPH_EMC_ENB) {
924 /* The EMC peripheral clock has 2 extra enable bits */
925 /* FIXME: Do they need to be disabled? */
926 val = clk_readl(c->reg);
927 val |= 0x3 << 24;
928 clk_writel(val, c->reg);
929 }
930 return 0;
931 }
932
933 static void tegra2_periph_clk_disable(struct clk *c)
934 {
935 pr_debug("%s on clock %s\n", __func__, c->name);
936
937 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
938 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
939 }
940
941 static void tegra2_periph_clk_reset(struct clk *c, bool assert)
942 {
943 unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
944
945 pr_debug("%s %s on clock %s\n", __func__,
946 assert ? "assert" : "deassert", c->name);
947 if (!(c->flags & PERIPH_NO_RESET))
948 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
949 base + PERIPH_CLK_TO_ENB_SET_REG(c));
950 }
951
952 static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
953 {
954 u32 val;
955 const struct clk_mux_sel *sel;
956 pr_debug("%s: %s %s\n", __func__, c->name, p->name);
957 for (sel = c->inputs; sel->input != NULL; sel++) {
958 if (sel->input == p) {
959 val = clk_readl(c->reg);
960 val &= ~PERIPH_CLK_SOURCE_MASK;
961 val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT;
962
963 if (c->refcnt)
964 clk_enable(p);
965
966 clk_writel(val, c->reg);
967
968 if (c->refcnt && c->parent)
969 clk_disable(c->parent);
970
971 clk_reparent(c, p);
972 return 0;
973 }
974 }
975
976 return -EINVAL;
977 }
978
979 static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
980 {
981 u32 val;
982 int divider;
983 unsigned long parent_rate = clk_get_rate(c->parent);
984
985 if (c->flags & DIV_U71) {
986 divider = clk_div71_get_divider(parent_rate, rate);
987 if (divider >= 0) {
988 val = clk_readl(c->reg);
989 val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
990 val |= divider;
991 clk_writel(val, c->reg);
992 c->div = divider + 2;
993 c->mul = 2;
994 return 0;
995 }
996 } else if (c->flags & DIV_U16) {
997 divider = clk_div16_get_divider(parent_rate, rate);
998 if (divider >= 0) {
999 val = clk_readl(c->reg);
1000 val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
1001 val |= divider;
1002 clk_writel(val, c->reg);
1003 c->div = divider + 1;
1004 c->mul = 1;
1005 return 0;
1006 }
1007 } else if (parent_rate <= rate) {
1008 c->div = 1;
1009 c->mul = 1;
1010 return 0;
1011 }
1012 return -EINVAL;
1013 }
1014
1015 static long tegra2_periph_clk_round_rate(struct clk *c,
1016 unsigned long rate)
1017 {
1018 int divider;
1019 unsigned long parent_rate = clk_get_rate(c->parent);
1020 pr_debug("%s: %s %lu\n", __func__, c->name, rate);
1021
1022 if (c->flags & DIV_U71) {
1023 divider = clk_div71_get_divider(parent_rate, rate);
1024 if (divider < 0)
1025 return divider;
1026
1027 return parent_rate * 2 / (divider + 2);
1028 } else if (c->flags & DIV_U16) {
1029 divider = clk_div16_get_divider(parent_rate, rate);
1030 if (divider < 0)
1031 return divider;
1032 return parent_rate / (divider + 1);
1033 }
1034 return -EINVAL;
1035 }
1036
1037 static struct clk_ops tegra_periph_clk_ops = {
1038 .init = &tegra2_periph_clk_init,
1039 .enable = &tegra2_periph_clk_enable,
1040 .disable = &tegra2_periph_clk_disable,
1041 .set_parent = &tegra2_periph_clk_set_parent,
1042 .set_rate = &tegra2_periph_clk_set_rate,
1043 .round_rate = &tegra2_periph_clk_round_rate,
1044 .reset = &tegra2_periph_clk_reset,
1045 };
1046
1047 /* Clock doubler ops */
1048 static void tegra2_clk_double_init(struct clk *c)
1049 {
1050 c->mul = 2;
1051 c->div = 1;
1052 c->state = ON;
1053 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1054 PERIPH_CLK_TO_ENB_BIT(c)))
1055 c->state = OFF;
1056 };
1057
1058 static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate)
1059 {
1060 if (rate != 2 * clk_get_rate(c->parent))
1061 return -EINVAL;
1062 c->mul = 2;
1063 c->div = 1;
1064 return 0;
1065 }
1066
1067 static struct clk_ops tegra_clk_double_ops = {
1068 .init = &tegra2_clk_double_init,
1069 .enable = &tegra2_periph_clk_enable,
1070 .disable = &tegra2_periph_clk_disable,
1071 .set_rate = &tegra2_clk_double_set_rate,
1072 };
1073
1074 /* Audio sync clock ops */
1075 static void tegra2_audio_sync_clk_init(struct clk *c)
1076 {
1077 int source;
1078 const struct clk_mux_sel *sel;
1079 u32 val = clk_readl(c->reg);
1080 c->state = (val & (1<<4)) ? OFF : ON;
1081 source = val & 0xf;
1082 for (sel = c->inputs; sel->input != NULL; sel++)
1083 if (sel->value == source)
1084 break;
1085 BUG_ON(sel->input == NULL);
1086 c->parent = sel->input;
1087 }
1088
1089 static int tegra2_audio_sync_clk_enable(struct clk *c)
1090 {
1091 clk_writel(0, c->reg);
1092 return 0;
1093 }
1094
1095 static void tegra2_audio_sync_clk_disable(struct clk *c)
1096 {
1097 clk_writel(1, c->reg);
1098 }
1099
1100 static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
1101 {
1102 u32 val;
1103 const struct clk_mux_sel *sel;
1104 for (sel = c->inputs; sel->input != NULL; sel++) {
1105 if (sel->input == p) {
1106 val = clk_readl(c->reg);
1107 val &= ~0xf;
1108 val |= sel->value;
1109
1110 if (c->refcnt)
1111 clk_enable(p);
1112
1113 clk_writel(val, c->reg);
1114
1115 if (c->refcnt && c->parent)
1116 clk_disable(c->parent);
1117
1118 clk_reparent(c, p);
1119 return 0;
1120 }
1121 }
1122
1123 return -EINVAL;
1124 }
1125
1126 static int tegra2_audio_sync_clk_set_rate(struct clk *c, unsigned long rate)
1127 {
1128 unsigned long parent_rate;
1129 if (!c->parent) {
1130 pr_err("%s: clock has no parent\n", __func__);
1131 return -EINVAL;
1132 }
1133 parent_rate = c->parent->rate;
1134 if (rate != parent_rate) {
1135 pr_err("%s: %s/%ld differs from parent %s/%ld\n",
1136 __func__,
1137 c->name, rate,
1138 c->parent->name, parent_rate);
1139 return -EINVAL;
1140 }
1141 c->rate = parent_rate;
1142 return 0;
1143 }
1144
1145 static struct clk_ops tegra_audio_sync_clk_ops = {
1146 .init = tegra2_audio_sync_clk_init,
1147 .enable = tegra2_audio_sync_clk_enable,
1148 .disable = tegra2_audio_sync_clk_disable,
1149 .set_rate = tegra2_audio_sync_clk_set_rate,
1150 .set_parent = tegra2_audio_sync_clk_set_parent,
1151 };
1152
1153 /* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
1154
1155 static void tegra2_cdev_clk_init(struct clk *c)
1156 {
1157 /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
1158 * currently done in the pinmux code. */
1159 c->state = ON;
1160 if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
1161 PERIPH_CLK_TO_ENB_BIT(c)))
1162 c->state = OFF;
1163 }
1164
1165 static int tegra2_cdev_clk_enable(struct clk *c)
1166 {
1167 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1168 CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
1169 return 0;
1170 }
1171
1172 static void tegra2_cdev_clk_disable(struct clk *c)
1173 {
1174 clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
1175 CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
1176 }
1177
1178 static struct clk_ops tegra_cdev_clk_ops = {
1179 .init = &tegra2_cdev_clk_init,
1180 .enable = &tegra2_cdev_clk_enable,
1181 .disable = &tegra2_cdev_clk_disable,
1182 };
1183
1184 /* Clock definitions */
1185 static struct clk tegra_clk_32k = {
1186 .name = "clk_32k",
1187 .rate = 32768,
1188 .ops = NULL,
1189 .max_rate = 32768,
1190 };
1191
1192 static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
1193 {32768, 12000000, 366, 1, 1, 0},
1194 {32768, 13000000, 397, 1, 1, 0},
1195 {32768, 19200000, 586, 1, 1, 0},
1196 {32768, 26000000, 793, 1, 1, 0},
1197 {0, 0, 0, 0, 0, 0},
1198 };
1199
1200 static struct clk tegra_pll_s = {
1201 .name = "pll_s",
1202 .flags = PLL_ALT_MISC_REG,
1203 .ops = &tegra_pll_ops,
1204 .parent = &tegra_clk_32k,
1205 .max_rate = 26000000,
1206 .reg = 0xf0,
1207 .u.pll = {
1208 .input_min = 32768,
1209 .input_max = 32768,
1210 .cf_min = 0, /* FIXME */
1211 .cf_max = 0, /* FIXME */
1212 .vco_min = 12000000,
1213 .vco_max = 26000000,
1214 .freq_table = tegra_pll_s_freq_table,
1215 .lock_delay = 300,
1216 },
1217 };
1218
1219 static struct clk_mux_sel tegra_clk_m_sel[] = {
1220 { .input = &tegra_clk_32k, .value = 0},
1221 { .input = &tegra_pll_s, .value = 1},
1222 { 0, 0},
1223 };
1224
1225 static struct clk tegra_clk_m = {
1226 .name = "clk_m",
1227 .flags = ENABLE_ON_INIT,
1228 .ops = &tegra_clk_m_ops,
1229 .inputs = tegra_clk_m_sel,
1230 .reg = 0x1fc,
1231 .reg_shift = 28,
1232 .max_rate = 26000000,
1233 };
1234
1235 static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
1236 { 0, 0, 0, 0, 0, 0 },
1237 };
1238
1239 static struct clk tegra_pll_c = {
1240 .name = "pll_c",
1241 .flags = PLL_HAS_CPCON,
1242 .ops = &tegra_pll_ops,
1243 .reg = 0x80,
1244 .parent = &tegra_clk_m,
1245 .max_rate = 600000000,
1246 .u.pll = {
1247 .input_min = 2000000,
1248 .input_max = 31000000,
1249 .cf_min = 1000000,
1250 .cf_max = 6000000,
1251 .vco_min = 20000000,
1252 .vco_max = 1400000000,
1253 .freq_table = tegra_pll_c_freq_table,
1254 .lock_delay = 300,
1255 },
1256 };
1257
1258 static struct clk tegra_pll_c_out1 = {
1259 .name = "pll_c_out1",
1260 .ops = &tegra_pll_div_ops,
1261 .flags = DIV_U71,
1262 .parent = &tegra_pll_c,
1263 .reg = 0x84,
1264 .reg_shift = 0,
1265 .max_rate = 600000000,
1266 };
1267
1268 static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
1269 { 12000000, 666000000, 666, 12, 1, 8},
1270 { 13000000, 666000000, 666, 13, 1, 8},
1271 { 19200000, 666000000, 555, 16, 1, 8},
1272 { 26000000, 666000000, 666, 26, 1, 8},
1273 { 12000000, 600000000, 600, 12, 1, 8},
1274 { 13000000, 600000000, 600, 13, 1, 8},
1275 { 19200000, 600000000, 375, 12, 1, 6},
1276 { 26000000, 600000000, 600, 26, 1, 8},
1277 { 0, 0, 0, 0, 0, 0 },
1278 };
1279
1280 static struct clk tegra_pll_m = {
1281 .name = "pll_m",
1282 .flags = PLL_HAS_CPCON,
1283 .ops = &tegra_pll_ops,
1284 .reg = 0x90,
1285 .parent = &tegra_clk_m,
1286 .max_rate = 800000000,
1287 .u.pll = {
1288 .input_min = 2000000,
1289 .input_max = 31000000,
1290 .cf_min = 1000000,
1291 .cf_max = 6000000,
1292 .vco_min = 20000000,
1293 .vco_max = 1200000000,
1294 .freq_table = tegra_pll_m_freq_table,
1295 .lock_delay = 300,
1296 },
1297 };
1298
1299 static struct clk tegra_pll_m_out1 = {
1300 .name = "pll_m_out1",
1301 .ops = &tegra_pll_div_ops,
1302 .flags = DIV_U71,
1303 .parent = &tegra_pll_m,
1304 .reg = 0x94,
1305 .reg_shift = 0,
1306 .max_rate = 600000000,
1307 };
1308
1309 static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
1310 { 12000000, 216000000, 432, 12, 2, 8},
1311 { 13000000, 216000000, 432, 13, 2, 8},
1312 { 19200000, 216000000, 90, 4, 2, 1},
1313 { 26000000, 216000000, 432, 26, 2, 8},
1314 { 12000000, 432000000, 432, 12, 1, 8},
1315 { 13000000, 432000000, 432, 13, 1, 8},
1316 { 19200000, 432000000, 90, 4, 1, 1},
1317 { 26000000, 432000000, 432, 26, 1, 8},
1318 { 0, 0, 0, 0, 0, 0 },
1319 };
1320
1321 static struct clk tegra_pll_p = {
1322 .name = "pll_p",
1323 .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
1324 .ops = &tegra_pll_ops,
1325 .reg = 0xa0,
1326 .parent = &tegra_clk_m,
1327 .max_rate = 432000000,
1328 .u.pll = {
1329 .input_min = 2000000,
1330 .input_max = 31000000,
1331 .cf_min = 1000000,
1332 .cf_max = 6000000,
1333 .vco_min = 20000000,
1334 .vco_max = 1400000000,
1335 .freq_table = tegra_pll_p_freq_table,
1336 .lock_delay = 300,
1337 },
1338 };
1339
1340 static struct clk tegra_pll_p_out1 = {
1341 .name = "pll_p_out1",
1342 .ops = &tegra_pll_div_ops,
1343 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1344 .parent = &tegra_pll_p,
1345 .reg = 0xa4,
1346 .reg_shift = 0,
1347 .max_rate = 432000000,
1348 };
1349
1350 static struct clk tegra_pll_p_out2 = {
1351 .name = "pll_p_out2",
1352 .ops = &tegra_pll_div_ops,
1353 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1354 .parent = &tegra_pll_p,
1355 .reg = 0xa4,
1356 .reg_shift = 16,
1357 .max_rate = 432000000,
1358 };
1359
1360 static struct clk tegra_pll_p_out3 = {
1361 .name = "pll_p_out3",
1362 .ops = &tegra_pll_div_ops,
1363 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1364 .parent = &tegra_pll_p,
1365 .reg = 0xa8,
1366 .reg_shift = 0,
1367 .max_rate = 432000000,
1368 };
1369
1370 static struct clk tegra_pll_p_out4 = {
1371 .name = "pll_p_out4",
1372 .ops = &tegra_pll_div_ops,
1373 .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
1374 .parent = &tegra_pll_p,
1375 .reg = 0xa8,
1376 .reg_shift = 16,
1377 .max_rate = 432000000,
1378 };
1379
1380 static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
1381 { 28800000, 56448000, 49, 25, 1, 1},
1382 { 28800000, 73728000, 64, 25, 1, 1},
1383 { 28800000, 11289600, 49, 25, 1, 1},
1384 { 28800000, 12288000, 64, 25, 1, 1},
1385 { 28800000, 24000000, 5, 6, 1, 1},
1386 { 0, 0, 0, 0, 0, 0 },
1387 };
1388
1389 static struct clk tegra_pll_a = {
1390 .name = "pll_a",
1391 .flags = PLL_HAS_CPCON,
1392 .ops = &tegra_pll_ops,
1393 .reg = 0xb0,
1394 .parent = &tegra_pll_p_out1,
1395 .max_rate = 56448000,
1396 .u.pll = {
1397 .input_min = 2000000,
1398 .input_max = 31000000,
1399 .cf_min = 1000000,
1400 .cf_max = 6000000,
1401 .vco_min = 20000000,
1402 .vco_max = 1400000000,
1403 .freq_table = tegra_pll_a_freq_table,
1404 .lock_delay = 300,
1405 },
1406 };
1407
1408 static struct clk tegra_pll_a_out0 = {
1409 .name = "pll_a_out0",
1410 .ops = &tegra_pll_div_ops,
1411 .flags = DIV_U71,
1412 .parent = &tegra_pll_a,
1413 .reg = 0xb4,
1414 .reg_shift = 0,
1415 .max_rate = 56448000,
1416 };
1417
1418 static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
1419 { 12000000, 216000000, 216, 12, 1, 4},
1420 { 13000000, 216000000, 216, 13, 1, 4},
1421 { 19200000, 216000000, 135, 12, 1, 3},
1422 { 26000000, 216000000, 216, 26, 1, 4},
1423
1424 { 12000000, 594000000, 594, 12, 1, 8},
1425 { 13000000, 594000000, 594, 13, 1, 8},
1426 { 19200000, 594000000, 495, 16, 1, 8},
1427 { 26000000, 594000000, 594, 26, 1, 8},
1428
1429 { 12000000, 1000000000, 1000, 12, 1, 12},
1430 { 13000000, 1000000000, 1000, 13, 1, 12},
1431 { 19200000, 1000000000, 625, 12, 1, 8},
1432 { 26000000, 1000000000, 1000, 26, 1, 12},
1433
1434 { 0, 0, 0, 0, 0, 0 },
1435 };
1436
1437 static struct clk tegra_pll_d = {
1438 .name = "pll_d",
1439 .flags = PLL_HAS_CPCON | PLLD,
1440 .ops = &tegra_pll_ops,
1441 .reg = 0xd0,
1442 .parent = &tegra_clk_m,
1443 .max_rate = 1000000000,
1444 .u.pll = {
1445 .input_min = 2000000,
1446 .input_max = 40000000,
1447 .cf_min = 1000000,
1448 .cf_max = 6000000,
1449 .vco_min = 40000000,
1450 .vco_max = 1000000000,
1451 .freq_table = tegra_pll_d_freq_table,
1452 .lock_delay = 1000,
1453 },
1454 };
1455
1456 static struct clk tegra_pll_d_out0 = {
1457 .name = "pll_d_out0",
1458 .ops = &tegra_pll_div_ops,
1459 .flags = DIV_2 | PLLD,
1460 .parent = &tegra_pll_d,
1461 .max_rate = 500000000,
1462 };
1463
1464 static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
1465 { 12000000, 480000000, 960, 12, 2, 0},
1466 { 13000000, 480000000, 960, 13, 2, 0},
1467 { 19200000, 480000000, 200, 4, 2, 0},
1468 { 26000000, 480000000, 960, 26, 2, 0},
1469 { 0, 0, 0, 0, 0, 0 },
1470 };
1471
1472 static struct clk tegra_pll_u = {
1473 .name = "pll_u",
1474 .flags = PLLU,
1475 .ops = &tegra_pll_ops,
1476 .reg = 0xc0,
1477 .parent = &tegra_clk_m,
1478 .max_rate = 480000000,
1479 .u.pll = {
1480 .input_min = 2000000,
1481 .input_max = 40000000,
1482 .cf_min = 1000000,
1483 .cf_max = 6000000,
1484 .vco_min = 480000000,
1485 .vco_max = 960000000,
1486 .freq_table = tegra_pll_u_freq_table,
1487 .lock_delay = 1000,
1488 },
1489 };
1490
1491 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
1492 /* 1 GHz */
1493 { 12000000, 1000000000, 1000, 12, 1, 12},
1494 { 13000000, 1000000000, 1000, 13, 1, 12},
1495 { 19200000, 1000000000, 625, 12, 1, 8},
1496 { 26000000, 1000000000, 1000, 26, 1, 12},
1497
1498 /* 912 MHz */
1499 { 12000000, 912000000, 912, 12, 1, 12},
1500 { 13000000, 912000000, 912, 13, 1, 12},
1501 { 19200000, 912000000, 760, 16, 1, 8},
1502 { 26000000, 912000000, 912, 26, 1, 12},
1503
1504 /* 816 MHz */
1505 { 12000000, 816000000, 816, 12, 1, 12},
1506 { 13000000, 816000000, 816, 13, 1, 12},
1507 { 19200000, 816000000, 680, 16, 1, 8},
1508 { 26000000, 816000000, 816, 26, 1, 12},
1509
1510 /* 760 MHz */
1511 { 12000000, 760000000, 760, 12, 1, 12},
1512 { 13000000, 760000000, 760, 13, 1, 12},
1513 { 19200000, 760000000, 950, 24, 1, 8},
1514 { 26000000, 760000000, 760, 26, 1, 12},
1515
1516 /* 608 MHz */
1517 { 12000000, 608000000, 760, 12, 1, 12},
1518 { 13000000, 608000000, 760, 13, 1, 12},
1519 { 19200000, 608000000, 380, 12, 1, 8},
1520 { 26000000, 608000000, 760, 26, 1, 12},
1521
1522 /* 456 MHz */
1523 { 12000000, 456000000, 456, 12, 1, 12},
1524 { 13000000, 456000000, 456, 13, 1, 12},
1525 { 19200000, 456000000, 380, 16, 1, 8},
1526 { 26000000, 456000000, 456, 26, 1, 12},
1527
1528 /* 312 MHz */
1529 { 12000000, 312000000, 312, 12, 1, 12},
1530 { 13000000, 312000000, 312, 13, 1, 12},
1531 { 19200000, 312000000, 260, 16, 1, 8},
1532 { 26000000, 312000000, 312, 26, 1, 12},
1533
1534 { 0, 0, 0, 0, 0, 0 },
1535 };
1536
1537 static struct clk tegra_pll_x = {
1538 .name = "pll_x",
1539 .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
1540 .ops = &tegra_pllx_ops,
1541 .reg = 0xe0,
1542 .parent = &tegra_clk_m,
1543 .max_rate = 1000000000,
1544 .u.pll = {
1545 .input_min = 2000000,
1546 .input_max = 31000000,
1547 .cf_min = 1000000,
1548 .cf_max = 6000000,
1549 .vco_min = 20000000,
1550 .vco_max = 1200000000,
1551 .freq_table = tegra_pll_x_freq_table,
1552 .lock_delay = 300,
1553 },
1554 };
1555
1556 static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
1557 { 12000000, 100000000, 200, 24, 1, 0 },
1558 { 0, 0, 0, 0, 0, 0 },
1559 };
1560
1561 static struct clk tegra_pll_e = {
1562 .name = "pll_e",
1563 .flags = PLL_ALT_MISC_REG,
1564 .ops = &tegra_plle_ops,
1565 .parent = &tegra_clk_m,
1566 .reg = 0xe8,
1567 .max_rate = 100000000,
1568 .u.pll = {
1569 .input_min = 12000000,
1570 .input_max = 12000000,
1571 .freq_table = tegra_pll_e_freq_table,
1572 },
1573 };
1574
1575 static struct clk tegra_clk_d = {
1576 .name = "clk_d",
1577 .flags = PERIPH_NO_RESET,
1578 .ops = &tegra_clk_double_ops,
1579 .reg = 0x34,
1580 .reg_shift = 12,
1581 .parent = &tegra_clk_m,
1582 .max_rate = 52000000,
1583 .u.periph = {
1584 .clk_num = 90,
1585 },
1586 };
1587
1588 /* dap_mclk1, belongs to the cdev1 pingroup. */
1589 static struct clk tegra_dev1_clk = {
1590 .name = "clk_dev1",
1591 .ops = &tegra_cdev_clk_ops,
1592 .rate = 26000000,
1593 .max_rate = 26000000,
1594 .u.periph = {
1595 .clk_num = 94,
1596 },
1597 };
1598
1599 /* dap_mclk2, belongs to the cdev2 pingroup. */
1600 static struct clk tegra_dev2_clk = {
1601 .name = "clk_dev2",
1602 .ops = &tegra_cdev_clk_ops,
1603 .rate = 26000000,
1604 .max_rate = 26000000,
1605 .u.periph = {
1606 .clk_num = 93,
1607 },
1608 };
1609
1610 /* initialized before peripheral clocks */
1611 static struct clk_mux_sel mux_audio_sync_clk[8+1];
1612 static const struct audio_sources {
1613 const char *name;
1614 int value;
1615 } mux_audio_sync_clk_sources[] = {
1616 { .name = "spdif_in", .value = 0 },
1617 { .name = "i2s1", .value = 1 },
1618 { .name = "i2s2", .value = 2 },
1619 { .name = "pll_a_out0", .value = 4 },
1620 #if 0 /* FIXME: not implemented */
1621 { .name = "ac97", .value = 3 },
1622 { .name = "ext_audio_clk2", .value = 5 },
1623 { .name = "ext_audio_clk1", .value = 6 },
1624 { .name = "ext_vimclk", .value = 7 },
1625 #endif
1626 { 0, 0 }
1627 };
1628
1629 static struct clk tegra_clk_audio = {
1630 .name = "audio",
1631 .inputs = mux_audio_sync_clk,
1632 .reg = 0x38,
1633 .max_rate = 24000000,
1634 .ops = &tegra_audio_sync_clk_ops
1635 };
1636
1637 static struct clk tegra_clk_audio_2x = {
1638 .name = "audio_2x",
1639 .flags = PERIPH_NO_RESET,
1640 .max_rate = 48000000,
1641 .ops = &tegra_clk_double_ops,
1642 .reg = 0x34,
1643 .reg_shift = 8,
1644 .parent = &tegra_clk_audio,
1645 .u.periph = {
1646 .clk_num = 89,
1647 },
1648 };
1649
1650 struct clk_lookup tegra_audio_clk_lookups[] = {
1651 { .con_id = "audio", .clk = &tegra_clk_audio },
1652 { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
1653 };
1654
1655 /* This is called after peripheral clocks are initialized, as the
1656 * audio_sync clock depends on some of the peripheral clocks.
1657 */
1658
1659 static void init_audio_sync_clock_mux(void)
1660 {
1661 int i;
1662 struct clk_mux_sel *sel = mux_audio_sync_clk;
1663 const struct audio_sources *src = mux_audio_sync_clk_sources;
1664 struct clk_lookup *lookup;
1665
1666 for (i = 0; src->name; i++, sel++, src++) {
1667 sel->input = tegra_get_clock_by_name(src->name);
1668 if (!sel->input)
1669 pr_err("%s: could not find clk %s\n", __func__,
1670 src->name);
1671 sel->value = src->value;
1672 }
1673
1674 lookup = tegra_audio_clk_lookups;
1675 for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
1676 clk_init(lookup->clk);
1677 clkdev_add(lookup);
1678 }
1679 }
1680
1681 static struct clk_mux_sel mux_cclk[] = {
1682 { .input = &tegra_clk_m, .value = 0},
1683 { .input = &tegra_pll_c, .value = 1},
1684 { .input = &tegra_clk_32k, .value = 2},
1685 { .input = &tegra_pll_m, .value = 3},
1686 { .input = &tegra_pll_p, .value = 4},
1687 { .input = &tegra_pll_p_out4, .value = 5},
1688 { .input = &tegra_pll_p_out3, .value = 6},
1689 { .input = &tegra_clk_d, .value = 7},
1690 { .input = &tegra_pll_x, .value = 8},
1691 { 0, 0},
1692 };
1693
1694 static struct clk_mux_sel mux_sclk[] = {
1695 { .input = &tegra_clk_m, .value = 0},
1696 { .input = &tegra_pll_c_out1, .value = 1},
1697 { .input = &tegra_pll_p_out4, .value = 2},
1698 { .input = &tegra_pll_p_out3, .value = 3},
1699 { .input = &tegra_pll_p_out2, .value = 4},
1700 { .input = &tegra_clk_d, .value = 5},
1701 { .input = &tegra_clk_32k, .value = 6},
1702 { .input = &tegra_pll_m_out1, .value = 7},
1703 { 0, 0},
1704 };
1705
1706 static struct clk tegra_clk_cclk = {
1707 .name = "cclk",
1708 .inputs = mux_cclk,
1709 .reg = 0x20,
1710 .ops = &tegra_super_ops,
1711 .max_rate = 1000000000,
1712 };
1713
1714 static struct clk tegra_clk_sclk = {
1715 .name = "sclk",
1716 .inputs = mux_sclk,
1717 .reg = 0x28,
1718 .ops = &tegra_super_ops,
1719 .max_rate = 600000000,
1720 };
1721
1722 static struct clk tegra_clk_virtual_cpu = {
1723 .name = "cpu",
1724 .parent = &tegra_clk_cclk,
1725 .ops = &tegra_cpu_ops,
1726 .max_rate = 1000000000,
1727 .u.cpu = {
1728 .main = &tegra_pll_x,
1729 .backup = &tegra_pll_p,
1730 },
1731 };
1732
1733 static struct clk tegra_clk_hclk = {
1734 .name = "hclk",
1735 .flags = DIV_BUS,
1736 .parent = &tegra_clk_sclk,
1737 .reg = 0x30,
1738 .reg_shift = 4,
1739 .ops = &tegra_bus_ops,
1740 .max_rate = 240000000,
1741 };
1742
1743 static struct clk tegra_clk_pclk = {
1744 .name = "pclk",
1745 .flags = DIV_BUS,
1746 .parent = &tegra_clk_hclk,
1747 .reg = 0x30,
1748 .reg_shift = 0,
1749 .ops = &tegra_bus_ops,
1750 .max_rate = 108000000,
1751 };
1752
1753 static struct clk tegra_clk_blink = {
1754 .name = "blink",
1755 .parent = &tegra_clk_32k,
1756 .reg = 0x40,
1757 .ops = &tegra_blink_clk_ops,
1758 .max_rate = 32768,
1759 };
1760
1761 static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
1762 { .input = &tegra_pll_m, .value = 0},
1763 { .input = &tegra_pll_c, .value = 1},
1764 { .input = &tegra_pll_p, .value = 2},
1765 { .input = &tegra_pll_a_out0, .value = 3},
1766 { 0, 0},
1767 };
1768
1769 static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
1770 { .input = &tegra_pll_m, .value = 0},
1771 { .input = &tegra_pll_c, .value = 1},
1772 { .input = &tegra_pll_p, .value = 2},
1773 { .input = &tegra_clk_m, .value = 3},
1774 { 0, 0},
1775 };
1776
1777 static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
1778 { .input = &tegra_pll_p, .value = 0},
1779 { .input = &tegra_pll_c, .value = 1},
1780 { .input = &tegra_pll_m, .value = 2},
1781 { .input = &tegra_clk_m, .value = 3},
1782 { 0, 0},
1783 };
1784
1785 static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
1786 {.input = &tegra_pll_a_out0, .value = 0},
1787 {.input = &tegra_clk_audio_2x, .value = 1},
1788 {.input = &tegra_pll_p, .value = 2},
1789 {.input = &tegra_clk_m, .value = 3},
1790 { 0, 0},
1791 };
1792
1793 static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
1794 {.input = &tegra_pll_p, .value = 0},
1795 {.input = &tegra_pll_d_out0, .value = 1},
1796 {.input = &tegra_pll_c, .value = 2},
1797 {.input = &tegra_clk_m, .value = 3},
1798 { 0, 0},
1799 };
1800
1801 static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
1802 {.input = &tegra_pll_p, .value = 0},
1803 {.input = &tegra_pll_c, .value = 1},
1804 {.input = &tegra_clk_audio, .value = 2},
1805 {.input = &tegra_clk_m, .value = 3},
1806 {.input = &tegra_clk_32k, .value = 4},
1807 { 0, 0},
1808 };
1809
1810 static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
1811 {.input = &tegra_pll_p, .value = 0},
1812 {.input = &tegra_pll_c, .value = 1},
1813 {.input = &tegra_pll_m, .value = 2},
1814 { 0, 0},
1815 };
1816
1817 static struct clk_mux_sel mux_clk_m[] = {
1818 { .input = &tegra_clk_m, .value = 0},
1819 { 0, 0},
1820 };
1821
1822 static struct clk_mux_sel mux_pllp_out3[] = {
1823 { .input = &tegra_pll_p_out3, .value = 0},
1824 { 0, 0},
1825 };
1826
1827 static struct clk_mux_sel mux_plld[] = {
1828 { .input = &tegra_pll_d, .value = 0},
1829 { 0, 0},
1830 };
1831
1832 static struct clk_mux_sel mux_clk_32k[] = {
1833 { .input = &tegra_clk_32k, .value = 0},
1834 { 0, 0},
1835 };
1836
1837 static struct clk_mux_sel mux_pclk[] = {
1838 { .input = &tegra_clk_pclk, .value = 0},
1839 { 0, 0},
1840 };
1841
1842 #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
1843 { \
1844 .name = _name, \
1845 .lookup = { \
1846 .dev_id = _dev, \
1847 .con_id = _con, \
1848 }, \
1849 .ops = &tegra_periph_clk_ops, \
1850 .reg = _reg, \
1851 .inputs = _inputs, \
1852 .flags = _flags, \
1853 .max_rate = _max, \
1854 .u.periph = { \
1855 .clk_num = _clk_num, \
1856 }, \
1857 }
1858
1859 struct clk tegra_list_clks[] = {
1860 PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 108000000, mux_pclk, 0),
1861 PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET),
1862 PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
1863 PERIPH_CLK("i2s1", "i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
1864 PERIPH_CLK("i2s2", "i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
1865 /* FIXME: spdif has 2 clocks but 1 enable */
1866 PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
1867 PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71),
1868 PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71),
1869 PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1870 PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1871 PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1872 PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1873 PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1874 PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1875 PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1876 PERIPH_CLK("ide", "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
1877 PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1878 /* FIXME: vfir shares an enable with uartb */
1879 PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1880 PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1881 PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1882 PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1883 PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1884 PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
1885 PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
1886 /* FIXME: what is la? */
1887 PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1888 PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
1889 PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
1890 PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
1891 PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
1892 PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
1893 PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
1894 PERIPH_CLK("dvc", "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
1895 PERIPH_CLK("i2c1_i2c", "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
1896 PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
1897 PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
1898 PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
1899 PERIPH_CLK("uarta", "uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
1900 PERIPH_CLK("uartb", "uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
1901 PERIPH_CLK("uartc", "uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
1902 PERIPH_CLK("uartd", "uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
1903 PERIPH_CLK("uarte", "uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
1904 PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
1905 PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1906 /* FIXME: vi and vi_sensor share an enable */
1907 PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1908 PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
1909 PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1910 PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1911 PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
1912 /* FIXME: cve and tvo share an enable */
1913 PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
1914 PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
1915 PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
1916 PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
1917 PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
1918 PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
1919 PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
1920 PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
1921 PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
1922 PERIPH_CLK("emc", "emc", NULL, 57, 0x19c, 800000000, mux_pllm_pllc_pllp_clkm, MUX | DIV_U71 | PERIPH_EMC_ENB),
1923 PERIPH_CLK("dsi", "dsi", NULL, 48, 0, 500000000, mux_plld, 0), /* scales with voltage */
1924 PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0),
1925 PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
1926 PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
1927 PERIPH_CLK("pex", NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
1928 PERIPH_CLK("afi", NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
1929 PERIPH_CLK("pcie_xclk", NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
1930 };
1931
1932 #define CLK_DUPLICATE(_name, _dev, _con) \
1933 { \
1934 .name = _name, \
1935 .lookup = { \
1936 .dev_id = _dev, \
1937 .con_id = _con, \
1938 }, \
1939 }
1940
1941 /* Some clocks may be used by different drivers depending on the board
1942 * configuration. List those here to register them twice in the clock lookup
1943 * table under two names.
1944 */
1945 struct clk_duplicate tegra_clk_duplicates[] = {
1946 CLK_DUPLICATE("uarta", "tegra_uart.0", NULL),
1947 CLK_DUPLICATE("uartb", "tegra_uart.1", NULL),
1948 CLK_DUPLICATE("uartc", "tegra_uart.2", NULL),
1949 CLK_DUPLICATE("uartd", "tegra_uart.3", NULL),
1950 CLK_DUPLICATE("uarte", "tegra_uart.4", NULL),
1951 CLK_DUPLICATE("usbd", "utmip-pad", NULL),
1952 CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
1953 CLK_DUPLICATE("usbd", "tegra-otg", NULL),
1954 CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
1955 CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
1956 CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL),
1957 CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL),
1958 CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL),
1959 CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL),
1960 };
1961
1962 #define CLK(dev, con, ck) \
1963 { \
1964 .dev_id = dev, \
1965 .con_id = con, \
1966 .clk = ck, \
1967 }
1968
1969 struct clk *tegra_ptr_clks[] = {
1970 &tegra_clk_32k,
1971 &tegra_pll_s,
1972 &tegra_clk_m,
1973 &tegra_pll_m,
1974 &tegra_pll_m_out1,
1975 &tegra_pll_c,
1976 &tegra_pll_c_out1,
1977 &tegra_pll_p,
1978 &tegra_pll_p_out1,
1979 &tegra_pll_p_out2,
1980 &tegra_pll_p_out3,
1981 &tegra_pll_p_out4,
1982 &tegra_pll_a,
1983 &tegra_pll_a_out0,
1984 &tegra_pll_d,
1985 &tegra_pll_d_out0,
1986 &tegra_pll_u,
1987 &tegra_pll_x,
1988 &tegra_pll_e,
1989 &tegra_clk_cclk,
1990 &tegra_clk_sclk,
1991 &tegra_clk_hclk,
1992 &tegra_clk_pclk,
1993 &tegra_clk_d,
1994 &tegra_dev1_clk,
1995 &tegra_dev2_clk,
1996 &tegra_clk_virtual_cpu,
1997 &tegra_clk_blink,
1998 };
1999
2000 static void tegra2_init_one_clock(struct clk *c)
2001 {
2002 clk_init(c);
2003 if (!c->lookup.dev_id && !c->lookup.con_id)
2004 c->lookup.con_id = c->name;
2005 c->lookup.clk = c;
2006 clkdev_add(&c->lookup);
2007 }
2008
2009 void __init tegra2_init_clocks(void)
2010 {
2011 int i;
2012 struct clk *c;
2013
2014 for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
2015 tegra2_init_one_clock(tegra_ptr_clks[i]);
2016
2017 for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
2018 tegra2_init_one_clock(&tegra_list_clks[i]);
2019
2020 for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
2021 c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
2022 if (!c) {
2023 pr_err("%s: Unknown duplicate clock %s\n", __func__,
2024 tegra_clk_duplicates[i].name);
2025 continue;
2026 }
2027
2028 tegra_clk_duplicates[i].lookup.clk = c;
2029 clkdev_add(&tegra_clk_duplicates[i].lookup);
2030 }
2031
2032 init_audio_sync_clock_mux();
2033 }
2034
2035 #ifdef CONFIG_PM
2036 static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
2037 PERIPH_CLK_SOURCE_NUM + 19];
2038
2039 void tegra_clk_suspend(void)
2040 {
2041 unsigned long off, i;
2042 u32 *ctx = clk_rst_suspend;
2043
2044 *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
2045 *ctx++ = clk_readl(tegra_pll_p.reg + PLL_BASE);
2046 *ctx++ = clk_readl(tegra_pll_p.reg + PLL_MISC(&tegra_pll_p));
2047 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE);
2048 *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2049 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
2050 *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2051
2052 *ctx++ = clk_readl(tegra_pll_m_out1.reg);
2053 *ctx++ = clk_readl(tegra_pll_p_out1.reg);
2054 *ctx++ = clk_readl(tegra_pll_p_out3.reg);
2055 *ctx++ = clk_readl(tegra_pll_a_out0.reg);
2056 *ctx++ = clk_readl(tegra_pll_c_out1.reg);
2057
2058 *ctx++ = clk_readl(tegra_clk_cclk.reg);
2059 *ctx++ = clk_readl(tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2060
2061 *ctx++ = clk_readl(tegra_clk_sclk.reg);
2062 *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2063 *ctx++ = clk_readl(tegra_clk_pclk.reg);
2064
2065 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2066 off += 4) {
2067 if (off == PERIPH_CLK_SOURCE_EMC)
2068 continue;
2069 *ctx++ = clk_readl(off);
2070 }
2071
2072 off = RST_DEVICES;
2073 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2074 *ctx++ = clk_readl(off);
2075
2076 off = CLK_OUT_ENB;
2077 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2078 *ctx++ = clk_readl(off);
2079
2080 *ctx++ = clk_readl(MISC_CLK_ENB);
2081 *ctx++ = clk_readl(CLK_MASK_ARM);
2082 }
2083
2084 void tegra_clk_resume(void)
2085 {
2086 unsigned long off, i;
2087 const u32 *ctx = clk_rst_suspend;
2088 u32 val;
2089
2090 val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
2091 val |= *ctx++;
2092 clk_writel(val, OSC_CTRL);
2093
2094 clk_writel(*ctx++, tegra_pll_p.reg + PLL_BASE);
2095 clk_writel(*ctx++, tegra_pll_p.reg + PLL_MISC(&tegra_pll_p));
2096 clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE);
2097 clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
2098 clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE);
2099 clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
2100 udelay(300);
2101
2102 clk_writel(*ctx++, tegra_pll_m_out1.reg);
2103 clk_writel(*ctx++, tegra_pll_p_out1.reg);
2104 clk_writel(*ctx++, tegra_pll_p_out3.reg);
2105 clk_writel(*ctx++, tegra_pll_a_out0.reg);
2106 clk_writel(*ctx++, tegra_pll_c_out1.reg);
2107
2108 clk_writel(*ctx++, tegra_clk_cclk.reg);
2109 clk_writel(*ctx++, tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
2110
2111 clk_writel(*ctx++, tegra_clk_sclk.reg);
2112 clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
2113 clk_writel(*ctx++, tegra_clk_pclk.reg);
2114
2115 /* enable all clocks before configuring clock sources */
2116 clk_writel(0xbffffff9ul, CLK_OUT_ENB);
2117 clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4);
2118 clk_writel(0x77f01bfful, CLK_OUT_ENB + 8);
2119 wmb();
2120
2121 for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
2122 off += 4) {
2123 if (off == PERIPH_CLK_SOURCE_EMC)
2124 continue;
2125 clk_writel(*ctx++, off);
2126 }
2127 wmb();
2128
2129 off = RST_DEVICES;
2130 for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
2131 clk_writel(*ctx++, off);
2132 wmb();
2133
2134 off = CLK_OUT_ENB;
2135 for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
2136 clk_writel(*ctx++, off);
2137 wmb();
2138
2139 clk_writel(*ctx++, MISC_CLK_ENB);
2140 clk_writel(*ctx++, CLK_MASK_ARM);
2141 }
2142 #endif
Linux kernel - Deliverables
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