2 * arch/arch/mach-tegra/timer.c
4 * Copyright (C) 2010 Google, Inc.
7 * Colin Cross <ccross@google.com>
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/init.h>
21 #include <linux/err.h>
22 #include <linux/time.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/clockchips.h>
26 #include <linux/clocksource.h>
27 #include <linux/clk.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
32 #include <asm/mach/time.h>
33 #include <asm/smp_twd.h>
34 #include <asm/sched_clock.h>
38 #define RTC_SECONDS 0x08
39 #define RTC_SHADOW_SECONDS 0x0c
40 #define RTC_MILLISECONDS 0x10
42 #define TIMERUS_CNTR_1US 0x10
43 #define TIMERUS_USEC_CFG 0x14
44 #define TIMERUS_CNTR_FREEZE 0x4c
46 #define TIMER1_BASE 0x0
47 #define TIMER2_BASE 0x8
48 #define TIMER3_BASE 0x50
49 #define TIMER4_BASE 0x58
54 static void __iomem
*timer_reg_base
;
55 static void __iomem
*rtc_base
;
57 static struct timespec persistent_ts
;
58 static u64 persistent_ms
, last_persistent_ms
;
60 #define timer_writel(value, reg) \
61 __raw_writel(value, timer_reg_base + (reg))
62 #define timer_readl(reg) \
63 __raw_readl(timer_reg_base + (reg))
65 static int tegra_timer_set_next_event(unsigned long cycles
,
66 struct clock_event_device
*evt
)
70 reg
= 0x80000000 | ((cycles
> 1) ? (cycles
-1) : 0);
71 timer_writel(reg
, TIMER3_BASE
+ TIMER_PTV
);
76 static void tegra_timer_set_mode(enum clock_event_mode mode
,
77 struct clock_event_device
*evt
)
81 timer_writel(0, TIMER3_BASE
+ TIMER_PTV
);
84 case CLOCK_EVT_MODE_PERIODIC
:
85 reg
= 0xC0000000 | ((1000000/HZ
)-1);
86 timer_writel(reg
, TIMER3_BASE
+ TIMER_PTV
);
88 case CLOCK_EVT_MODE_ONESHOT
:
90 case CLOCK_EVT_MODE_UNUSED
:
91 case CLOCK_EVT_MODE_SHUTDOWN
:
92 case CLOCK_EVT_MODE_RESUME
:
97 static struct clock_event_device tegra_clockevent
= {
100 .features
= CLOCK_EVT_FEAT_ONESHOT
| CLOCK_EVT_FEAT_PERIODIC
,
101 .set_next_event
= tegra_timer_set_next_event
,
102 .set_mode
= tegra_timer_set_mode
,
105 static u32 notrace
tegra_read_sched_clock(void)
107 return timer_readl(TIMERUS_CNTR_1US
);
111 * tegra_rtc_read - Reads the Tegra RTC registers
112 * Care must be taken that this funciton is not called while the
113 * tegra_rtc driver could be executing to avoid race conditions
114 * on the RTC shadow register
116 static u64
tegra_rtc_read_ms(void)
118 u32 ms
= readl(rtc_base
+ RTC_MILLISECONDS
);
119 u32 s
= readl(rtc_base
+ RTC_SHADOW_SECONDS
);
120 return (u64
)s
* MSEC_PER_SEC
+ ms
;
124 * tegra_read_persistent_clock - Return time from a persistent clock.
126 * Reads the time from a source which isn't disabled during PM, the
127 * 32k sync timer. Convert the cycles elapsed since last read into
128 * nsecs and adds to a monotonically increasing timespec.
129 * Care must be taken that this funciton is not called while the
130 * tegra_rtc driver could be executing to avoid race conditions
131 * on the RTC shadow register
133 static void tegra_read_persistent_clock(struct timespec
*ts
)
136 struct timespec
*tsp
= &persistent_ts
;
138 last_persistent_ms
= persistent_ms
;
139 persistent_ms
= tegra_rtc_read_ms();
140 delta
= persistent_ms
- last_persistent_ms
;
142 timespec_add_ns(tsp
, delta
* NSEC_PER_MSEC
);
146 static irqreturn_t
tegra_timer_interrupt(int irq
, void *dev_id
)
148 struct clock_event_device
*evt
= (struct clock_event_device
*)dev_id
;
149 timer_writel(1<<30, TIMER3_BASE
+ TIMER_PCR
);
150 evt
->event_handler(evt
);
154 static struct irqaction tegra_timer_irq
= {
156 .flags
= IRQF_DISABLED
| IRQF_TIMER
| IRQF_TRIGGER_HIGH
,
157 .handler
= tegra_timer_interrupt
,
158 .dev_id
= &tegra_clockevent
,
161 static const struct of_device_id timer_match
[] __initconst
= {
162 { .compatible
= "nvidia,tegra20-timer" },
166 static const struct of_device_id rtc_match
[] __initconst
= {
167 { .compatible
= "nvidia,tegra20-rtc" },
171 void __init
tegra_init_timer(void)
173 struct device_node
*np
;
178 np
= of_find_matching_node(NULL
, timer_match
);
180 pr_err("Failed to find timer DT node\n");
184 timer_reg_base
= of_iomap(np
, 0);
185 if (!timer_reg_base
) {
186 pr_err("Can't map timer registers");
190 tegra_timer_irq
.irq
= irq_of_parse_and_map(np
, 2);
191 if (tegra_timer_irq
.irq
<= 0) {
192 pr_err("Failed to map timer IRQ\n");
196 clk
= clk_get_sys("timer", NULL
);
198 pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
201 clk_prepare_enable(clk
);
202 rate
= clk_get_rate(clk
);
207 np
= of_find_matching_node(NULL
, rtc_match
);
209 pr_err("Failed to find RTC DT node\n");
213 rtc_base
= of_iomap(np
, 0);
215 pr_err("Can't map RTC registers");
220 * rtc registers are used by read_persistent_clock, keep the rtc clock
223 clk
= clk_get_sys("rtc-tegra", NULL
);
225 pr_warn("Unable to get rtc-tegra clock\n");
227 clk_prepare_enable(clk
);
233 timer_writel(0x000b, TIMERUS_USEC_CFG
);
236 timer_writel(0x000c, TIMERUS_USEC_CFG
);
239 timer_writel(0x045f, TIMERUS_USEC_CFG
);
242 timer_writel(0x0019, TIMERUS_USEC_CFG
);
245 WARN(1, "Unknown clock rate");
248 setup_sched_clock(tegra_read_sched_clock
, 32, 1000000);
250 if (clocksource_mmio_init(timer_reg_base
+ TIMERUS_CNTR_1US
,
251 "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up
)) {
252 pr_err("Failed to register clocksource\n");
256 ret
= setup_irq(tegra_timer_irq
.irq
, &tegra_timer_irq
);
258 pr_err("Failed to register timer IRQ: %d\n", ret
);
262 clockevents_calc_mult_shift(&tegra_clockevent
, 1000000, 5);
263 tegra_clockevent
.max_delta_ns
=
264 clockevent_delta2ns(0x1fffffff, &tegra_clockevent
);
265 tegra_clockevent
.min_delta_ns
=
266 clockevent_delta2ns(0x1, &tegra_clockevent
);
267 tegra_clockevent
.cpumask
= cpu_all_mask
;
268 tegra_clockevent
.irq
= tegra_timer_irq
.irq
;
269 clockevents_register_device(&tegra_clockevent
);
270 #ifdef CONFIG_HAVE_ARM_TWD
271 twd_local_timer_of_register();
273 register_persistent_clock(NULL
, tegra_read_persistent_clock
);
277 static u32 usec_config
;
279 void tegra_timer_suspend(void)
281 usec_config
= timer_readl(TIMERUS_USEC_CFG
);
284 void tegra_timer_resume(void)
286 timer_writel(usec_config
, TIMERUS_USEC_CFG
);