arch/arm/mach-ux500/cpu-db8500.c

   1 /*
   2  * Copyright (C) 2008-2009 ST-Ericsson SA
   3  *
   4  * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2, as
   8  * published by the Free Software Foundation.
   9  *
  10  */
  11 #include <linux/types.h>
  12 #include <linux/init.h>
  13 #include <linux/device.h>
  14 #include <linux/amba/bus.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/irq.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/io.h>
  19 #include <linux/mfd/abx500/ab8500.h>
  20 #include <linux/mfd/dbx500-prcmu.h>
  21 #include <linux/of.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/regulator/machine.h>
  24 #include <linux/platform_data/pinctrl-nomadik.h>
  25 #include <linux/random.h>
  26
  27 #include <asm/pmu.h>
  28 #include <asm/mach/map.h>
  29 #include <asm/mach/arch.h>
  30
  31 #include "setup.h"
  32 #include "devices.h"
  33 #include "irqs.h"
  34
  35 #include "devices-db8500.h"
  36 #include "ste-dma40-db8500.h"
  37 #include "db8500-regs.h"
  38 #include "board-mop500.h"
  39 #include "id.h"
  40
  41 /* minimum static i/o mapping required to boot U8500 platforms */
  42 static struct map_desc u8500_uart_io_desc[] __initdata = {
  43         __IO_DEV_DESC(U8500_UART0_BASE, SZ_4K),
  44         __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K),
  45 };
  46 /*  U8500 and U9540 common io_desc */
  47 static struct map_desc u8500_common_io_desc[] __initdata = {
  48         /* SCU base also covers GIC CPU BASE and TWD with its 4K page */
  49         __IO_DEV_DESC(U8500_SCU_BASE, SZ_4K),
  50         __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K),
  51         __IO_DEV_DESC(U8500_L2CC_BASE, SZ_4K),
  52         __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
  53         __IO_DEV_DESC(U8500_BACKUPRAM0_BASE, SZ_8K),
  54
  55         __IO_DEV_DESC(U8500_CLKRST1_BASE, SZ_4K),
  56         __IO_DEV_DESC(U8500_CLKRST2_BASE, SZ_4K),
  57         __IO_DEV_DESC(U8500_CLKRST3_BASE, SZ_4K),
  58         __IO_DEV_DESC(U8500_CLKRST5_BASE, SZ_4K),
  59         __IO_DEV_DESC(U8500_CLKRST6_BASE, SZ_4K),
  60
  61         __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K),
  62         __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
  63         __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
  64         __IO_DEV_DESC(U8500_GPIO3_BASE, SZ_4K),
  65 };
  66
  67 /* U8500 IO map specific description */
  68 static struct map_desc u8500_io_desc[] __initdata = {
  69         __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K),
  70         __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
  71
  72 };
  73
  74 /* U9540 IO map specific description */
  75 static struct map_desc u9540_io_desc[] __initdata = {
  76         __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K + SZ_8K),
  77         __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K + SZ_8K),
  78 };
  79
  80 void __init u8500_map_io(void)
  81 {
  82         /*
  83          * Map the UARTs early so that the DEBUG_LL stuff continues to work.
  84          */
  85         iotable_init(u8500_uart_io_desc, ARRAY_SIZE(u8500_uart_io_desc));
  86
  87         ux500_map_io();
  88
  89         iotable_init(u8500_common_io_desc, ARRAY_SIZE(u8500_common_io_desc));
  90
  91         if (cpu_is_ux540_family())
  92                 iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc));
  93         else
  94                 iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
  95 }
  96
  97 static struct resource db8500_pmu_resources[] = {
  98         [0] = {
  99                 .start          = IRQ_DB8500_PMU,
 100                 .end            = IRQ_DB8500_PMU,
 101                 .flags          = IORESOURCE_IRQ,
 102         },
 103 };
 104
 105 /*
 106  * The PMU IRQ lines of two cores are wired together into a single interrupt.
 107  * Bounce the interrupt to the other core if it's not ours.
 108  */
 109 static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler)
 110 {
 111         irqreturn_t ret = handler(irq, dev);
 112         int other = !smp_processor_id();
 113
 114         if (ret == IRQ_NONE && cpu_online(other))
 115                 irq_set_affinity(irq, cpumask_of(other));
 116
 117         /*
 118          * We should be able to get away with the amount of IRQ_NONEs we give,
 119          * while still having the spurious IRQ detection code kick in if the
 120          * interrupt really starts hitting spuriously.
 121          */
 122         return ret;
 123 }
 124
 125 struct arm_pmu_platdata db8500_pmu_platdata = {
 126         .handle_irq             = db8500_pmu_handler,
 127 };
 128
 129 static struct platform_device db8500_pmu_device = {
 130         .name                   = "arm-pmu",
 131         .id                     = -1,
 132         .num_resources          = ARRAY_SIZE(db8500_pmu_resources),
 133         .resource               = db8500_pmu_resources,
 134         .dev.platform_data      = &db8500_pmu_platdata,
 135 };
 136
 137 static struct platform_device *platform_devs[] __initdata = {
 138         &u8500_dma40_device,
 139         &db8500_pmu_device,
 140 };
 141
 142 static resource_size_t __initdata db8500_gpio_base[] = {
 143         U8500_GPIOBANK0_BASE,
 144         U8500_GPIOBANK1_BASE,
 145         U8500_GPIOBANK2_BASE,
 146         U8500_GPIOBANK3_BASE,
 147         U8500_GPIOBANK4_BASE,
 148         U8500_GPIOBANK5_BASE,
 149         U8500_GPIOBANK6_BASE,
 150         U8500_GPIOBANK7_BASE,
 151         U8500_GPIOBANK8_BASE,
 152 };
 153
 154 static void __init db8500_add_gpios(struct device *parent)
 155 {
 156         struct nmk_gpio_platform_data pdata = {
 157                 .supports_sleepmode = true,
 158         };
 159
 160         dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base),
 161                          IRQ_DB8500_GPIO0, &pdata);
 162         dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE);
 163 }
 164
 165 static int usb_db8500_dma_cfg[] = {
 166         DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9,
 167         DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10,
 168         DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11,
 169         DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12,
 170         DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13,
 171         DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14,
 172         DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15,
 173         DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8
 174 };
 175
 176 static const char *db8500_read_soc_id(void)
 177 {
 178         void __iomem *uid = __io_address(U8500_BB_UID_BASE);
 179
 180         /* Throw these device-specific numbers into the entropy pool */
 181         add_device_randomness(uid, 0x14);
 182         return kasprintf(GFP_KERNEL, "%08x%08x%08x%08x%08x",
 183                          readl((u32 *)uid+0),
 184                          readl((u32 *)uid+1), readl((u32 *)uid+2),
 185                          readl((u32 *)uid+3), readl((u32 *)uid+4));
 186 }
 187
 188 static struct device * __init db8500_soc_device_init(void)
 189 {
 190         const char *soc_id = db8500_read_soc_id();
 191
 192         return ux500_soc_device_init(soc_id);
 193 }
 194
 195 /*
 196  * This function is called from the board init
 197  */
 198 struct device * __init u8500_init_devices(void)
 199 {
 200         struct device *parent;
 201         int i;
 202
 203         parent = db8500_soc_device_init();
 204
 205         db8500_add_rtc(parent);
 206         db8500_add_gpios(parent);
 207         db8500_add_usb(parent, usb_db8500_dma_cfg, usb_db8500_dma_cfg);
 208
 209         for (i = 0; i < ARRAY_SIZE(platform_devs); i++)
 210                 platform_devs[i]->dev.parent = parent;
 211
 212         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
 213
 214         return parent;
 215 }
 216
 217 #ifdef CONFIG_MACH_UX500_DT
 218 static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
 219         /* Requires call-back bindings. */
 220         OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
 221         /* Requires DMA bindings. */
 222         OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL),
 223         OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL),
 224         OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL),
 225         OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
 226         OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  &mop500_sdi0_data),
 227         OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1",  &mop500_sdi1_data),
 228         OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2",  &mop500_sdi2_data),
 229         OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4",  &mop500_sdi4_data),
 230         /* Requires clock name bindings. */
 231         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
 232         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
 233         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e000, "gpio.2", NULL),
 234         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e080, "gpio.3", NULL),
 235         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e100, "gpio.4", NULL),
 236         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8000e180, "gpio.5", NULL),
 237         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL),
 238         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL),
 239         OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL),
 240         OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL),
 241         OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL),
 242         OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
 243         OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
 244         OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
 245         OF_DEV_AUXDATA("stericsson,db8500-musb", 0xa03e0000, "musb-ux500.0", NULL),
 246         OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
 247                         &db8500_prcmu_pdata),
 248         OF_DEV_AUXDATA("smsc,lan9115", 0x50000000, "smsc911x.0", NULL),
 249         OF_DEV_AUXDATA("stericsson,ux500-cryp", 0xa03cb000, "cryp1", NULL),
 250         OF_DEV_AUXDATA("stericsson,ux500-hash", 0xa03c2000, "hash1", NULL),
 251         OF_DEV_AUXDATA("stericsson,snd-soc-mop500", 0, "snd-soc-mop500.0",
 252                         NULL),
 253         /* Requires device name bindings. */
 254         OF_DEV_AUXDATA("stericsson,db8500-pinctrl", U8500_PRCMU_BASE,
 255                 "pinctrl-db8500", NULL),
 256         /* Requires clock name and DMA bindings. */
 257         OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
 258                 "ux500-msp-i2s.0", &msp0_platform_data),
 259         OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
 260                 "ux500-msp-i2s.1", &msp1_platform_data),
 261         OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000,
 262                 "ux500-msp-i2s.2", &msp2_platform_data),
 263         OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
 264                 "ux500-msp-i2s.3", &msp3_platform_data),
 265         /* Requires clock name bindings and channel address lookup table. */
 266         OF_DEV_AUXDATA("stericsson,db8500-dma40", 0x801C0000, "dma40.0", NULL),
 267         {},
 268 };
 269
 270 static struct of_dev_auxdata u8540_auxdata_lookup[] __initdata = {
 271         /* Requires DMA bindings. */
 272         OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL),
 273         OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL),
 274         OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL),
 275         OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu",
 276                         &db8500_prcmu_pdata),
 277         {},
 278 };
 279
 280 static const struct of_device_id u8500_local_bus_nodes[] = {
 281         /* only create devices below soc node */
 282         { .compatible = "stericsson,db8500", },
 283         { .compatible = "stericsson,db8500-prcmu", },
 284         { .compatible = "simple-bus"},
 285         { },
 286 };
 287
 288 static void __init u8500_init_machine(void)
 289 {
 290         struct device *parent = db8500_soc_device_init();
 291
 292         /* Pinmaps must be in place before devices register */
 293         if (of_machine_is_compatible("st-ericsson,mop500"))
 294                 mop500_pinmaps_init();
 295         else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
 296                 snowball_pinmaps_init();
 297         } else if (of_machine_is_compatible("st-ericsson,hrefv60+"))
 298                 hrefv60_pinmaps_init();
 299         else if (of_machine_is_compatible("st-ericsson,ccu9540")) {}
 300                 /* TODO: Add pinmaps for ccu9540 board. */
 301
 302         /* automatically probe child nodes of dbx5x0 devices */
 303         if (of_machine_is_compatible("st-ericsson,u8540"))
 304                 of_platform_populate(NULL, u8500_local_bus_nodes,
 305                                      u8540_auxdata_lookup, parent);
 306         else
 307                 of_platform_populate(NULL, u8500_local_bus_nodes,
 308                                      u8500_auxdata_lookup, parent);
 309 }
 310
 311 static const char * stericsson_dt_platform_compat[] = {
 312         "st-ericsson,u8500",
 313         "st-ericsson,u8540",
 314         "st-ericsson,u9500",
 315         "st-ericsson,u9540",
 316         NULL,
 317 };
 318
 319 DT_MACHINE_START(U8500_DT, "ST-Ericsson Ux5x0 platform (Device Tree Support)")
 320         .smp            = smp_ops(ux500_smp_ops),
 321         .map_io         = u8500_map_io,
 322         .init_irq       = ux500_init_irq,
 323         /* we re-use nomadik timer here */
 324         .init_time      = ux500_timer_init,
 325         .init_machine   = u8500_init_machine,
 326         .init_late      = NULL,
 327         .dt_compat      = stericsson_dt_platform_compat,
 328 MACHINE_END
 329
 330 #endif