arch/arm/mach-ux500/timer.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2011
   3  *
   4  * License Terms: GNU General Public License v2
   5  * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
   6  */
   7 #include <linux/io.h>
   8 #include <linux/errno.h>
   9 #include <linux/clksrc-dbx500-prcmu.h>
  10 #include <linux/of.h>
  11 #include <linux/of_address.h>
  12 #include <linux/platform_data/clocksource-nomadik-mtu.h>
  13
  14 #include <asm/smp_twd.h>
  15
  16 #include <mach/setup.h>
  17 #include <mach/hardware.h>
  18 #include <mach/irqs.h>
  19
  20 #ifdef CONFIG_HAVE_ARM_TWD
  21 static DEFINE_TWD_LOCAL_TIMER(u8500_twd_local_timer,
  22                               U8500_TWD_BASE, IRQ_LOCALTIMER);
  23
  24 static void __init ux500_twd_init(void)
  25 {
  26         struct twd_local_timer *twd_local_timer;
  27         int err;
  28
  29         /* Use this to switch local timer base if changed in new ASICs */
  30         twd_local_timer = &u8500_twd_local_timer;
  31
  32         if (of_have_populated_dt())
  33                 twd_local_timer_of_register();
  34         else {
  35                 err = twd_local_timer_register(twd_local_timer);
  36                 if (err)
  37                         pr_err("twd_local_timer_register failed %d\n", err);
  38         }
  39 }
  40 #else
  41 #define ux500_twd_init()        do { } while(0)
  42 #endif
  43
  44 const static struct of_device_id prcmu_timer_of_match[] __initconst = {
  45         { .compatible = "stericsson,db8500-prcmu-timer-4", },
  46         { },
  47 };
  48
  49 static void __init ux500_timer_init(void)
  50 {
  51         void __iomem *mtu_timer_base;
  52         void __iomem *prcmu_timer_base;
  53         void __iomem *tmp_base;
  54         struct device_node *np;
  55
  56         if (cpu_is_u8500_family() || cpu_is_ux540_family()) {
  57                 mtu_timer_base = __io_address(U8500_MTU0_BASE);
  58                 prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
  59         } else {
  60                 ux500_unknown_soc();
  61         }
  62
  63         /* TODO: Once MTU has been DT:ed place code above into else. */
  64         if (of_have_populated_dt()) {
  65 #ifdef CONFIG_OF
  66                 np = of_find_matching_node(NULL, prcmu_timer_of_match);
  67                 if (!np)
  68 #endif
  69                         goto dt_fail;
  70
  71                 tmp_base = of_iomap(np, 0);
  72                 if (!tmp_base)
  73                         goto dt_fail;
  74
  75                 prcmu_timer_base = tmp_base;
  76         }
  77
  78 dt_fail:
  79         /* Doing it the old fashioned way. */
  80
  81         /*
  82          * Here we register the timerblocks active in the system.
  83          * Localtimers (twd) is started when both cpu is up and running.
  84          * MTU register a clocksource, clockevent and sched_clock.
  85          * Since the MTU is located in the VAPE power domain
  86          * it will be cleared in sleep which makes it unsuitable.
  87          * We however need it as a timer tick (clockevent)
  88          * during boot to calibrate delay until twd is started.
  89          * RTC-RTT have problems as timer tick during boot since it is
  90          * depending on delay which is not yet calibrated. RTC-RTT is in the
  91          * always-on powerdomain and is used as clockevent instead of twd when
  92          * sleeping.
  93          * The PRCMU timer 4 register a clocksource and
  94          * sched_clock with higher rating then MTU since is always-on.
  95          *
  96          */
  97
  98         nmdk_timer_init(mtu_timer_base, IRQ_MTU0);
  99         clksrc_dbx500_prcmu_init(prcmu_timer_base);
 100         ux500_twd_init();
 101 }
 102
 103 static void ux500_timer_reset(void)
 104 {
 105         nmdk_clkevt_reset();
 106         nmdk_clksrc_reset();
 107 }
 108
 109 struct sys_timer ux500_timer = {
 110         .init           = ux500_timer_init,
 111         .resume         = ux500_timer_reset,
 112 };