2 * linux/arch/arm/mach-versatile/core.c
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/config.h>
22 #include <linux/init.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/platform_device.h>
26 #include <linux/sysdev.h>
27 #include <linux/interrupt.h>
29 #include <asm/system.h>
30 #include <asm/hardware.h>
34 #include <asm/hardware/amba.h>
35 #include <asm/hardware/amba_clcd.h>
36 #include <asm/hardware/arm_timer.h>
37 #include <asm/hardware/icst307.h>
39 #include <asm/mach/arch.h>
40 #include <asm/mach/flash.h>
41 #include <asm/mach/irq.h>
42 #include <asm/mach/time.h>
43 #include <asm/mach/map.h>
44 #include <asm/mach/mmc.h>
50 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
53 * Setup a VA for the Versatile Vectored Interrupt Controller.
55 #define __io_address(n) __io(IO_ADDRESS(n))
56 #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
57 #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
59 static void vic_mask_irq(unsigned int irq
)
62 writel(1 << irq
, VA_VIC_BASE
+ VIC_IRQ_ENABLE_CLEAR
);
65 static void vic_unmask_irq(unsigned int irq
)
68 writel(1 << irq
, VA_VIC_BASE
+ VIC_IRQ_ENABLE
);
71 static struct irqchip vic_chip
= {
74 .unmask
= vic_unmask_irq
,
77 static void sic_mask_irq(unsigned int irq
)
80 writel(1 << irq
, VA_SIC_BASE
+ SIC_IRQ_ENABLE_CLEAR
);
83 static void sic_unmask_irq(unsigned int irq
)
86 writel(1 << irq
, VA_SIC_BASE
+ SIC_IRQ_ENABLE_SET
);
89 static struct irqchip sic_chip
= {
92 .unmask
= sic_unmask_irq
,
96 sic_handle_irq(unsigned int irq
, struct irqdesc
*desc
, struct pt_regs
*regs
)
98 unsigned long status
= readl(VA_SIC_BASE
+ SIC_IRQ_STATUS
);
101 do_bad_IRQ(irq
, desc
, regs
);
106 irq
= ffs(status
) - 1;
107 status
&= ~(1 << irq
);
109 irq
+= IRQ_SIC_START
;
111 desc
= irq_desc
+ irq
;
112 desc_handle_irq(irq
, desc
, regs
);
117 #define IRQ_MMCI0A IRQ_VICSOURCE22
118 #define IRQ_AACI IRQ_VICSOURCE24
119 #define IRQ_ETH IRQ_VICSOURCE25
120 #define PIC_MASK 0xFFD00000
122 #define IRQ_MMCI0A IRQ_SIC_MMCI0A
123 #define IRQ_AACI IRQ_SIC_AACI
124 #define IRQ_ETH IRQ_SIC_ETH
128 void __init
versatile_init_irq(void)
130 unsigned int i
, value
;
132 /* Disable all interrupts initially. */
134 writel(0, VA_VIC_BASE
+ VIC_INT_SELECT
);
135 writel(0, VA_VIC_BASE
+ VIC_IRQ_ENABLE
);
136 writel(~0, VA_VIC_BASE
+ VIC_IRQ_ENABLE_CLEAR
);
137 writel(0, VA_VIC_BASE
+ VIC_IRQ_STATUS
);
138 writel(0, VA_VIC_BASE
+ VIC_ITCR
);
139 writel(~0, VA_VIC_BASE
+ VIC_IRQ_SOFT_CLEAR
);
142 * Make sure we clear all existing interrupts
144 writel(0, VA_VIC_BASE
+ VIC_VECT_ADDR
);
145 for (i
= 0; i
< 19; i
++) {
146 value
= readl(VA_VIC_BASE
+ VIC_VECT_ADDR
);
147 writel(value
, VA_VIC_BASE
+ VIC_VECT_ADDR
);
150 for (i
= 0; i
< 16; i
++) {
151 value
= readl(VA_VIC_BASE
+ VIC_VECT_CNTL0
+ (i
* 4));
152 writel(value
| VICVectCntl_Enable
| i
, VA_VIC_BASE
+ VIC_VECT_CNTL0
+ (i
* 4));
155 writel(32, VA_VIC_BASE
+ VIC_DEF_VECT_ADDR
);
157 for (i
= IRQ_VIC_START
; i
<= IRQ_VIC_END
; i
++) {
158 if (i
!= IRQ_VICSOURCE31
) {
159 set_irq_chip(i
, &vic_chip
);
160 set_irq_handler(i
, do_level_IRQ
);
161 set_irq_flags(i
, IRQF_VALID
| IRQF_PROBE
);
165 set_irq_handler(IRQ_VICSOURCE31
, sic_handle_irq
);
166 vic_unmask_irq(IRQ_VICSOURCE31
);
168 /* Do second interrupt controller */
169 writel(~0, VA_SIC_BASE
+ SIC_IRQ_ENABLE_CLEAR
);
171 for (i
= IRQ_SIC_START
; i
<= IRQ_SIC_END
; i
++) {
172 if ((PIC_MASK
& (1 << (i
- IRQ_SIC_START
))) == 0) {
173 set_irq_chip(i
, &sic_chip
);
174 set_irq_handler(i
, do_level_IRQ
);
175 set_irq_flags(i
, IRQF_VALID
| IRQF_PROBE
);
180 * Interrupts on secondary controller from 0 to 8 are routed to
182 * Interrupts from 21 to 31 are routed directly to the VIC on
183 * the corresponding number on primary controller. This is controlled
184 * by setting PIC_ENABLEx.
186 writel(PIC_MASK
, VA_SIC_BASE
+ SIC_INT_PIC_ENABLE
);
189 static struct map_desc versatile_io_desc
[] __initdata
= {
191 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE
),
192 .pfn
= __phys_to_pfn(VERSATILE_SYS_BASE
),
196 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE
),
197 .pfn
= __phys_to_pfn(VERSATILE_SIC_BASE
),
201 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE
),
202 .pfn
= __phys_to_pfn(VERSATILE_VIC_BASE
),
206 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE
),
207 .pfn
= __phys_to_pfn(VERSATILE_SCTL_BASE
),
211 #ifdef CONFIG_MACH_VERSATILE_AB
213 .virtual = IO_ADDRESS(VERSATILE_GPIO0_BASE
),
214 .pfn
= __phys_to_pfn(VERSATILE_GPIO0_BASE
),
218 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE
),
219 .pfn
= __phys_to_pfn(VERSATILE_IB2_BASE
),
224 #ifdef CONFIG_DEBUG_LL
226 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE
),
227 .pfn
= __phys_to_pfn(VERSATILE_UART0_BASE
),
234 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE
),
235 .pfn
= __phys_to_pfn(VERSATILE_PCI_CORE_BASE
),
239 .virtual = VERSATILE_PCI_VIRT_BASE
,
240 .pfn
= __phys_to_pfn(VERSATILE_PCI_BASE
),
241 .length
= VERSATILE_PCI_BASE_SIZE
,
244 .virtual = VERSATILE_PCI_CFG_VIRT_BASE
,
245 .pfn
= __phys_to_pfn(VERSATILE_PCI_CFG_BASE
),
246 .length
= VERSATILE_PCI_CFG_BASE_SIZE
,
251 .virtual = VERSATILE_PCI_VIRT_MEM_BASE0
,
252 .pfn
= __phys_to_pfn(VERSATILE_PCI_MEM_BASE0
),
256 .virtual = VERSATILE_PCI_VIRT_MEM_BASE1
,
257 .pfn
= __phys_to_pfn(VERSATILE_PCI_MEM_BASE1
),
261 .virtual = VERSATILE_PCI_VIRT_MEM_BASE2
,
262 .pfn
= __phys_to_pfn(VERSATILE_PCI_MEM_BASE2
),
270 void __init
versatile_map_io(void)
272 iotable_init(versatile_io_desc
, ARRAY_SIZE(versatile_io_desc
));
275 #define VERSATILE_REFCOUNTER (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_24MHz_OFFSET)
278 * This is the Versatile sched_clock implementation. This has
279 * a resolution of 41.7ns, and a maximum value of about 179s.
281 unsigned long long sched_clock(void)
283 unsigned long long v
;
285 v
= (unsigned long long)readl(VERSATILE_REFCOUNTER
) * 125;
292 #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
294 static int versatile_flash_init(void)
298 val
= __raw_readl(VERSATILE_FLASHCTRL
);
299 val
&= ~VERSATILE_FLASHPROG_FLVPPEN
;
300 __raw_writel(val
, VERSATILE_FLASHCTRL
);
305 static void versatile_flash_exit(void)
309 val
= __raw_readl(VERSATILE_FLASHCTRL
);
310 val
&= ~VERSATILE_FLASHPROG_FLVPPEN
;
311 __raw_writel(val
, VERSATILE_FLASHCTRL
);
314 static void versatile_flash_set_vpp(int on
)
318 val
= __raw_readl(VERSATILE_FLASHCTRL
);
320 val
|= VERSATILE_FLASHPROG_FLVPPEN
;
322 val
&= ~VERSATILE_FLASHPROG_FLVPPEN
;
323 __raw_writel(val
, VERSATILE_FLASHCTRL
);
326 static struct flash_platform_data versatile_flash_data
= {
327 .map_name
= "cfi_probe",
329 .init
= versatile_flash_init
,
330 .exit
= versatile_flash_exit
,
331 .set_vpp
= versatile_flash_set_vpp
,
334 static struct resource versatile_flash_resource
= {
335 .start
= VERSATILE_FLASH_BASE
,
336 .end
= VERSATILE_FLASH_BASE
+ VERSATILE_FLASH_SIZE
,
337 .flags
= IORESOURCE_MEM
,
340 static struct platform_device versatile_flash_device
= {
344 .platform_data
= &versatile_flash_data
,
347 .resource
= &versatile_flash_resource
,
350 static struct resource smc91x_resources
[] = {
352 .start
= VERSATILE_ETH_BASE
,
353 .end
= VERSATILE_ETH_BASE
+ SZ_64K
- 1,
354 .flags
= IORESOURCE_MEM
,
359 .flags
= IORESOURCE_IRQ
,
363 static struct platform_device smc91x_device
= {
366 .num_resources
= ARRAY_SIZE(smc91x_resources
),
367 .resource
= smc91x_resources
,
370 #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
372 unsigned int mmc_status(struct device
*dev
)
374 struct amba_device
*adev
= container_of(dev
, struct amba_device
, dev
);
377 if (adev
->res
.start
== VERSATILE_MMCI0_BASE
)
382 return readl(VERSATILE_SYSMCI
) & mask
;
385 static struct mmc_platform_data mmc0_plat_data
= {
386 .ocr_mask
= MMC_VDD_32_33
|MMC_VDD_33_34
,
387 .status
= mmc_status
,
393 static const struct icst307_params versatile_oscvco_params
= {
402 static void versatile_oscvco_set(struct clk
*clk
, struct icst307_vco vco
)
404 void __iomem
*sys_lock
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_LOCK_OFFSET
;
405 #if defined(CONFIG_ARCH_VERSATILE_PB)
406 void __iomem
*sys_osc
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_OSC4_OFFSET
;
407 #elif defined(CONFIG_MACH_VERSATILE_AB)
408 void __iomem
*sys_osc
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_OSC1_OFFSET
;
412 val
= readl(sys_osc
) & ~0x7ffff;
413 val
|= vco
.v
| (vco
.r
<< 9) | (vco
.s
<< 16);
415 writel(0xa05f, sys_lock
);
416 writel(val
, sys_osc
);
420 static struct clk versatile_clcd_clk
= {
422 .params
= &versatile_oscvco_params
,
423 .setvco
= versatile_oscvco_set
,
429 #define SYS_CLCD_MODE_MASK (3 << 0)
430 #define SYS_CLCD_MODE_888 (0 << 0)
431 #define SYS_CLCD_MODE_5551 (1 << 0)
432 #define SYS_CLCD_MODE_565_RLSB (2 << 0)
433 #define SYS_CLCD_MODE_565_BLSB (3 << 0)
434 #define SYS_CLCD_NLCDIOON (1 << 2)
435 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
436 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
437 #define SYS_CLCD_ID_MASK (0x1f << 8)
438 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
439 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
440 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
441 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
442 #define SYS_CLCD_ID_VGA (0x1f << 8)
444 static struct clcd_panel vga
= {
458 .vmode
= FB_VMODE_NONINTERLACED
,
462 .tim2
= TIM2_BCD
| TIM2_IPC
,
463 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
467 static struct clcd_panel sanyo_3_8_in
= {
469 .name
= "Sanyo QVGA",
481 .vmode
= FB_VMODE_NONINTERLACED
,
486 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
490 static struct clcd_panel sanyo_2_5_in
= {
492 .name
= "Sanyo QVGA Portrait",
503 .sync
= FB_SYNC_HOR_HIGH_ACT
| FB_SYNC_VERT_HIGH_ACT
,
504 .vmode
= FB_VMODE_NONINTERLACED
,
508 .tim2
= TIM2_IVS
| TIM2_IHS
| TIM2_IPC
,
509 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
513 static struct clcd_panel epson_2_2_in
= {
515 .name
= "Epson QCIF",
527 .vmode
= FB_VMODE_NONINTERLACED
,
531 .tim2
= TIM2_BCD
| TIM2_IPC
,
532 .cntl
= CNTL_LCDTFT
| CNTL_LCDVCOMP(1),
537 * Detect which LCD panel is connected, and return the appropriate
538 * clcd_panel structure. Note: we do not have any information on
539 * the required timings for the 8.4in panel, so we presently assume
542 static struct clcd_panel
*versatile_clcd_panel(void)
544 void __iomem
*sys_clcd
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_CLCD_OFFSET
;
545 struct clcd_panel
*panel
= &vga
;
548 val
= readl(sys_clcd
) & SYS_CLCD_ID_MASK
;
549 if (val
== SYS_CLCD_ID_SANYO_3_8
)
550 panel
= &sanyo_3_8_in
;
551 else if (val
== SYS_CLCD_ID_SANYO_2_5
)
552 panel
= &sanyo_2_5_in
;
553 else if (val
== SYS_CLCD_ID_EPSON_2_2
)
554 panel
= &epson_2_2_in
;
555 else if (val
== SYS_CLCD_ID_VGA
)
558 printk(KERN_ERR
"CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
567 * Disable all display connectors on the interface module.
569 static void versatile_clcd_disable(struct clcd_fb
*fb
)
571 void __iomem
*sys_clcd
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_CLCD_OFFSET
;
574 val
= readl(sys_clcd
);
575 val
&= ~SYS_CLCD_NLCDIOON
| SYS_CLCD_PWR3V5SWITCH
;
576 writel(val
, sys_clcd
);
578 #ifdef CONFIG_MACH_VERSATILE_AB
580 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
582 if (fb
->panel
== &sanyo_2_5_in
) {
583 void __iomem
*versatile_ib2_ctrl
= __io_address(VERSATILE_IB2_CTRL
);
586 ctrl
= readl(versatile_ib2_ctrl
);
588 writel(ctrl
, versatile_ib2_ctrl
);
594 * Enable the relevant connector on the interface module.
596 static void versatile_clcd_enable(struct clcd_fb
*fb
)
598 void __iomem
*sys_clcd
= __io_address(VERSATILE_SYS_BASE
) + VERSATILE_SYS_CLCD_OFFSET
;
601 val
= readl(sys_clcd
);
602 val
&= ~SYS_CLCD_MODE_MASK
;
604 switch (fb
->fb
.var
.green
.length
) {
606 val
|= SYS_CLCD_MODE_5551
;
609 val
|= SYS_CLCD_MODE_565_RLSB
;
612 val
|= SYS_CLCD_MODE_888
;
619 writel(val
, sys_clcd
);
622 * And now enable the PSUs
624 val
|= SYS_CLCD_NLCDIOON
| SYS_CLCD_PWR3V5SWITCH
;
625 writel(val
, sys_clcd
);
627 #ifdef CONFIG_MACH_VERSATILE_AB
629 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
631 if (fb
->panel
== &sanyo_2_5_in
) {
632 void __iomem
*versatile_ib2_ctrl
= __io_address(VERSATILE_IB2_CTRL
);
635 ctrl
= readl(versatile_ib2_ctrl
);
637 writel(ctrl
, versatile_ib2_ctrl
);
642 static unsigned long framesize
= SZ_1M
;
644 static int versatile_clcd_setup(struct clcd_fb
*fb
)
648 fb
->panel
= versatile_clcd_panel();
650 fb
->fb
.screen_base
= dma_alloc_writecombine(&fb
->dev
->dev
, framesize
,
652 if (!fb
->fb
.screen_base
) {
653 printk(KERN_ERR
"CLCD: unable to map framebuffer\n");
657 fb
->fb
.fix
.smem_start
= dma
;
658 fb
->fb
.fix
.smem_len
= framesize
;
663 static int versatile_clcd_mmap(struct clcd_fb
*fb
, struct vm_area_struct
*vma
)
665 return dma_mmap_writecombine(&fb
->dev
->dev
, vma
,
667 fb
->fb
.fix
.smem_start
,
668 fb
->fb
.fix
.smem_len
);
671 static void versatile_clcd_remove(struct clcd_fb
*fb
)
673 dma_free_writecombine(&fb
->dev
->dev
, fb
->fb
.fix
.smem_len
,
674 fb
->fb
.screen_base
, fb
->fb
.fix
.smem_start
);
677 static struct clcd_board clcd_plat_data
= {
679 .check
= clcdfb_check
,
680 .decode
= clcdfb_decode
,
681 .disable
= versatile_clcd_disable
,
682 .enable
= versatile_clcd_enable
,
683 .setup
= versatile_clcd_setup
,
684 .mmap
= versatile_clcd_mmap
,
685 .remove
= versatile_clcd_remove
,
688 #define AACI_IRQ { IRQ_AACI, NO_IRQ }
689 #define AACI_DMA { 0x80, 0x81 }
690 #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
691 #define MMCI0_DMA { 0x84, 0 }
692 #define KMI0_IRQ { IRQ_SIC_KMI0, NO_IRQ }
693 #define KMI0_DMA { 0, 0 }
694 #define KMI1_IRQ { IRQ_SIC_KMI1, NO_IRQ }
695 #define KMI1_DMA { 0, 0 }
698 * These devices are connected directly to the multi-layer AHB switch
700 #define SMC_IRQ { NO_IRQ, NO_IRQ }
701 #define SMC_DMA { 0, 0 }
702 #define MPMC_IRQ { NO_IRQ, NO_IRQ }
703 #define MPMC_DMA { 0, 0 }
704 #define CLCD_IRQ { IRQ_CLCDINT, NO_IRQ }
705 #define CLCD_DMA { 0, 0 }
706 #define DMAC_IRQ { IRQ_DMAINT, NO_IRQ }
707 #define DMAC_DMA { 0, 0 }
710 * These devices are connected via the core APB bridge
712 #define SCTL_IRQ { NO_IRQ, NO_IRQ }
713 #define SCTL_DMA { 0, 0 }
714 #define WATCHDOG_IRQ { IRQ_WDOGINT, NO_IRQ }
715 #define WATCHDOG_DMA { 0, 0 }
716 #define GPIO0_IRQ { IRQ_GPIOINT0, NO_IRQ }
717 #define GPIO0_DMA { 0, 0 }
718 #define GPIO1_IRQ { IRQ_GPIOINT1, NO_IRQ }
719 #define GPIO1_DMA { 0, 0 }
720 #define RTC_IRQ { IRQ_RTCINT, NO_IRQ }
721 #define RTC_DMA { 0, 0 }
724 * These devices are connected via the DMA APB bridge
726 #define SCI_IRQ { IRQ_SCIINT, NO_IRQ }
727 #define SCI_DMA { 7, 6 }
728 #define UART0_IRQ { IRQ_UARTINT0, NO_IRQ }
729 #define UART0_DMA { 15, 14 }
730 #define UART1_IRQ { IRQ_UARTINT1, NO_IRQ }
731 #define UART1_DMA { 13, 12 }
732 #define UART2_IRQ { IRQ_UARTINT2, NO_IRQ }
733 #define UART2_DMA { 11, 10 }
734 #define SSP_IRQ { IRQ_SSPINT, NO_IRQ }
735 #define SSP_DMA { 9, 8 }
737 /* FPGA Primecells */
738 AMBA_DEVICE(aaci
, "fpga:04", AACI
, NULL
);
739 AMBA_DEVICE(mmc0
, "fpga:05", MMCI0
, &mmc0_plat_data
);
740 AMBA_DEVICE(kmi0
, "fpga:06", KMI0
, NULL
);
741 AMBA_DEVICE(kmi1
, "fpga:07", KMI1
, NULL
);
743 /* DevChip Primecells */
744 AMBA_DEVICE(smc
, "dev:00", SMC
, NULL
);
745 AMBA_DEVICE(mpmc
, "dev:10", MPMC
, NULL
);
746 AMBA_DEVICE(clcd
, "dev:20", CLCD
, &clcd_plat_data
);
747 AMBA_DEVICE(dmac
, "dev:30", DMAC
, NULL
);
748 AMBA_DEVICE(sctl
, "dev:e0", SCTL
, NULL
);
749 AMBA_DEVICE(wdog
, "dev:e1", WATCHDOG
, NULL
);
750 AMBA_DEVICE(gpio0
, "dev:e4", GPIO0
, NULL
);
751 AMBA_DEVICE(gpio1
, "dev:e5", GPIO1
, NULL
);
752 AMBA_DEVICE(rtc
, "dev:e8", RTC
, NULL
);
753 AMBA_DEVICE(sci0
, "dev:f0", SCI
, NULL
);
754 AMBA_DEVICE(uart0
, "dev:f1", UART0
, NULL
);
755 AMBA_DEVICE(uart1
, "dev:f2", UART1
, NULL
);
756 AMBA_DEVICE(uart2
, "dev:f3", UART2
, NULL
);
757 AMBA_DEVICE(ssp0
, "dev:f4", SSP
, NULL
);
759 static struct amba_device
*amba_devs
[] __initdata
= {
781 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
783 static void versatile_leds_event(led_event_t ledevt
)
788 local_irq_save(flags
);
789 val
= readl(VA_LEDS_BASE
);
793 val
= val
& ~VERSATILE_SYS_LED0
;
797 val
= val
| VERSATILE_SYS_LED0
;
801 val
= val
^ VERSATILE_SYS_LED1
;
812 writel(val
, VA_LEDS_BASE
);
813 local_irq_restore(flags
);
815 #endif /* CONFIG_LEDS */
817 void __init
versatile_init(void)
821 clk_register(&versatile_clcd_clk
);
823 platform_device_register(&versatile_flash_device
);
824 platform_device_register(&smc91x_device
);
826 for (i
= 0; i
< ARRAY_SIZE(amba_devs
); i
++) {
827 struct amba_device
*d
= amba_devs
[i
];
828 amba_device_register(d
, &iomem_resource
);
832 leds_event
= versatile_leds_event
;
837 * Where is the timer (VA)?
839 #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
840 #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
841 #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
842 #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
843 #define VA_IC_BASE __io_address(VERSATILE_VIC_BASE)
846 * How long is the timer interval?
848 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
849 #if TIMER_INTERVAL >= 0x100000
850 #define TIMER_RELOAD (TIMER_INTERVAL >> 8)
851 #define TIMER_DIVISOR (TIMER_CTRL_DIV256)
852 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
853 #elif TIMER_INTERVAL >= 0x10000
854 #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
855 #define TIMER_DIVISOR (TIMER_CTRL_DIV16)
856 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
858 #define TIMER_RELOAD (TIMER_INTERVAL)
859 #define TIMER_DIVISOR (TIMER_CTRL_DIV1)
860 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
864 * Returns number of ms since last clock interrupt. Note that interrupts
865 * will have been disabled by do_gettimeoffset()
867 static unsigned long versatile_gettimeoffset(void)
869 unsigned long ticks1
, ticks2
, status
;
872 * Get the current number of ticks. Note that there is a race
873 * condition between us reading the timer and checking for
874 * an interrupt. We get around this by ensuring that the
875 * counter has not reloaded between our two reads.
877 ticks2
= readl(TIMER0_VA_BASE
+ TIMER_VALUE
) & 0xffff;
880 status
= __raw_readl(VA_IC_BASE
+ VIC_IRQ_RAW_STATUS
);
881 ticks2
= readl(TIMER0_VA_BASE
+ TIMER_VALUE
) & 0xffff;
882 } while (ticks2
> ticks1
);
885 * Number of ticks since last interrupt.
887 ticks1
= TIMER_RELOAD
- ticks2
;
890 * Interrupt pending? If so, we've reloaded once already.
892 * FIXME: Need to check this is effectively timer 0 that expires
894 if (status
& IRQMASK_TIMERINT0_1
)
895 ticks1
+= TIMER_RELOAD
;
898 * Convert the ticks to usecs
900 return TICKS2USECS(ticks1
);
904 * IRQ handler for the timer
906 static irqreturn_t
versatile_timer_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
908 write_seqlock(&xtime_lock
);
910 // ...clear the interrupt
911 writel(1, TIMER0_VA_BASE
+ TIMER_INTCLR
);
915 write_sequnlock(&xtime_lock
);
920 static struct irqaction versatile_timer_irq
= {
921 .name
= "Versatile Timer Tick",
922 .flags
= SA_INTERRUPT
| SA_TIMER
,
923 .handler
= versatile_timer_interrupt
,
927 * Set up timer interrupt, and return the current time in seconds.
929 static void __init
versatile_timer_init(void)
934 * set clock frequency:
935 * VERSATILE_REFCLK is 32KHz
936 * VERSATILE_TIMCLK is 1MHz
938 val
= readl(__io_address(VERSATILE_SCTL_BASE
));
939 writel((VERSATILE_TIMCLK
<< VERSATILE_TIMER1_EnSel
) |
940 (VERSATILE_TIMCLK
<< VERSATILE_TIMER2_EnSel
) |
941 (VERSATILE_TIMCLK
<< VERSATILE_TIMER3_EnSel
) |
942 (VERSATILE_TIMCLK
<< VERSATILE_TIMER4_EnSel
) | val
,
943 __io_address(VERSATILE_SCTL_BASE
));
946 * Initialise to a known state (all timers off)
948 writel(0, TIMER0_VA_BASE
+ TIMER_CTRL
);
949 writel(0, TIMER1_VA_BASE
+ TIMER_CTRL
);
950 writel(0, TIMER2_VA_BASE
+ TIMER_CTRL
);
951 writel(0, TIMER3_VA_BASE
+ TIMER_CTRL
);
953 writel(TIMER_RELOAD
, TIMER0_VA_BASE
+ TIMER_LOAD
);
954 writel(TIMER_RELOAD
, TIMER0_VA_BASE
+ TIMER_VALUE
);
955 writel(TIMER_DIVISOR
| TIMER_CTRL_ENABLE
| TIMER_CTRL_PERIODIC
|
956 TIMER_CTRL_IE
, TIMER0_VA_BASE
+ TIMER_CTRL
);
959 * Make irqs happen for the system timer
961 setup_irq(IRQ_TIMERINT0_1
, &versatile_timer_irq
);
964 struct sys_timer versatile_timer
= {
965 .init
= versatile_timer_init
,
966 .offset
= versatile_gettimeoffset
,