arch/arm/mm/Kconfig

   1 comment "Processor Type"
   2
   3 # Select CPU types depending on the architecture selected.  This selects
   4 # which CPUs we support in the kernel image, and the compiler instruction
   5 # optimiser behaviour.
   6
   7 # ARM7TDMI
   8 config CPU_ARM7TDMI
   9         bool
  10         depends on !MMU
  11         select CPU_32v4T
  12         select CPU_ABRT_LV4T
  13         select CPU_CACHE_V4
  14         select CPU_PABRT_LEGACY
  15         help
  16           A 32-bit RISC microprocessor based on the ARM7 processor core
  17           which has no memory control unit and cache.
  18
  19           Say Y if you want support for the ARM7TDMI processor.
  20           Otherwise, say N.
  21
  22 # ARM720T
  23 config CPU_ARM720T
  24         bool "Support ARM720T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
  25         select CPU_32v4T
  26         select CPU_ABRT_LV4T
  27         select CPU_CACHE_V4
  28         select CPU_CACHE_VIVT
  29         select CPU_COPY_V4WT if MMU
  30         select CPU_CP15_MMU
  31         select CPU_PABRT_LEGACY
  32         select CPU_TLB_V4WT if MMU
  33         help
  34           A 32-bit RISC processor with 8kByte Cache, Write Buffer and
  35           MMU built around an ARM7TDMI core.
  36
  37           Say Y if you want support for the ARM720T processor.
  38           Otherwise, say N.
  39
  40 # ARM740T
  41 config CPU_ARM740T
  42         bool "Support ARM740T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
  43         depends on !MMU
  44         select CPU_32v4T
  45         select CPU_ABRT_LV4T
  46         select CPU_CACHE_V4
  47         select CPU_CP15_MPU
  48         select CPU_PABRT_LEGACY
  49         help
  50           A 32-bit RISC processor with 8KB cache or 4KB variants,
  51           write buffer and MPU(Protection Unit) built around
  52           an ARM7TDMI core.
  53
  54           Say Y if you want support for the ARM740T processor.
  55           Otherwise, say N.
  56
  57 # ARM9TDMI
  58 config CPU_ARM9TDMI
  59         bool
  60         depends on !MMU
  61         select CPU_32v4T
  62         select CPU_ABRT_NOMMU
  63         select CPU_CACHE_V4
  64         select CPU_PABRT_LEGACY
  65         help
  66           A 32-bit RISC microprocessor based on the ARM9 processor core
  67           which has no memory control unit and cache.
  68
  69           Say Y if you want support for the ARM9TDMI processor.
  70           Otherwise, say N.
  71
  72 # ARM920T
  73 config CPU_ARM920T
  74         bool "Support ARM920T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
  75         select CPU_32v4T
  76         select CPU_ABRT_EV4T
  77         select CPU_CACHE_V4WT
  78         select CPU_CACHE_VIVT
  79         select CPU_COPY_V4WB if MMU
  80         select CPU_CP15_MMU
  81         select CPU_PABRT_LEGACY
  82         select CPU_TLB_V4WBI if MMU
  83         help
  84           The ARM920T is licensed to be produced by numerous vendors,
  85           and is used in the Cirrus EP93xx and the Samsung S3C2410.
  86
  87           Say Y if you want support for the ARM920T processor.
  88           Otherwise, say N.
  89
  90 # ARM922T
  91 config CPU_ARM922T
  92         bool "Support ARM922T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
  93         select CPU_32v4T
  94         select CPU_ABRT_EV4T
  95         select CPU_CACHE_V4WT
  96         select CPU_CACHE_VIVT
  97         select CPU_COPY_V4WB if MMU
  98         select CPU_CP15_MMU
  99         select CPU_PABRT_LEGACY
 100         select CPU_TLB_V4WBI if MMU
 101         help
 102           The ARM922T is a version of the ARM920T, but with smaller
 103           instruction and data caches. It is used in Altera's
 104           Excalibur XA device family and Micrel's KS8695 Centaur.
 105
 106           Say Y if you want support for the ARM922T processor.
 107           Otherwise, say N.
 108
 109 # ARM925T
 110 config CPU_ARM925T
 111         bool "Support ARM925T processor" if ARCH_OMAP1
 112         select CPU_32v4T
 113         select CPU_ABRT_EV4T
 114         select CPU_CACHE_V4WT
 115         select CPU_CACHE_VIVT
 116         select CPU_COPY_V4WB if MMU
 117         select CPU_CP15_MMU
 118         select CPU_PABRT_LEGACY
 119         select CPU_TLB_V4WBI if MMU
 120         help
 121           The ARM925T is a mix between the ARM920T and ARM926T, but with
 122           different instruction and data caches. It is used in TI's OMAP
 123           device family.
 124
 125           Say Y if you want support for the ARM925T processor.
 126           Otherwise, say N.
 127
 128 # ARM926T
 129 config CPU_ARM926T
 130         bool "Support ARM926T processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V5) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB)
 131         select CPU_32v5
 132         select CPU_ABRT_EV5TJ
 133         select CPU_CACHE_VIVT
 134         select CPU_COPY_V4WB if MMU
 135         select CPU_CP15_MMU
 136         select CPU_PABRT_LEGACY
 137         select CPU_TLB_V4WBI if MMU
 138         help
 139           This is a variant of the ARM920.  It has slightly different
 140           instruction sequences for cache and TLB operations.  Curiously,
 141           there is no documentation on it at the ARM corporate website.
 142
 143           Say Y if you want support for the ARM926T processor.
 144           Otherwise, say N.
 145
 146 # FA526
 147 config CPU_FA526
 148         bool
 149         select CPU_32v4
 150         select CPU_ABRT_EV4
 151         select CPU_CACHE_FA
 152         select CPU_CACHE_VIVT
 153         select CPU_COPY_FA if MMU
 154         select CPU_CP15_MMU
 155         select CPU_PABRT_LEGACY
 156         select CPU_TLB_FA if MMU
 157         help
 158           The FA526 is a version of the ARMv4 compatible processor with
 159           Branch Target Buffer, Unified TLB and cache line size 16.
 160
 161           Say Y if you want support for the FA526 processor.
 162           Otherwise, say N.
 163
 164 # ARM940T
 165 config CPU_ARM940T
 166         bool "Support ARM940T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
 167         depends on !MMU
 168         select CPU_32v4T
 169         select CPU_ABRT_NOMMU
 170         select CPU_CACHE_VIVT
 171         select CPU_CP15_MPU
 172         select CPU_PABRT_LEGACY
 173         help
 174           ARM940T is a member of the ARM9TDMI family of general-
 175           purpose microprocessors with MPU and separate 4KB
 176           instruction and 4KB data cases, each with a 4-word line
 177           length.
 178
 179           Say Y if you want support for the ARM940T processor.
 180           Otherwise, say N.
 181
 182 # ARM946E-S
 183 config CPU_ARM946E
 184         bool "Support ARM946E-S processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
 185         depends on !MMU
 186         select CPU_32v5
 187         select CPU_ABRT_NOMMU
 188         select CPU_CACHE_VIVT
 189         select CPU_CP15_MPU
 190         select CPU_PABRT_LEGACY
 191         help
 192           ARM946E-S is a member of the ARM9E-S family of high-
 193           performance, 32-bit system-on-chip processor solutions.
 194           The TCM and ARMv5TE 32-bit instruction set is supported.
 195
 196           Say Y if you want support for the ARM946E-S processor.
 197           Otherwise, say N.
 198
 199 # ARM1020 - needs validating
 200 config CPU_ARM1020
 201         bool "Support ARM1020T (rev 0) processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
 202         select CPU_32v5
 203         select CPU_ABRT_EV4T
 204         select CPU_CACHE_V4WT
 205         select CPU_CACHE_VIVT
 206         select CPU_COPY_V4WB if MMU
 207         select CPU_CP15_MMU
 208         select CPU_PABRT_LEGACY
 209         select CPU_TLB_V4WBI if MMU
 210         help
 211           The ARM1020 is the 32K cached version of the ARM10 processor,
 212           with an addition of a floating-point unit.
 213
 214           Say Y if you want support for the ARM1020 processor.
 215           Otherwise, say N.
 216
 217 # ARM1020E - needs validating
 218 config CPU_ARM1020E
 219         bool "Support ARM1020E processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
 220         depends on n
 221         select CPU_32v5
 222         select CPU_ABRT_EV4T
 223         select CPU_CACHE_V4WT
 224         select CPU_CACHE_VIVT
 225         select CPU_COPY_V4WB if MMU
 226         select CPU_CP15_MMU
 227         select CPU_PABRT_LEGACY
 228         select CPU_TLB_V4WBI if MMU
 229
 230 # ARM1022E
 231 config CPU_ARM1022
 232         bool "Support ARM1022E processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
 233         select CPU_32v5
 234         select CPU_ABRT_EV4T
 235         select CPU_CACHE_VIVT
 236         select CPU_COPY_V4WB if MMU # can probably do better
 237         select CPU_CP15_MMU
 238         select CPU_PABRT_LEGACY
 239         select CPU_TLB_V4WBI if MMU
 240         help
 241           The ARM1022E is an implementation of the ARMv5TE architecture
 242           based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
 243           embedded trace macrocell, and a floating-point unit.
 244
 245           Say Y if you want support for the ARM1022E processor.
 246           Otherwise, say N.
 247
 248 # ARM1026EJ-S
 249 config CPU_ARM1026
 250         bool "Support ARM1026EJ-S processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
 251         select CPU_32v5
 252         select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
 253         select CPU_CACHE_VIVT
 254         select CPU_COPY_V4WB if MMU # can probably do better
 255         select CPU_CP15_MMU
 256         select CPU_PABRT_LEGACY
 257         select CPU_TLB_V4WBI if MMU
 258         help
 259           The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
 260           based upon the ARM10 integer core.
 261
 262           Say Y if you want support for the ARM1026EJ-S processor.
 263           Otherwise, say N.
 264
 265 # SA110
 266 config CPU_SA110
 267         bool
 268         select CPU_32v3 if ARCH_RPC
 269         select CPU_32v4 if !ARCH_RPC
 270         select CPU_ABRT_EV4
 271         select CPU_CACHE_V4WB
 272         select CPU_CACHE_VIVT
 273         select CPU_COPY_V4WB if MMU
 274         select CPU_CP15_MMU
 275         select CPU_PABRT_LEGACY
 276         select CPU_TLB_V4WB if MMU
 277         help
 278           The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
 279           is available at five speeds ranging from 100 MHz to 233 MHz.
 280           More information is available at
 281           <http://developer.intel.com/design/strong/sa110.htm>.
 282
 283           Say Y if you want support for the SA-110 processor.
 284           Otherwise, say N.
 285
 286 # SA1100
 287 config CPU_SA1100
 288         bool
 289         select CPU_32v4
 290         select CPU_ABRT_EV4
 291         select CPU_CACHE_V4WB
 292         select CPU_CACHE_VIVT
 293         select CPU_CP15_MMU
 294         select CPU_PABRT_LEGACY
 295         select CPU_TLB_V4WB if MMU
 296
 297 # XScale
 298 config CPU_XSCALE
 299         bool
 300         select CPU_32v5
 301         select CPU_ABRT_EV5T
 302         select CPU_CACHE_VIVT
 303         select CPU_CP15_MMU
 304         select CPU_PABRT_LEGACY
 305         select CPU_TLB_V4WBI if MMU
 306
 307 # XScale Core Version 3
 308 config CPU_XSC3
 309         bool
 310         select CPU_32v5
 311         select CPU_ABRT_EV5T
 312         select CPU_CACHE_VIVT
 313         select CPU_CP15_MMU
 314         select CPU_PABRT_LEGACY
 315         select CPU_TLB_V4WBI if MMU
 316         select IO_36
 317
 318 # Marvell PJ1 (Mohawk)
 319 config CPU_MOHAWK
 320         bool
 321         select CPU_32v5
 322         select CPU_ABRT_EV5T
 323         select CPU_CACHE_VIVT
 324         select CPU_COPY_V4WB if MMU
 325         select CPU_CP15_MMU
 326         select CPU_PABRT_LEGACY
 327         select CPU_TLB_V4WBI if MMU
 328
 329 # Feroceon
 330 config CPU_FEROCEON
 331         bool
 332         select CPU_32v5
 333         select CPU_ABRT_EV5T
 334         select CPU_CACHE_VIVT
 335         select CPU_COPY_FEROCEON if MMU
 336         select CPU_CP15_MMU
 337         select CPU_PABRT_LEGACY
 338         select CPU_TLB_FEROCEON if MMU
 339
 340 config CPU_FEROCEON_OLD_ID
 341         bool "Accept early Feroceon cores with an ARM926 ID"
 342         depends on CPU_FEROCEON && !CPU_ARM926T
 343         default y
 344         help
 345           This enables the usage of some old Feroceon cores
 346           for which the CPU ID is equal to the ARM926 ID.
 347           Relevant for Feroceon-1850 and early Feroceon-2850.
 348
 349 # Marvell PJ4
 350 config CPU_PJ4
 351         bool
 352         select ARM_THUMBEE
 353         select CPU_V7
 354
 355 config CPU_PJ4B
 356         bool
 357         select CPU_V7
 358
 359 # ARMv6
 360 config CPU_V6
 361         bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
 362         select CPU_32v6
 363         select CPU_ABRT_EV6
 364         select CPU_CACHE_V6
 365         select CPU_CACHE_VIPT
 366         select CPU_COPY_V6 if MMU
 367         select CPU_CP15_MMU
 368         select CPU_HAS_ASID if MMU
 369         select CPU_PABRT_V6
 370         select CPU_TLB_V6 if MMU
 371
 372 # ARMv6k
 373 config CPU_V6K
 374         bool "Support ARM V6K processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
 375         select CPU_32v6
 376         select CPU_32v6K
 377         select CPU_ABRT_EV6
 378         select CPU_CACHE_V6
 379         select CPU_CACHE_VIPT
 380         select CPU_COPY_V6 if MMU
 381         select CPU_CP15_MMU
 382         select CPU_HAS_ASID if MMU
 383         select CPU_PABRT_V6
 384         select CPU_TLB_V6 if MMU
 385
 386 # ARMv7
 387 config CPU_V7
 388         bool "Support ARM V7 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V7) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
 389         select CPU_32v6K
 390         select CPU_32v7
 391         select CPU_ABRT_EV7
 392         select CPU_CACHE_V7
 393         select CPU_CACHE_VIPT
 394         select CPU_COPY_V6 if MMU
 395         select CPU_CP15_MMU if MMU
 396         select CPU_CP15_MPU if !MMU
 397         select CPU_HAS_ASID if MMU
 398         select CPU_PABRT_V7
 399         select CPU_TLB_V7 if MMU
 400
 401 # ARMv7M
 402 config CPU_V7M
 403         bool
 404         select CPU_32v7M
 405         select CPU_ABRT_NOMMU
 406         select CPU_CACHE_NOP
 407         select CPU_PABRT_LEGACY
 408         select CPU_THUMBONLY
 409
 410 config CPU_THUMBONLY
 411         bool
 412         # There are no CPUs available with MMU that don't implement an ARM ISA:
 413         depends on !MMU
 414         help
 415           Select this if your CPU doesn't support the 32 bit ARM instructions.
 416
 417 # Figure out what processor architecture version we should be using.
 418 # This defines the compiler instruction set which depends on the machine type.
 419 config CPU_32v3
 420         bool
 421         select CPU_USE_DOMAINS if MMU
 422         select NEED_KUSER_HELPERS
 423         select TLS_REG_EMUL if SMP || !MMU
 424
 425 config CPU_32v4
 426         bool
 427         select CPU_USE_DOMAINS if MMU
 428         select NEED_KUSER_HELPERS
 429         select TLS_REG_EMUL if SMP || !MMU
 430
 431 config CPU_32v4T
 432         bool
 433         select CPU_USE_DOMAINS if MMU
 434         select NEED_KUSER_HELPERS
 435         select TLS_REG_EMUL if SMP || !MMU
 436
 437 config CPU_32v5
 438         bool
 439         select CPU_USE_DOMAINS if MMU
 440         select NEED_KUSER_HELPERS
 441         select TLS_REG_EMUL if SMP || !MMU
 442
 443 config CPU_32v6
 444         bool
 445         select TLS_REG_EMUL if !CPU_32v6K && !MMU
 446
 447 config CPU_32v6K
 448         bool
 449
 450 config CPU_32v7
 451         bool
 452
 453 config CPU_32v7M
 454         bool
 455
 456 # The abort model
 457 config CPU_ABRT_NOMMU
 458         bool
 459
 460 config CPU_ABRT_EV4
 461         bool
 462
 463 config CPU_ABRT_EV4T
 464         bool
 465
 466 config CPU_ABRT_LV4T
 467         bool
 468
 469 config CPU_ABRT_EV5T
 470         bool
 471
 472 config CPU_ABRT_EV5TJ
 473         bool
 474
 475 config CPU_ABRT_EV6
 476         bool
 477
 478 config CPU_ABRT_EV7
 479         bool
 480
 481 config CPU_PABRT_LEGACY
 482         bool
 483
 484 config CPU_PABRT_V6
 485         bool
 486
 487 config CPU_PABRT_V7
 488         bool
 489
 490 # The cache model
 491 config CPU_CACHE_V4
 492         bool
 493
 494 config CPU_CACHE_V4WT
 495         bool
 496
 497 config CPU_CACHE_V4WB
 498         bool
 499
 500 config CPU_CACHE_V6
 501         bool
 502
 503 config CPU_CACHE_V7
 504         bool
 505
 506 config CPU_CACHE_NOP
 507         bool
 508
 509 config CPU_CACHE_VIVT
 510         bool
 511
 512 config CPU_CACHE_VIPT
 513         bool
 514
 515 config CPU_CACHE_FA
 516         bool
 517
 518 if MMU
 519 # The copy-page model
 520 config CPU_COPY_V4WT
 521         bool
 522
 523 config CPU_COPY_V4WB
 524         bool
 525
 526 config CPU_COPY_FEROCEON
 527         bool
 528
 529 config CPU_COPY_FA
 530         bool
 531
 532 config CPU_COPY_V6
 533         bool
 534
 535 # This selects the TLB model
 536 config CPU_TLB_V4WT
 537         bool
 538         help
 539           ARM Architecture Version 4 TLB with writethrough cache.
 540
 541 config CPU_TLB_V4WB
 542         bool
 543         help
 544           ARM Architecture Version 4 TLB with writeback cache.
 545
 546 config CPU_TLB_V4WBI
 547         bool
 548         help
 549           ARM Architecture Version 4 TLB with writeback cache and invalidate
 550           instruction cache entry.
 551
 552 config CPU_TLB_FEROCEON
 553         bool
 554         help
 555           Feroceon TLB (v4wbi with non-outer-cachable page table walks).
 556
 557 config CPU_TLB_FA
 558         bool
 559         help
 560           Faraday ARM FA526 architecture, unified TLB with writeback cache
 561           and invalidate instruction cache entry. Branch target buffer is
 562           also supported.
 563
 564 config CPU_TLB_V6
 565         bool
 566
 567 config CPU_TLB_V7
 568         bool
 569
 570 config VERIFY_PERMISSION_FAULT
 571         bool
 572 endif
 573
 574 config CPU_HAS_ASID
 575         bool
 576         help
 577           This indicates whether the CPU has the ASID register; used to
 578           tag TLB and possibly cache entries.
 579
 580 config CPU_CP15
 581         bool
 582         help
 583           Processor has the CP15 register.
 584
 585 config CPU_CP15_MMU
 586         bool
 587         select CPU_CP15
 588         help
 589           Processor has the CP15 register, which has MMU related registers.
 590
 591 config CPU_CP15_MPU
 592         bool
 593         select CPU_CP15
 594         help
 595           Processor has the CP15 register, which has MPU related registers.
 596
 597 config CPU_USE_DOMAINS
 598         bool
 599         help
 600           This option enables or disables the use of domain switching
 601           via the set_fs() function.
 602
 603 config CPU_V7M_NUM_IRQ
 604         int "Number of external interrupts connected to the NVIC"
 605         depends on CPU_V7M
 606         default 90 if ARCH_STM32
 607         default 38 if ARCH_EFM32
 608         default 112 if SOC_VF610
 609         default 240
 610         help
 611           This option indicates the number of interrupts connected to the NVIC.
 612           The value can be larger than the real number of interrupts supported
 613           by the system, but must not be lower.
 614           The default value is 240, corresponding to the maximum number of
 615           interrupts supported by the NVIC on Cortex-M family.
 616
 617           If unsure, keep default value.
 618
 619 #
 620 # CPU supports 36-bit I/O
 621 #
 622 config IO_36
 623         bool
 624
 625 comment "Processor Features"
 626
 627 config ARM_LPAE
 628         bool "Support for the Large Physical Address Extension"
 629         depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
 630                 !CPU_32v4 && !CPU_32v3
 631         help
 632           Say Y if you have an ARMv7 processor supporting the LPAE page
 633           table format and you would like to access memory beyond the
 634           4GB limit. The resulting kernel image will not run on
 635           processors without the LPA extension.
 636
 637           If unsure, say N.
 638
 639 config ARM_PV_FIXUP
 640         def_bool y
 641         depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE
 642
 643 config ARCH_PHYS_ADDR_T_64BIT
 644         def_bool ARM_LPAE
 645
 646 config ARCH_DMA_ADDR_T_64BIT
 647         bool
 648
 649 config ARM_THUMB
 650         bool "Support Thumb user binaries" if !CPU_THUMBONLY
 651         depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \
 652                 CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \
 653                 CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
 654                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \
 655                 CPU_V7 || CPU_FEROCEON || CPU_V7M
 656         default y
 657         help
 658           Say Y if you want to include kernel support for running user space
 659           Thumb binaries.
 660
 661           The Thumb instruction set is a compressed form of the standard ARM
 662           instruction set resulting in smaller binaries at the expense of
 663           slightly less efficient code.
 664
 665           If you don't know what this all is, saying Y is a safe choice.
 666
 667 config ARM_THUMBEE
 668         bool "Enable ThumbEE CPU extension"
 669         depends on CPU_V7
 670         help
 671           Say Y here if you have a CPU with the ThumbEE extension and code to
 672           make use of it. Say N for code that can run on CPUs without ThumbEE.
 673
 674 config ARM_VIRT_EXT
 675         bool
 676         depends on MMU
 677         default y if CPU_V7
 678         help
 679           Enable the kernel to make use of the ARM Virtualization
 680           Extensions to install hypervisors without run-time firmware
 681           assistance.
 682
 683           A compliant bootloader is required in order to make maximum
 684           use of this feature.  Refer to Documentation/arm/Booting for
 685           details.
 686
 687 config SWP_EMULATE
 688         bool "Emulate SWP/SWPB instructions" if !SMP
 689         depends on CPU_V7
 690         default y if SMP
 691         select HAVE_PROC_CPU if PROC_FS
 692         help
 693           ARMv6 architecture deprecates use of the SWP/SWPB instructions.
 694           ARMv7 multiprocessing extensions introduce the ability to disable
 695           these instructions, triggering an undefined instruction exception
 696           when executed. Say Y here to enable software emulation of these
 697           instructions for userspace (not kernel) using LDREX/STREX.
 698           Also creates /proc/cpu/swp_emulation for statistics.
 699
 700           In some older versions of glibc [<=2.8] SWP is used during futex
 701           trylock() operations with the assumption that the code will not
 702           be preempted. This invalid assumption may be more likely to fail
 703           with SWP emulation enabled, leading to deadlock of the user
 704           application.
 705
 706           NOTE: when accessing uncached shared regions, LDREX/STREX rely
 707           on an external transaction monitoring block called a global
 708           monitor to maintain update atomicity. If your system does not
 709           implement a global monitor, this option can cause programs that
 710           perform SWP operations to uncached memory to deadlock.
 711
 712           If unsure, say Y.
 713
 714 config CPU_BIG_ENDIAN
 715         bool "Build big-endian kernel"
 716         depends on ARCH_SUPPORTS_BIG_ENDIAN
 717         help
 718           Say Y if you plan on running a kernel in big-endian mode.
 719           Note that your board must be properly built and your board
 720           port must properly enable any big-endian related features
 721           of your chipset/board/processor.
 722
 723 config CPU_ENDIAN_BE8
 724         bool
 725         depends on CPU_BIG_ENDIAN
 726         default CPU_V6 || CPU_V6K || CPU_V7
 727         help
 728           Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
 729
 730 config CPU_ENDIAN_BE32
 731         bool
 732         depends on CPU_BIG_ENDIAN
 733         default !CPU_ENDIAN_BE8
 734         help
 735           Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
 736
 737 config CPU_HIGH_VECTOR
 738         depends on !MMU && CPU_CP15 && !CPU_ARM740T
 739         bool "Select the High exception vector"
 740         help
 741           Say Y here to select high exception vector(0xFFFF0000~).
 742           The exception vector can vary depending on the platform
 743           design in nommu mode. If your platform needs to select
 744           high exception vector, say Y.
 745           Otherwise or if you are unsure, say N, and the low exception
 746           vector (0x00000000~) will be used.
 747
 748 config CPU_ICACHE_DISABLE
 749         bool "Disable I-Cache (I-bit)"
 750         depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
 751         help
 752           Say Y here to disable the processor instruction cache. Unless
 753           you have a reason not to or are unsure, say N.
 754
 755 config CPU_DCACHE_DISABLE
 756         bool "Disable D-Cache (C-bit)"
 757         depends on CPU_CP15 && !SMP
 758         help
 759           Say Y here to disable the processor data cache. Unless
 760           you have a reason not to or are unsure, say N.
 761
 762 config CPU_DCACHE_SIZE
 763         hex
 764         depends on CPU_ARM740T || CPU_ARM946E
 765         default 0x00001000 if CPU_ARM740T
 766         default 0x00002000 # default size for ARM946E-S
 767         help
 768           Some cores are synthesizable to have various sized cache. For
 769           ARM946E-S case, it can vary from 0KB to 1MB.
 770           To support such cache operations, it is efficient to know the size
 771           before compile time.
 772           If your SoC is configured to have a different size, define the value
 773           here with proper conditions.
 774
 775 config CPU_DCACHE_WRITETHROUGH
 776         bool "Force write through D-cache"
 777         depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
 778         default y if CPU_ARM925T
 779         help
 780           Say Y here to use the data cache in writethrough mode. Unless you
 781           specifically require this or are unsure, say N.
 782
 783 config CPU_CACHE_ROUND_ROBIN
 784         bool "Round robin I and D cache replacement algorithm"
 785         depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
 786         help
 787           Say Y here to use the predictable round-robin cache replacement
 788           policy.  Unless you specifically require this or are unsure, say N.
 789
 790 config CPU_BPREDICT_DISABLE
 791         bool "Disable branch prediction"
 792         depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
 793         help
 794           Say Y here to disable branch prediction.  If unsure, say N.
 795
 796 config TLS_REG_EMUL
 797         bool
 798         select NEED_KUSER_HELPERS
 799         help
 800           An SMP system using a pre-ARMv6 processor (there are apparently
 801           a few prototypes like that in existence) and therefore access to
 802           that required register must be emulated.
 803
 804 config NEED_KUSER_HELPERS
 805         bool
 806
 807 config KUSER_HELPERS
 808         bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS
 809         depends on MMU
 810         default y
 811         help
 812           Warning: disabling this option may break user programs.
 813
 814           Provide kuser helpers in the vector page.  The kernel provides
 815           helper code to userspace in read only form at a fixed location
 816           in the high vector page to allow userspace to be independent of
 817           the CPU type fitted to the system.  This permits binaries to be
 818           run on ARMv4 through to ARMv7 without modification.
 819
 820           See Documentation/arm/kernel_user_helpers.txt for details.
 821
 822           However, the fixed address nature of these helpers can be used
 823           by ROP (return orientated programming) authors when creating
 824           exploits.
 825
 826           If all of the binaries and libraries which run on your platform
 827           are built specifically for your platform, and make no use of
 828           these helpers, then you can turn this option off to hinder
 829           such exploits. However, in that case, if a binary or library
 830           relying on those helpers is run, it will receive a SIGILL signal,
 831           which will terminate the program.
 832
 833           Say N here only if you are absolutely certain that you do not
 834           need these helpers; otherwise, the safe option is to say Y.
 835
 836 config VDSO
 837         bool "Enable VDSO for acceleration of some system calls"
 838         depends on AEABI && MMU && CPU_V7
 839         default y if ARM_ARCH_TIMER
 840         select GENERIC_TIME_VSYSCALL
 841         help
 842           Place in the process address space an ELF shared object
 843           providing fast implementations of gettimeofday and
 844           clock_gettime.  Systems that implement the ARM architected
 845           timer will receive maximum benefit.
 846
 847           You must have glibc 2.22 or later for programs to seamlessly
 848           take advantage of this.
 849
 850 config DMA_CACHE_RWFO
 851         bool "Enable read/write for ownership DMA cache maintenance"
 852         depends on CPU_V6K && SMP
 853         default y
 854         help
 855           The Snoop Control Unit on ARM11MPCore does not detect the
 856           cache maintenance operations and the dma_{map,unmap}_area()
 857           functions may leave stale cache entries on other CPUs. By
 858           enabling this option, Read or Write For Ownership in the ARMv6
 859           DMA cache maintenance functions is performed. These LDR/STR
 860           instructions change the cache line state to shared or modified
 861           so that the cache operation has the desired effect.
 862
 863           Note that the workaround is only valid on processors that do
 864           not perform speculative loads into the D-cache. For such
 865           processors, if cache maintenance operations are not broadcast
 866           in hardware, other workarounds are needed (e.g. cache
 867           maintenance broadcasting in software via FIQ).
 868
 869 config OUTER_CACHE
 870         bool
 871
 872 config OUTER_CACHE_SYNC
 873         bool
 874         select ARM_HEAVY_MB
 875         help
 876           The outer cache has a outer_cache_fns.sync function pointer
 877           that can be used to drain the write buffer of the outer cache.
 878
 879 config CACHE_FEROCEON_L2
 880         bool "Enable the Feroceon L2 cache controller"
 881         depends on ARCH_MV78XX0 || ARCH_MVEBU
 882         default y
 883         select OUTER_CACHE
 884         help
 885           This option enables the Feroceon L2 cache controller.
 886
 887 config CACHE_FEROCEON_L2_WRITETHROUGH
 888         bool "Force Feroceon L2 cache write through"
 889         depends on CACHE_FEROCEON_L2
 890         help
 891           Say Y here to use the Feroceon L2 cache in writethrough mode.
 892           Unless you specifically require this, say N for writeback mode.
 893
 894 config MIGHT_HAVE_CACHE_L2X0
 895         bool
 896         help
 897           This option should be selected by machines which have a L2x0
 898           or PL310 cache controller, but where its use is optional.
 899
 900           The only effect of this option is to make CACHE_L2X0 and
 901           related options available to the user for configuration.
 902
 903           Boards or SoCs which always require the cache controller
 904           support to be present should select CACHE_L2X0 directly
 905           instead of this option, thus preventing the user from
 906           inadvertently configuring a broken kernel.
 907
 908 config CACHE_L2X0
 909         bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
 910         default MIGHT_HAVE_CACHE_L2X0
 911         select OUTER_CACHE
 912         select OUTER_CACHE_SYNC
 913         help
 914           This option enables the L2x0 PrimeCell.
 915
 916 if CACHE_L2X0
 917
 918 config PL310_ERRATA_588369
 919         bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
 920         help
 921            The PL310 L2 cache controller implements three types of Clean &
 922            Invalidate maintenance operations: by Physical Address
 923            (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
 924            They are architecturally defined to behave as the execution of a
 925            clean operation followed immediately by an invalidate operation,
 926            both performing to the same memory location. This functionality
 927            is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
 928            as clean lines are not invalidated as a result of these operations.
 929
 930 config PL310_ERRATA_727915
 931         bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
 932         help
 933           PL310 implements the Clean & Invalidate by Way L2 cache maintenance
 934           operation (offset 0x7FC). This operation runs in background so that
 935           PL310 can handle normal accesses while it is in progress. Under very
 936           rare circumstances, due to this erratum, write data can be lost when
 937           PL310 treats a cacheable write transaction during a Clean &
 938           Invalidate by Way operation.  Revisions prior to r3p1 are affected by
 939           this errata (fixed in r3p1).
 940
 941 config PL310_ERRATA_753970
 942         bool "PL310 errata: cache sync operation may be faulty"
 943         help
 944           This option enables the workaround for the 753970 PL310 (r3p0) erratum.
 945
 946           Under some condition the effect of cache sync operation on
 947           the store buffer still remains when the operation completes.
 948           This means that the store buffer is always asked to drain and
 949           this prevents it from merging any further writes. The workaround
 950           is to replace the normal offset of cache sync operation (0x730)
 951           by another offset targeting an unmapped PL310 register 0x740.
 952           This has the same effect as the cache sync operation: store buffer
 953           drain and waiting for all buffers empty.
 954
 955 config PL310_ERRATA_769419
 956         bool "PL310 errata: no automatic Store Buffer drain"
 957         help
 958           On revisions of the PL310 prior to r3p2, the Store Buffer does
 959           not automatically drain. This can cause normal, non-cacheable
 960           writes to be retained when the memory system is idle, leading
 961           to suboptimal I/O performance for drivers using coherent DMA.
 962           This option adds a write barrier to the cpu_idle loop so that,
 963           on systems with an outer cache, the store buffer is drained
 964           explicitly.
 965
 966 endif
 967
 968 config CACHE_TAUROS2
 969         bool "Enable the Tauros2 L2 cache controller"
 970         depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
 971         default y
 972         select OUTER_CACHE
 973         help
 974           This option enables the Tauros2 L2 cache controller (as
 975           found on PJ1/PJ4).
 976
 977 config CACHE_UNIPHIER
 978         bool "Enable the UniPhier outer cache controller"
 979         depends on ARCH_UNIPHIER
 980         default y
 981         select OUTER_CACHE
 982         select OUTER_CACHE_SYNC
 983         help
 984           This option enables the UniPhier outer cache (system cache)
 985           controller.
 986
 987 config CACHE_XSC3L2
 988         bool "Enable the L2 cache on XScale3"
 989         depends on CPU_XSC3
 990         default y
 991         select OUTER_CACHE
 992         help
 993           This option enables the L2 cache on XScale3.
 994
 995 config ARM_L1_CACHE_SHIFT_6
 996         bool
 997         default y if CPU_V7
 998         help
 999           Setting ARM L1 cache line size to 64 Bytes.
1000
1001 config ARM_L1_CACHE_SHIFT
1002         int
1003         default 6 if ARM_L1_CACHE_SHIFT_6
1004         default 5
1005
1006 config ARM_DMA_MEM_BUFFERABLE
1007         bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
1008         depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
1009                      MACH_REALVIEW_PB11MP)
1010         default y if CPU_V6 || CPU_V6K || CPU_V7
1011         help
1012           Historically, the kernel has used strongly ordered mappings to
1013           provide DMA coherent memory.  With the advent of ARMv7, mapping
1014           memory with differing types results in unpredictable behaviour,
1015           so on these CPUs, this option is forced on.
1016
1017           Multiple mappings with differing attributes is also unpredictable
1018           on ARMv6 CPUs, but since they do not have aggressive speculative
1019           prefetch, no harm appears to occur.
1020
1021           However, drivers may be missing the necessary barriers for ARMv6,
1022           and therefore turning this on may result in unpredictable driver
1023           behaviour.  Therefore, we offer this as an option.
1024
1025           You are recommended say 'Y' here and debug any affected drivers.
1026
1027 config ARCH_HAS_BARRIERS
1028         bool
1029         help
1030           This option allows the use of custom mandatory barriers
1031           included via the mach/barriers.h file.
1032
1033 config ARM_HEAVY_MB
1034         bool
1035
1036 config ARCH_SUPPORTS_BIG_ENDIAN
1037         bool
1038         help
1039           This option specifies the architecture can support big endian
1040           operation.
1041
1042 config ARM_KERNMEM_PERMS
1043         bool "Restrict kernel memory permissions"
1044         depends on MMU
1045         help
1046           If this is set, kernel memory other than kernel text (and rodata)
1047           will be made non-executable. The tradeoff is that each region is
1048           padded to section-size (1MiB) boundaries (because their permissions
1049           are different and splitting the 1M pages into 4K ones causes TLB
1050           performance problems), wasting memory.
1051
1052 config DEBUG_RODATA
1053         bool "Make kernel text and rodata read-only"
1054         depends on ARM_KERNMEM_PERMS
1055         default y
1056         help
1057           If this is set, kernel text and rodata will be made read-only. This
1058           is to help catch accidental or malicious attempts to change the
1059           kernel's executable code. Additionally splits rodata from kernel
1060           text so it can be made explicitly non-executable. This creates
1061           another section-size padded region, so it can waste more memory
1062           space while gaining the read-only protections.