arch/arm/mm/flush.c

   1 /*
   2  *  linux/arch/arm/mm/flush.c
   3  *
   4  *  Copyright (C) 1995-2002 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/module.h>
  11 #include <linux/mm.h>
  12 #include <linux/pagemap.h>
  13
  14 #include <asm/cacheflush.h>
  15 #include <asm/cachetype.h>
  16 #include <asm/system.h>
  17 #include <asm/tlbflush.h>
  18
  19 #include "mm.h"
  20
  21 #ifdef CONFIG_CPU_CACHE_VIPT
  22
  23 #define ALIAS_FLUSH_START       0xffff4000
  24
  25 static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr)
  26 {
  27         unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT);
  28         const int zero = 0;
  29
  30         set_pte_ext(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL), 0);
  31         flush_tlb_kernel_page(to);
  32
  33         asm(    "mcrr   p15, 0, %1, %0, c14\n"
  34         "       mcr     p15, 0, %2, c7, c10, 4"
  35             :
  36             : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero)
  37             : "cc");
  38 }
  39
  40 void flush_cache_mm(struct mm_struct *mm)
  41 {
  42         if (cache_is_vivt()) {
  43                 vivt_flush_cache_mm(mm);
  44                 return;
  45         }
  46
  47         if (cache_is_vipt_aliasing()) {
  48                 asm(    "mcr    p15, 0, %0, c7, c14, 0\n"
  49                 "       mcr     p15, 0, %0, c7, c10, 4"
  50                     :
  51                     : "r" (0)
  52                     : "cc");
  53                 __flush_icache_all();
  54         }
  55 }
  56
  57 void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
  58 {
  59         if (cache_is_vivt()) {
  60                 vivt_flush_cache_range(vma, start, end);
  61                 return;
  62         }
  63
  64         if (cache_is_vipt_aliasing()) {
  65                 asm(    "mcr    p15, 0, %0, c7, c14, 0\n"
  66                 "       mcr     p15, 0, %0, c7, c10, 4"
  67                     :
  68                     : "r" (0)
  69                     : "cc");
  70                 __flush_icache_all();
  71         }
  72
  73         if (vma->vm_flags & VM_EXEC && icache_is_vivt_asid_tagged())
  74                 __flush_icache_all();
  75 }
  76
  77 void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
  78 {
  79         if (cache_is_vivt()) {
  80                 vivt_flush_cache_page(vma, user_addr, pfn);
  81                 return;
  82         }
  83
  84         if (cache_is_vipt_aliasing()) {
  85                 flush_pfn_alias(pfn, user_addr);
  86                 __flush_icache_all();
  87         }
  88
  89         if (vma->vm_flags & VM_EXEC && icache_is_vivt_asid_tagged())
  90                 __flush_icache_all();
  91 }
  92
  93 void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
  94                          unsigned long uaddr, void *kaddr,
  95                          unsigned long len, int write)
  96 {
  97         if (cache_is_vivt()) {
  98                 vivt_flush_ptrace_access(vma, page, uaddr, kaddr, len, write);
  99                 return;
 100         }
 101
 102         if (cache_is_vipt_aliasing()) {
 103                 flush_pfn_alias(page_to_pfn(page), uaddr);
 104                 __flush_icache_all();
 105                 return;
 106         }
 107
 108         /* VIPT non-aliasing cache */
 109         if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm)) &&
 110             vma->vm_flags & VM_EXEC) {
 111                 unsigned long addr = (unsigned long)kaddr;
 112                 /* only flushing the kernel mapping on non-aliasing VIPT */
 113                 __cpuc_coherent_kern_range(addr, addr + len);
 114         }
 115 }
 116 #else
 117 #define flush_pfn_alias(pfn,vaddr)      do { } while (0)
 118 #endif
 119
 120 void __flush_dcache_page(struct address_space *mapping, struct page *page)
 121 {
 122         void *addr = page_address(page);
 123
 124         /*
 125          * Writeback any data associated with the kernel mapping of this
 126          * page.  This ensures that data in the physical page is mutually
 127          * coherent with the kernels mapping.
 128          */
 129 #ifdef CONFIG_HIGHMEM
 130         /*
 131          * kmap_atomic() doesn't set the page virtual address, and
 132          * kunmap_atomic() takes care of cache flushing already.
 133          */
 134         if (addr)
 135 #endif
 136                 __cpuc_flush_dcache_page(addr);
 137
 138         /*
 139          * If this is a page cache page, and we have an aliasing VIPT cache,
 140          * we only need to do one flush - which would be at the relevant
 141          * userspace colour, which is congruent with page->index.
 142          */
 143         if (mapping && cache_is_vipt_aliasing())
 144                 flush_pfn_alias(page_to_pfn(page),
 145                                 page->index << PAGE_CACHE_SHIFT);
 146 }
 147
 148 static void __flush_dcache_aliases(struct address_space *mapping, struct page *page)
 149 {
 150         struct mm_struct *mm = current->active_mm;
 151         struct vm_area_struct *mpnt;
 152         struct prio_tree_iter iter;
 153         pgoff_t pgoff;
 154
 155         /*
 156          * There are possible user space mappings of this page:
 157          * - VIVT cache: we need to also write back and invalidate all user
 158          *   data in the current VM view associated with this page.
 159          * - aliasing VIPT: we only need to find one mapping of this page.
 160          */
 161         pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);
 162
 163         flush_dcache_mmap_lock(mapping);
 164         vma_prio_tree_foreach(mpnt, &iter, &mapping->i_mmap, pgoff, pgoff) {
 165                 unsigned long offset;
 166
 167                 /*
 168                  * If this VMA is not in our MM, we can ignore it.
 169                  */
 170                 if (mpnt->vm_mm != mm)
 171                         continue;
 172                 if (!(mpnt->vm_flags & VM_MAYSHARE))
 173                         continue;
 174                 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
 175                 flush_cache_page(mpnt, mpnt->vm_start + offset, page_to_pfn(page));
 176         }
 177         flush_dcache_mmap_unlock(mapping);
 178 }
 179
 180 /*
 181  * Ensure cache coherency between kernel mapping and userspace mapping
 182  * of this page.
 183  *
 184  * We have three cases to consider:
 185  *  - VIPT non-aliasing cache: fully coherent so nothing required.
 186  *  - VIVT: fully aliasing, so we need to handle every alias in our
 187  *          current VM view.
 188  *  - VIPT aliasing: need to handle one alias in our current VM view.
 189  *
 190  * If we need to handle aliasing:
 191  *  If the page only exists in the page cache and there are no user
 192  *  space mappings, we can be lazy and remember that we may have dirty
 193  *  kernel cache lines for later.  Otherwise, we assume we have
 194  *  aliasing mappings.
 195  *
 196  * Note that we disable the lazy flush for SMP.
 197  */
 198 void flush_dcache_page(struct page *page)
 199 {
 200         struct address_space *mapping;
 201
 202         /*
 203          * The zero page is never written to, so never has any dirty
 204          * cache lines, and therefore never needs to be flushed.
 205          */
 206         if (page == ZERO_PAGE(0))
 207                 return;
 208
 209         mapping = page_mapping(page);
 210
 211 #ifndef CONFIG_SMP
 212         if (!PageHighMem(page) && mapping && !mapping_mapped(mapping))
 213                 set_bit(PG_dcache_dirty, &page->flags);
 214         else
 215 #endif
 216         {
 217                 __flush_dcache_page(mapping, page);
 218                 if (mapping && cache_is_vivt())
 219                         __flush_dcache_aliases(mapping, page);
 220                 else if (mapping)
 221                         __flush_icache_all();
 222         }
 223 }
 224 EXPORT_SYMBOL(flush_dcache_page);
 225
 226 /*
 227  * Flush an anonymous page so that users of get_user_pages()
 228  * can safely access the data.  The expected sequence is:
 229  *
 230  *  get_user_pages()
 231  *    -> flush_anon_page
 232  *  memcpy() to/from page
 233  *  if written to page, flush_dcache_page()
 234  */
 235 void __flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr)
 236 {
 237         unsigned long pfn;
 238
 239         /* VIPT non-aliasing caches need do nothing */
 240         if (cache_is_vipt_nonaliasing())
 241                 return;
 242
 243         /*
 244          * Write back and invalidate userspace mapping.
 245          */
 246         pfn = page_to_pfn(page);
 247         if (cache_is_vivt()) {
 248                 flush_cache_page(vma, vmaddr, pfn);
 249         } else {
 250                 /*
 251                  * For aliasing VIPT, we can flush an alias of the
 252                  * userspace address only.
 253                  */
 254                 flush_pfn_alias(pfn, vmaddr);
 255                 __flush_icache_all();
 256         }
 257
 258         /*
 259          * Invalidate kernel mapping.  No data should be contained
 260          * in this mapping of the page.  FIXME: this is overkill
 261          * since we actually ask for a write-back and invalidate.
 262          */
 263         __cpuc_flush_dcache_page(page_address(page));
 264 }