arch/arm/mm/proc-arm1022.S

   1 /*
   2  *  linux/arch/arm/mm/proc-arm1022.S: MMU functions for ARM1022E
   3  *
   4  *  Copyright (C) 2000 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  *
  13  * These are the low level assembler for performing cache and TLB
  14  * functions on the ARM1022E.
  15  */
  16 #include <linux/linkage.h>
  17 #include <linux/config.h>
  18 #include <linux/init.h>
  19 #include <asm/assembler.h>
  20 #include <asm/constants.h>
  21 #include <asm/pgtable.h>
  22 #include <asm/procinfo.h>
  23 #include <asm/ptrace.h>
  24
  25 /*
  26  * This is the maximum size of an area which will be invalidated
  27  * using the single invalidate entry instructions.  Anything larger
  28  * than this, and we go for the whole cache.
  29  *
  30  * This value should be chosen such that we choose the cheapest
  31  * alternative.
  32  */
  33 #define MAX_AREA_SIZE   32768
  34
  35 /*
  36  * The size of one data cache line.
  37  */
  38 #define CACHE_DLINESIZE 32
  39
  40 /*
  41  * The number of data cache segments.
  42  */
  43 #define CACHE_DSEGMENTS 16
  44
  45 /*
  46  * The number of lines in a cache segment.
  47  */
  48 #define CACHE_DENTRIES  64
  49
  50 /*
  51  * This is the size at which it becomes more efficient to
  52  * clean the whole cache, rather than using the individual
  53  * cache line maintainence instructions.
  54  */
  55 #define CACHE_DLIMIT    32768
  56
  57         .text
  58 /*
  59  * cpu_arm1022_proc_init()
  60  */
  61 ENTRY(cpu_arm1022_proc_init)
  62         mov     pc, lr
  63
  64 /*
  65  * cpu_arm1022_proc_fin()
  66  */
  67 ENTRY(cpu_arm1022_proc_fin)
  68         stmfd   sp!, {lr}
  69         mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
  70         msr     cpsr_c, ip
  71         bl      arm1022_flush_kern_cache_all
  72         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
  73         bic     r0, r0, #0x1000                 @ ...i............
  74         bic     r0, r0, #0x000e                 @ ............wca.
  75         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  76         ldmfd   sp!, {pc}
  77
  78 /*
  79  * cpu_arm1022_reset(loc)
  80  *
  81  * Perform a soft reset of the system.  Put the CPU into the
  82  * same state as it would be if it had been reset, and branch
  83  * to what would be the reset vector.
  84  *
  85  * loc: location to jump to for soft reset
  86  */
  87         .align  5
  88 ENTRY(cpu_arm1022_reset)
  89         mov     ip, #0
  90         mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
  91         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
  92         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
  93         mrc     p15, 0, ip, c1, c0, 0           @ ctrl register
  94         bic     ip, ip, #0x000f                 @ ............wcam
  95         bic     ip, ip, #0x1100                 @ ...i...s........
  96         mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
  97         mov     pc, r0
  98
  99 /*
 100  * cpu_arm1022_do_idle()
 101  */
 102         .align  5
 103 ENTRY(cpu_arm1022_do_idle)
 104         mcr     p15, 0, r0, c7, c0, 4           @ Wait for interrupt
 105         mov     pc, lr
 106
 107 /* ================================= CACHE ================================ */
 108
 109         .align  5
 110 /*
 111  *      flush_user_cache_all()
 112  *
 113  *      Invalidate all cache entries in a particular address
 114  *      space.
 115  */
 116 ENTRY(arm1022_flush_user_cache_all)
 117         /* FALLTHROUGH */
 118 /*
 119  *      flush_kern_cache_all()
 120  *
 121  *      Clean and invalidate the entire cache.
 122  */
 123 ENTRY(arm1022_flush_kern_cache_all)
 124         mov     r2, #VM_EXEC
 125         mov     ip, #0
 126 __flush_whole_cache:
 127 #ifndef CONFIG_CPU_DCACHE_DISABLE
 128         mov     r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
 129 1:      orr     r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
 130 2:      mcr     p15, 0, r3, c7, c14, 2          @ clean+invalidate D index
 131         subs    r3, r3, #1 << 26
 132         bcs     2b                              @ entries 63 to 0
 133         subs    r1, r1, #1 << 5
 134         bcs     1b                              @ segments 15 to 0
 135 #endif
 136         tst     r2, #VM_EXEC
 137 #ifndef CONFIG_CPU_ICACHE_DISABLE
 138         mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
 139 #endif
 140         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
 141         mov     pc, lr
 142
 143 /*
 144  *      flush_user_cache_range(start, end, flags)
 145  *
 146  *      Invalidate a range of cache entries in the specified
 147  *      address space.
 148  *
 149  *      - start - start address (inclusive)
 150  *      - end   - end address (exclusive)
 151  *      - flags - vm_flags for this space
 152  */
 153 ENTRY(arm1022_flush_user_cache_range)
 154         mov     ip, #0
 155         sub     r3, r1, r0                      @ calculate total size
 156         cmp     r3, #CACHE_DLIMIT
 157         bhs     __flush_whole_cache
 158
 159 #ifndef CONFIG_CPU_DCACHE_DISABLE
 160 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 161         add     r0, r0, #CACHE_DLINESIZE
 162         cmp     r0, r1
 163         blo     1b
 164 #endif
 165         tst     r2, #VM_EXEC
 166 #ifndef CONFIG_CPU_ICACHE_DISABLE
 167         mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
 168 #endif
 169         mcrne   p15, 0, ip, c7, c10, 4          @ drain WB
 170         mov     pc, lr
 171
 172 /*
 173  *      coherent_kern_range(start, end)
 174  *
 175  *      Ensure coherency between the Icache and the Dcache in the
 176  *      region described by start.  If you have non-snooping
 177  *      Harvard caches, you need to implement this function.
 178  *
 179  *      - start - virtual start address
 180  *      - end   - virtual end address
 181  */
 182 ENTRY(arm1022_coherent_kern_range)
 183         /* FALLTHROUGH */
 184
 185 /*
 186  *      coherent_user_range(start, end)
 187  *
 188  *      Ensure coherency between the Icache and the Dcache in the
 189  *      region described by start.  If you have non-snooping
 190  *      Harvard caches, you need to implement this function.
 191  *
 192  *      - start - virtual start address
 193  *      - end   - virtual end address
 194  */
 195 ENTRY(arm1022_coherent_user_range)
 196         mov     ip, #0
 197         bic     r0, r0, #CACHE_DLINESIZE - 1
 198 1:
 199 #ifndef CONFIG_CPU_DCACHE_DISABLE
 200         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 201 #endif
 202 #ifndef CONFIG_CPU_ICACHE_DISABLE
 203         mcr     p15, 0, r0, c7, c5, 1           @ invalidate I entry
 204 #endif
 205         add     r0, r0, #CACHE_DLINESIZE
 206         cmp     r0, r1
 207         blo     1b
 208         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 209         mov     pc, lr
 210
 211 /*
 212  *      flush_kern_dcache_page(void *page)
 213  *
 214  *      Ensure no D cache aliasing occurs, either with itself or
 215  *      the I cache
 216  *
 217  *      - page  - page aligned address
 218  */
 219 ENTRY(arm1022_flush_kern_dcache_page)
 220         mov     ip, #0
 221 #ifndef CONFIG_CPU_DCACHE_DISABLE
 222         add     r1, r0, #PAGE_SZ
 223 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 224         add     r0, r0, #CACHE_DLINESIZE
 225         cmp     r0, r1
 226         blo     1b
 227 #endif
 228         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 229         mov     pc, lr
 230
 231 /*
 232  *      dma_inv_range(start, end)
 233  *
 234  *      Invalidate (discard) the specified virtual address range.
 235  *      May not write back any entries.  If 'start' or 'end'
 236  *      are not cache line aligned, those lines must be written
 237  *      back.
 238  *
 239  *      - start - virtual start address
 240  *      - end   - virtual end address
 241  *
 242  * (same as v4wb)
 243  */
 244 ENTRY(arm1022_dma_inv_range)
 245         mov     ip, #0
 246 #ifndef CONFIG_CPU_DCACHE_DISABLE
 247         tst     r0, #CACHE_DLINESIZE - 1
 248         bic     r0, r0, #CACHE_DLINESIZE - 1
 249         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
 250         tst     r1, #CACHE_DLINESIZE - 1
 251         mcrne   p15, 0, r1, c7, c10, 1          @ clean D entry
 252 1:      mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
 253         add     r0, r0, #CACHE_DLINESIZE
 254         cmp     r0, r1
 255         blo     1b
 256 #endif
 257         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 258         mov     pc, lr
 259
 260 /*
 261  *      dma_clean_range(start, end)
 262  *
 263  *      Clean the specified virtual address range.
 264  *
 265  *      - start - virtual start address
 266  *      - end   - virtual end address
 267  *
 268  * (same as v4wb)
 269  */
 270 ENTRY(arm1022_dma_clean_range)
 271         mov     ip, #0
 272 #ifndef CONFIG_CPU_DCACHE_DISABLE
 273         bic     r0, r0, #CACHE_DLINESIZE - 1
 274 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 275         add     r0, r0, #CACHE_DLINESIZE
 276         cmp     r0, r1
 277         blo     1b
 278 #endif
 279         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 280         mov     pc, lr
 281
 282 /*
 283  *      dma_flush_range(start, end)
 284  *
 285  *      Clean and invalidate the specified virtual address range.
 286  *
 287  *      - start - virtual start address
 288  *      - end   - virtual end address
 289  */
 290 ENTRY(arm1022_dma_flush_range)
 291         mov     ip, #0
 292 #ifndef CONFIG_CPU_DCACHE_DISABLE
 293         bic     r0, r0, #CACHE_DLINESIZE - 1
 294 1:      mcr     p15, 0, r0, c7, c14, 1          @ clean+invalidate D entry
 295         add     r0, r0, #CACHE_DLINESIZE
 296         cmp     r0, r1
 297         blo     1b
 298 #endif
 299         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
 300         mov     pc, lr
 301
 302 ENTRY(arm1022_cache_fns)
 303         .long   arm1022_flush_kern_cache_all
 304         .long   arm1022_flush_user_cache_all
 305         .long   arm1022_flush_user_cache_range
 306         .long   arm1022_coherent_kern_range
 307         .long   arm1022_coherent_user_range
 308         .long   arm1022_flush_kern_dcache_page
 309         .long   arm1022_dma_inv_range
 310         .long   arm1022_dma_clean_range
 311         .long   arm1022_dma_flush_range
 312
 313         .align  5
 314 ENTRY(cpu_arm1022_dcache_clean_area)
 315 #ifndef CONFIG_CPU_DCACHE_DISABLE
 316         mov     ip, #0
 317 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 318         add     r0, r0, #CACHE_DLINESIZE
 319         subs    r1, r1, #CACHE_DLINESIZE
 320         bhi     1b
 321 #endif
 322         mov     pc, lr
 323
 324 /* =============================== PageTable ============================== */
 325
 326 /*
 327  * cpu_arm1022_switch_mm(pgd)
 328  *
 329  * Set the translation base pointer to be as described by pgd.
 330  *
 331  * pgd: new page tables
 332  */
 333         .align  5
 334 ENTRY(cpu_arm1022_switch_mm)
 335 #ifndef CONFIG_CPU_DCACHE_DISABLE
 336         mov     r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
 337 1:      orr     r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
 338 2:      mcr     p15, 0, r3, c7, c14, 2          @ clean+invalidate D index
 339         subs    r3, r3, #1 << 26
 340         bcs     2b                              @ entries 63 to 0
 341         subs    r1, r1, #1 << 5
 342         bcs     1b                              @ segments 15 to 0
 343 #endif
 344         mov     r1, #0
 345 #ifndef CONFIG_CPU_ICACHE_DISABLE
 346         mcr     p15, 0, r1, c7, c5, 0           @ invalidate I cache
 347 #endif
 348         mcr     p15, 0, r1, c7, c10, 4          @ drain WB
 349         mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
 350         mcr     p15, 0, r1, c8, c7, 0           @ invalidate I & D TLBs
 351         mov     pc, lr
 352
 353 /*
 354  * cpu_arm1022_set_pte(ptep, pte)
 355  *
 356  * Set a PTE and flush it out
 357  */
 358         .align  5
 359 ENTRY(cpu_arm1022_set_pte)
 360         str     r1, [r0], #-2048                @ linux version
 361
 362         eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
 363
 364         bic     r2, r1, #PTE_SMALL_AP_MASK
 365         bic     r2, r2, #PTE_TYPE_MASK
 366         orr     r2, r2, #PTE_TYPE_SMALL
 367
 368         tst     r1, #L_PTE_USER                 @ User?
 369         orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
 370
 371         tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
 372         orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
 373
 374         tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
 375         movne   r2, #0
 376
 377 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 378         eor     r3, r1, #0x0a                   @ C & small page?
 379         tst     r3, #0x0b
 380         biceq   r2, r2, #4
 381 #endif
 382         str     r2, [r0]                        @ hardware version
 383         mov     r0, r0
 384 #ifndef CONFIG_CPU_DCACHE_DISABLE
 385         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 386 #endif
 387         mov     pc, lr
 388
 389         __INIT
 390
 391         .type   __arm1022_setup, #function
 392 __arm1022_setup:
 393         mov     r0, #0
 394         mcr     p15, 0, r0, c7, c7              @ invalidate I,D caches on v4
 395         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer on v4
 396         mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
 397         mrc     p15, 0, r0, c1, c0              @ get control register v4
 398         ldr     r5, arm1022_cr1_clear
 399         bic     r0, r0, r5
 400         ldr     r5, arm1022_cr1_set
 401         orr     r0, r0, r5
 402 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
 403         orr     r0, r0, #0x4000                 @ .R..............
 404 #endif
 405         mov     pc, lr
 406         .size   __arm1022_setup, . - __arm1022_setup
 407
 408         /*
 409          *  R
 410          * .RVI ZFRS BLDP WCAM
 411          * .011 1001 ..11 0101
 412          *
 413          */
 414         .type   arm1022_cr1_clear, #object
 415         .type   arm1022_cr1_set, #object
 416 arm1022_cr1_clear:
 417         .word   0x7f3f
 418 arm1022_cr1_set:
 419         .word   0x3935
 420
 421         __INITDATA
 422
 423 /*
 424  * Purpose : Function pointers used to access above functions - all calls
 425  *           come through these
 426  */
 427         .type   arm1022_processor_functions, #object
 428 arm1022_processor_functions:
 429         .word   v4t_early_abort
 430         .word   cpu_arm1022_proc_init
 431         .word   cpu_arm1022_proc_fin
 432         .word   cpu_arm1022_reset
 433         .word   cpu_arm1022_do_idle
 434         .word   cpu_arm1022_dcache_clean_area
 435         .word   cpu_arm1022_switch_mm
 436         .word   cpu_arm1022_set_pte
 437         .size   arm1022_processor_functions, . - arm1022_processor_functions
 438
 439         .section ".rodata"
 440
 441         .type   cpu_arch_name, #object
 442 cpu_arch_name:
 443         .asciz  "armv5te"
 444         .size   cpu_arch_name, . - cpu_arch_name
 445
 446         .type   cpu_elf_name, #object
 447 cpu_elf_name:
 448         .asciz  "v5"
 449         .size   cpu_elf_name, . - cpu_elf_name
 450
 451         .type   cpu_arm1022_name, #object
 452 cpu_arm1022_name:
 453         .ascii  "arm1022"
 454 #ifndef CONFIG_CPU_ICACHE_DISABLE
 455         .ascii  "i"
 456 #endif
 457 #ifndef CONFIG_CPU_DCACHE_DISABLE
 458         .ascii  "d"
 459 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 460         .ascii  "(wt)"
 461 #else
 462         .ascii  "(wb)"
 463 #endif
 464 #endif
 465 #ifndef CONFIG_CPU_BPREDICT_DISABLE
 466         .ascii  "B"
 467 #endif
 468 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
 469         .ascii  "RR"
 470 #endif
 471         .ascii  "\0"
 472         .size   cpu_arm1022_name, . - cpu_arm1022_name
 473
 474         .align
 475
 476         .section ".proc.info", #alloc, #execinstr
 477
 478         .type   __arm1022_proc_info,#object
 479 __arm1022_proc_info:
 480         .long   0x4105a220                      @ ARM 1022E (v5TE)
 481         .long   0xff0ffff0
 482         .long   PMD_TYPE_SECT | \
 483                 PMD_BIT4 | \
 484                 PMD_SECT_AP_WRITE | \
 485                 PMD_SECT_AP_READ
 486         b       __arm1022_setup
 487         .long   cpu_arch_name
 488         .long   cpu_elf_name
 489         .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
 490         .long   cpu_arm1022_name
 491         .long   arm1022_processor_functions
 492         .long   v4wbi_tlb_fns
 493         .long   v4wb_user_fns
 494         .long   arm1022_cache_fns
 495         .size   __arm1022_proc_info, . - __arm1022_proc_info