arch/arm/mm/proc-arm740.S

   1 /*
   2  *  linux/arch/arm/mm/arm740.S: utility functions for ARM740
   3  *
   4  *  Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  */
  11 #include <linux/linkage.h>
  12 #include <linux/init.h>
  13 #include <asm/assembler.h>
  14 #include <asm/asm-offsets.h>
  15 #include <asm/hwcap.h>
  16 #include <asm/pgtable-hwdef.h>
  17 #include <asm/pgtable.h>
  18 #include <asm/ptrace.h>
  19
  20 #include "proc-macros.S"
  21
  22         .text
  23 /*
  24  * cpu_arm740_proc_init()
  25  * cpu_arm740_do_idle()
  26  * cpu_arm740_dcache_clean_area()
  27  * cpu_arm740_switch_mm()
  28  *
  29  * These are not required.
  30  */
  31 ENTRY(cpu_arm740_proc_init)
  32 ENTRY(cpu_arm740_do_idle)
  33 ENTRY(cpu_arm740_dcache_clean_area)
  34 ENTRY(cpu_arm740_switch_mm)
  35         ret     lr
  36
  37 /*
  38  * cpu_arm740_proc_fin()
  39  */
  40 ENTRY(cpu_arm740_proc_fin)
  41         mrc     p15, 0, r0, c1, c0, 0
  42         bic     r0, r0, #0x3f000000             @ bank/f/lock/s
  43         bic     r0, r0, #0x0000000c             @ w-buffer/cache
  44         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  45         ret     lr
  46
  47 /*
  48  * cpu_arm740_reset(loc)
  49  * Params  : r0 = address to jump to
  50  * Notes   : This sets up everything for a reset
  51  */
  52         .pushsection    .idmap.text, "ax"
  53 ENTRY(cpu_arm740_reset)
  54         mov     ip, #0
  55         mcr     p15, 0, ip, c7, c0, 0           @ invalidate cache
  56         mrc     p15, 0, ip, c1, c0, 0           @ get ctrl register
  57         bic     ip, ip, #0x0000000c             @ ............wc..
  58         mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
  59         ret     r0
  60 ENDPROC(cpu_arm740_reset)
  61         .popsection
  62
  63         .type   __arm740_setup, #function
  64 __arm740_setup:
  65         mov     r0, #0
  66         mcr     p15, 0, r0, c7, c0, 0           @ invalidate caches
  67
  68         mcr     p15, 0, r0, c6, c3              @ disable area 3~7
  69         mcr     p15, 0, r0, c6, c4
  70         mcr     p15, 0, r0, c6, c5
  71         mcr     p15, 0, r0, c6, c6
  72         mcr     p15, 0, r0, c6, c7
  73
  74         mov     r0, #0x0000003F                 @ base = 0, size = 4GB
  75         mcr     p15, 0, r0, c6, c0              @ set area 0, default
  76
  77         ldr     r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
  78         ldr     r3, =(CONFIG_DRAM_SIZE >> 12)   @ size of RAM (must be >= 4KB)
  79         mov     r4, #10                         @ 11 is the minimum (4KB)
  80 1:      add     r4, r4, #1                      @ area size *= 2
  81         movs    r3, r3, lsr #1
  82         bne     1b                              @ count not zero r-shift
  83         orr     r0, r0, r4, lsl #1              @ the area register value
  84         orr     r0, r0, #1                      @ set enable bit
  85         mcr     p15, 0, r0, c6, c1              @ set area 1, RAM
  86
  87         ldr     r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
  88         ldr     r3, =(CONFIG_FLASH_SIZE >> 12)  @ size of FLASH (must be >= 4KB)
  89         cmp     r3, #0
  90         moveq   r0, #0
  91         beq     2f
  92         mov     r4, #10                         @ 11 is the minimum (4KB)
  93 1:      add     r4, r4, #1                      @ area size *= 2
  94         movs    r3, r3, lsr #1
  95         bne     1b                              @ count not zero r-shift
  96         orr     r0, r0, r4, lsl #1              @ the area register value
  97         orr     r0, r0, #1                      @ set enable bit
  98 2:      mcr     p15, 0, r0, c6, c2              @ set area 2, ROM/FLASH
  99
 100         mov     r0, #0x06
 101         mcr     p15, 0, r0, c2, c0              @ Region 1&2 cacheable
 102 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 103         mov     r0, #0x00                       @ disable whole write buffer
 104 #else
 105         mov     r0, #0x02                       @ Region 1 write bufferred
 106 #endif
 107         mcr     p15, 0, r0, c3, c0
 108
 109         mov     r0, #0x10000
 110         sub     r0, r0, #1                      @ r0 = 0xffff
 111         mcr     p15, 0, r0, c5, c0              @ all read/write access
 112
 113         mrc     p15, 0, r0, c1, c0              @ get control register
 114         bic     r0, r0, #0x3F000000             @ set to standard caching mode
 115                                                 @ need some benchmark
 116         orr     r0, r0, #0x0000000d             @ MPU/Cache/WB
 117
 118         ret     lr
 119
 120         .size   __arm740_setup, . - __arm740_setup
 121
 122         __INITDATA
 123
 124         @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
 125         define_processor_functions arm740, dabort=v4t_late_abort, pabort=legacy_pabort, nommu=1
 126
 127         .section ".rodata"
 128
 129         string  cpu_arch_name, "armv4"
 130         string  cpu_elf_name, "v4"
 131         string  cpu_arm740_name, "ARM740T"
 132
 133         .align
 134
 135         .section ".proc.info.init", #alloc
 136         .type   __arm740_proc_info,#object
 137 __arm740_proc_info:
 138         .long   0x41807400
 139         .long   0xfffffff0
 140         .long   0
 141         .long   0
 142         initfn  __arm740_setup, __arm740_proc_info
 143         .long   cpu_arch_name
 144         .long   cpu_elf_name
 145         .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_26BIT
 146         .long   cpu_arm740_name
 147         .long   arm740_processor_functions
 148         .long   0
 149         .long   0
 150         .long   v4_cache_fns                    @ cache model
 151         .size   __arm740_proc_info, . - __arm740_proc_info