arch/arm/mm/proc-sa1100.S

   1 /*
   2  *  linux/arch/arm/mm/proc-sa1100.S
   3  *
   4  *  Copyright (C) 1997-2002 Russell King
   5  *  hacked for non-paged-MM by Hyok S. Choi, 2003.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  *  MMU functions for SA110
  12  *
  13  *  These are the low level assembler for performing cache and TLB
  14  *  functions on the StrongARM-1100 and StrongARM-1110.
  15  *
  16  *  Note that SA1100 and SA1110 share everything but their name and CPU ID.
  17  *
  18  *  12-jun-2000, Erik Mouw (J.A.K.Mouw@its.tudelft.nl):
  19  *    Flush the read buffer at context switches
  20  */
  21 #include <linux/linkage.h>
  22 #include <linux/init.h>
  23 #include <asm/assembler.h>
  24 #include <asm/asm-offsets.h>
  25 #include <asm/hwcap.h>
  26 #include <mach/hardware.h>
  27 #include <asm/pgtable-hwdef.h>
  28 #include <asm/pgtable.h>
  29
  30 #include "proc-macros.S"
  31
  32 /*
  33  * the cache line size of the I and D cache
  34  */
  35 #define DCACHELINESIZE  32
  36
  37         __INIT
  38
  39 /*
  40  * cpu_sa1100_proc_init()
  41  */
  42 ENTRY(cpu_sa1100_proc_init)
  43         mov     r0, #0
  44         mcr     p15, 0, r0, c15, c1, 2          @ Enable clock switching
  45         mcr     p15, 0, r0, c9, c0, 5           @ Allow read-buffer operations from userland
  46         mov     pc, lr
  47
  48         .section .text
  49
  50 /*
  51  * cpu_sa1100_proc_fin()
  52  *
  53  * Prepare the CPU for reset:
  54  *  - Disable interrupts
  55  *  - Clean and turn off caches.
  56  */
  57 ENTRY(cpu_sa1100_proc_fin)
  58         mcr     p15, 0, ip, c15, c2, 2          @ Disable clock switching
  59         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
  60         bic     r0, r0, #0x1000                 @ ...i............
  61         bic     r0, r0, #0x000e                 @ ............wca.
  62         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  63         mov     pc, lr
  64
  65 /*
  66  * cpu_sa1100_reset(loc)
  67  *
  68  * Perform a soft reset of the system.  Put the CPU into the
  69  * same state as it would be if it had been reset, and branch
  70  * to what would be the reset vector.
  71  *
  72  * loc: location to jump to for soft reset
  73  */
  74         .align  5
  75 ENTRY(cpu_sa1100_reset)
  76         mov     ip, #0
  77         mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
  78         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
  79 #ifdef CONFIG_MMU
  80         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
  81 #endif
  82         mrc     p15, 0, ip, c1, c0, 0           @ ctrl register
  83         bic     ip, ip, #0x000f                 @ ............wcam
  84         bic     ip, ip, #0x1100                 @ ...i...s........
  85         mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
  86         mov     pc, r0
  87
  88 /*
  89  * cpu_sa1100_do_idle(type)
  90  *
  91  * Cause the processor to idle
  92  *
  93  * type: call type:
  94  *   0 = slow idle
  95  *   1 = fast idle
  96  *   2 = switch to slow processor clock
  97  *   3 = switch to fast processor clock
  98  */
  99         .align  5
 100 ENTRY(cpu_sa1100_do_idle)
 101         mov     r0, r0                          @ 4 nop padding
 102         mov     r0, r0
 103         mov     r0, r0
 104         mov     r0, r0                          @ 4 nop padding
 105         mov     r0, r0
 106         mov     r0, r0
 107         mov     r0, #0
 108         ldr     r1, =UNCACHEABLE_ADDR           @ ptr to uncacheable address
 109         @ --- aligned to a cache line
 110         mcr     p15, 0, r0, c15, c2, 2          @ disable clock switching
 111         ldr     r1, [r1, #0]                    @ force switch to MCLK
 112         mcr     p15, 0, r0, c15, c8, 2          @ wait for interrupt
 113         mov     r0, r0                          @ safety
 114         mcr     p15, 0, r0, c15, c1, 2          @ enable clock switching
 115         mov     pc, lr
 116
 117 /* ================================= CACHE ================================ */
 118
 119 /*
 120  * cpu_sa1100_dcache_clean_area(addr,sz)
 121  *
 122  * Clean the specified entry of any caches such that the MMU
 123  * translation fetches will obtain correct data.
 124  *
 125  * addr: cache-unaligned virtual address
 126  */
 127         .align  5
 128 ENTRY(cpu_sa1100_dcache_clean_area)
 129 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 130         add     r0, r0, #DCACHELINESIZE
 131         subs    r1, r1, #DCACHELINESIZE
 132         bhi     1b
 133         mov     pc, lr
 134
 135 /* =============================== PageTable ============================== */
 136
 137 /*
 138  * cpu_sa1100_switch_mm(pgd)
 139  *
 140  * Set the translation base pointer to be as described by pgd.
 141  *
 142  * pgd: new page tables
 143  */
 144         .align  5
 145 ENTRY(cpu_sa1100_switch_mm)
 146 #ifdef CONFIG_MMU
 147         str     lr, [sp, #-4]!
 148         bl      v4wb_flush_kern_cache_all       @ clears IP
 149         mcr     p15, 0, ip, c9, c0, 0           @ invalidate RB
 150         mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
 151         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
 152         ldr     pc, [sp], #4
 153 #else
 154         mov     pc, lr
 155 #endif
 156
 157 /*
 158  * cpu_sa1100_set_pte_ext(ptep, pte, ext)
 159  *
 160  * Set a PTE and flush it out
 161  */
 162         .align  5
 163 ENTRY(cpu_sa1100_set_pte_ext)
 164 #ifdef CONFIG_MMU
 165         armv3_set_pte_ext wc_disable=0
 166         mov     r0, r0
 167         mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 168         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
 169 #endif
 170         mov     pc, lr
 171
 172         __CPUINIT
 173
 174         .type   __sa1100_setup, #function
 175 __sa1100_setup:
 176         mov     r0, #0
 177         mcr     p15, 0, r0, c7, c7              @ invalidate I,D caches on v4
 178         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer on v4
 179 #ifdef CONFIG_MMU
 180         mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
 181 #endif
 182         adr     r5, sa1100_crval
 183         ldmia   r5, {r5, r6}
 184         mrc     p15, 0, r0, c1, c0              @ get control register v4
 185         bic     r0, r0, r5
 186         orr     r0, r0, r6
 187         mov     pc, lr
 188         .size   __sa1100_setup, . - __sa1100_setup
 189
 190         /*
 191          *  R
 192          * .RVI ZFRS BLDP WCAM
 193          * ..11 0001 ..11 1101
 194          *
 195          */
 196         .type   sa1100_crval, #object
 197 sa1100_crval:
 198         crval   clear=0x00003f3f, mmuset=0x0000313d, ucset=0x00001130
 199
 200         __INITDATA
 201
 202 /*
 203  * Purpose : Function pointers used to access above functions - all calls
 204  *           come through these
 205  */
 206
 207 /*
 208  * SA1100 and SA1110 share the same function calls
 209  */
 210         .type   sa1100_processor_functions, #object
 211 ENTRY(sa1100_processor_functions)
 212         .word   v4_early_abort
 213         .word   legacy_pabort
 214         .word   cpu_sa1100_proc_init
 215         .word   cpu_sa1100_proc_fin
 216         .word   cpu_sa1100_reset
 217         .word   cpu_sa1100_do_idle
 218         .word   cpu_sa1100_dcache_clean_area
 219         .word   cpu_sa1100_switch_mm
 220         .word   cpu_sa1100_set_pte_ext
 221         .size   sa1100_processor_functions, . - sa1100_processor_functions
 222
 223         .section ".rodata"
 224
 225         .type   cpu_arch_name, #object
 226 cpu_arch_name:
 227         .asciz  "armv4"
 228         .size   cpu_arch_name, . - cpu_arch_name
 229
 230         .type   cpu_elf_name, #object
 231 cpu_elf_name:
 232         .asciz  "v4"
 233         .size   cpu_elf_name, . - cpu_elf_name
 234
 235         .type   cpu_sa1100_name, #object
 236 cpu_sa1100_name:
 237         .asciz  "StrongARM-1100"
 238         .size   cpu_sa1100_name, . - cpu_sa1100_name
 239
 240         .type   cpu_sa1110_name, #object
 241 cpu_sa1110_name:
 242         .asciz  "StrongARM-1110"
 243         .size   cpu_sa1110_name, . - cpu_sa1110_name
 244
 245         .align
 246
 247         .section ".proc.info.init", #alloc, #execinstr
 248
 249         .type   __sa1100_proc_info,#object
 250 __sa1100_proc_info:
 251         .long   0x4401a110
 252         .long   0xfffffff0
 253         .long   PMD_TYPE_SECT | \
 254                 PMD_SECT_BUFFERABLE | \
 255                 PMD_SECT_CACHEABLE | \
 256                 PMD_SECT_AP_WRITE | \
 257                 PMD_SECT_AP_READ
 258         .long   PMD_TYPE_SECT | \
 259                 PMD_SECT_AP_WRITE | \
 260                 PMD_SECT_AP_READ
 261         b       __sa1100_setup
 262         .long   cpu_arch_name
 263         .long   cpu_elf_name
 264         .long   HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
 265         .long   cpu_sa1100_name
 266         .long   sa1100_processor_functions
 267         .long   v4wb_tlb_fns
 268         .long   v4_mc_user_fns
 269         .long   v4wb_cache_fns
 270         .size   __sa1100_proc_info, . - __sa1100_proc_info
 271
 272         .type   __sa1110_proc_info,#object
 273 __sa1110_proc_info:
 274         .long   0x6901b110
 275         .long   0xfffffff0
 276         .long   PMD_TYPE_SECT | \
 277                 PMD_SECT_BUFFERABLE | \
 278                 PMD_SECT_CACHEABLE | \
 279                 PMD_SECT_AP_WRITE | \
 280                 PMD_SECT_AP_READ
 281         .long   PMD_TYPE_SECT | \
 282                 PMD_SECT_AP_WRITE | \
 283                 PMD_SECT_AP_READ
 284         b       __sa1100_setup
 285         .long   cpu_arch_name
 286         .long   cpu_elf_name
 287         .long   HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT
 288         .long   cpu_sa1110_name
 289         .long   sa1100_processor_functions
 290         .long   v4wb_tlb_fns
 291         .long   v4_mc_user_fns
 292         .long   v4wb_cache_fns
 293         .size   __sa1110_proc_info, . - __sa1110_proc_info