arch/arm/mm/proc-v7-3level.S

   1 /*
   2  * arch/arm/mm/proc-v7-3level.S
   3  *
   4  * Copyright (C) 2001 Deep Blue Solutions Ltd.
   5  * Copyright (C) 2011 ARM Ltd.
   6  * Author: Catalin Marinas <catalin.marinas@arm.com>
   7  *   based on arch/arm/mm/proc-v7-2level.S
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21  */
  22
  23 #define TTB_IRGN_NC     (0 << 8)
  24 #define TTB_IRGN_WBWA   (1 << 8)
  25 #define TTB_IRGN_WT     (2 << 8)
  26 #define TTB_IRGN_WB     (3 << 8)
  27 #define TTB_RGN_NC      (0 << 10)
  28 #define TTB_RGN_OC_WBWA (1 << 10)
  29 #define TTB_RGN_OC_WT   (2 << 10)
  30 #define TTB_RGN_OC_WB   (3 << 10)
  31 #define TTB_S           (3 << 12)
  32 #define TTB_EAE         (1 << 31)
  33
  34 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
  35 #define TTB_FLAGS_UP    (TTB_IRGN_WB|TTB_RGN_OC_WB)
  36 #define PMD_FLAGS_UP    (PMD_SECT_WB)
  37
  38 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
  39 #define TTB_FLAGS_SMP   (TTB_IRGN_WBWA|TTB_S|TTB_RGN_OC_WBWA)
  40 #define PMD_FLAGS_SMP   (PMD_SECT_WBWA|PMD_SECT_S)
  41
  42 #ifndef __ARMEB__
  43 #  define rpgdl r0
  44 #  define rpgdh r1
  45 #else
  46 #  define rpgdl r1
  47 #  define rpgdh r0
  48 #endif
  49
  50 /*
  51  * cpu_v7_switch_mm(pgd_phys, tsk)
  52  *
  53  * Set the translation table base pointer to be pgd_phys (physical address of
  54  * the new TTB).
  55  */
  56 ENTRY(cpu_v7_switch_mm)
  57 #ifdef CONFIG_MMU
  58         mmid    r2, r2
  59         asid    r2, r2
  60         orr     rpgdh, rpgdh, r2, lsl #(48 - 32)        @ upper 32-bits of pgd
  61         mcrr    p15, 0, rpgdl, rpgdh, c2                @ set TTB 0
  62         isb
  63 #endif
  64         mov     pc, lr
  65 ENDPROC(cpu_v7_switch_mm)
  66
  67 /*
  68  * cpu_v7_set_pte_ext(ptep, pte)
  69  *
  70  * Set a level 2 translation table entry.
  71  * - ptep - pointer to level 3 translation table entry
  72  * - pte - PTE value to store (64-bit in r2 and r3)
  73  */
  74 ENTRY(cpu_v7_set_pte_ext)
  75 #ifdef CONFIG_MMU
  76         tst     r2, #L_PTE_VALID
  77         beq     1f
  78         tst     r3, #1 << (57 - 32)             @ L_PTE_NONE
  79         bicne   r2, #L_PTE_VALID
  80         bne     1f
  81         tst     r3, #1 << (55 - 32)             @ L_PTE_DIRTY
  82         orreq   r2, #L_PTE_RDONLY
  83 1:      strd    r2, r3, [r0]
  84         ALT_SMP(W(nop))
  85         ALT_UP (mcr     p15, 0, r0, c7, c10, 1)         @ flush_pte
  86 #endif
  87         mov     pc, lr
  88 ENDPROC(cpu_v7_set_pte_ext)
  89
  90         /*
  91          * Memory region attributes for LPAE (defined in pgtable-3level.h):
  92          *
  93          *   n = AttrIndx[2:0]
  94          *
  95          *                      n       MAIR
  96          *   UNCACHED           000     00000000
  97          *   BUFFERABLE         001     01000100
  98          *   DEV_WC             001     01000100
  99          *   WRITETHROUGH       010     10101010
 100          *   WRITEBACK          011     11101110
 101          *   DEV_CACHED         011     11101110
 102          *   DEV_SHARED         100     00000100
 103          *   DEV_NONSHARED      100     00000100
 104          *   unused             101
 105          *   unused             110
 106          *   WRITEALLOC         111     11111111
 107          */
 108 .equ    PRRR,   0xeeaa4400                      @ MAIR0
 109 .equ    NMRR,   0xff000004                      @ MAIR1
 110
 111         /*
 112          * Macro for setting up the TTBRx and TTBCR registers.
 113          * - \ttbr1 updated.
 114          */
 115         .macro  v7_ttb_setup, zero, ttbr0, ttbr1, tmp
 116         ldr     \tmp, =swapper_pg_dir           @ swapper_pg_dir virtual address
 117         mov     \tmp, \tmp, lsr #ARCH_PGD_SHIFT
 118         cmp     \ttbr1, \tmp                    @ PHYS_OFFSET > PAGE_OFFSET?
 119         mrc     p15, 0, \tmp, c2, c0, 2         @ TTB control register
 120         orr     \tmp, \tmp, #TTB_EAE
 121         ALT_SMP(orr     \tmp, \tmp, #TTB_FLAGS_SMP)
 122         ALT_UP(orr      \tmp, \tmp, #TTB_FLAGS_UP)
 123         ALT_SMP(orr     \tmp, \tmp, #TTB_FLAGS_SMP << 16)
 124         ALT_UP(orr      \tmp, \tmp, #TTB_FLAGS_UP << 16)
 125         /*
 126          * Only use split TTBRs if PHYS_OFFSET <= PAGE_OFFSET (cmp above),
 127          * otherwise booting secondary CPUs would end up using TTBR1 for the
 128          * identity mapping set up in TTBR0.
 129          */
 130         orrls   \tmp, \tmp, #TTBR1_SIZE                         @ TTBCR.T1SZ
 131         mcr     p15, 0, \tmp, c2, c0, 2                         @ TTBCR
 132         mov     \tmp, \ttbr1, lsr #(32 - ARCH_PGD_SHIFT)        @ upper bits
 133         mov     \ttbr1, \ttbr1, lsl #ARCH_PGD_SHIFT             @ lower bits
 134         addls   \ttbr1, \ttbr1, #TTBR1_OFFSET
 135         mcrr    p15, 1, \ttbr1, \zero, c2                       @ load TTBR1
 136         mov     \tmp, \ttbr0, lsr #(32 - ARCH_PGD_SHIFT)        @ upper bits
 137         mov     \ttbr0, \ttbr0, lsl #ARCH_PGD_SHIFT             @ lower bits
 138         mcrr    p15, 0, \ttbr0, \zero, c2                       @ load TTBR0
 139         mcrr    p15, 1, \ttbr1, \zero, c2                       @ load TTBR1
 140         mcrr    p15, 0, \ttbr0, \zero, c2                       @ load TTBR0
 141         .endm
 142
 143         /*
 144          *   AT
 145          *  TFR   EV X F   IHD LR    S
 146          * .EEE ..EE PUI. .TAT 4RVI ZWRS BLDP WCAM
 147          * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
 148          *   11    0 110    1  0011 1100 .111 1101 < we want
 149          */
 150         .align  2
 151         .type   v7_crval, #object
 152 v7_crval:
 153         crval   clear=0x0120c302, mmuset=0x30c23c7d, ucset=0x00c01c7c