arch/arm/mm/proc-v7.S

   1 /*
   2  *  linux/arch/arm/mm/proc-v7.S
   3  *
   4  *  Copyright (C) 2001 Deep Blue Solutions Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  This is the "shell" of the ARMv7 processor support.
  11  */
  12 #include <linux/init.h>
  13 #include <linux/linkage.h>
  14 #include <asm/assembler.h>
  15 #include <asm/asm-offsets.h>
  16 #include <asm/hwcap.h>
  17 #include <asm/pgtable-hwdef.h>
  18 #include <asm/pgtable.h>
  19
  20 #include "proc-macros.S"
  21
  22 #ifdef CONFIG_ARM_LPAE
  23 #include "proc-v7-3level.S"
  24 #else
  25 #include "proc-v7-2level.S"
  26 #endif
  27
  28 ENTRY(cpu_v7_proc_init)
  29         mov     pc, lr
  30 ENDPROC(cpu_v7_proc_init)
  31
  32 ENTRY(cpu_v7_proc_fin)
  33         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
  34         bic     r0, r0, #0x1000                 @ ...i............
  35         bic     r0, r0, #0x0006                 @ .............ca.
  36         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  37         mov     pc, lr
  38 ENDPROC(cpu_v7_proc_fin)
  39
  40 /*
  41  *      cpu_v7_reset(loc)
  42  *
  43  *      Perform a soft reset of the system.  Put the CPU into the
  44  *      same state as it would be if it had been reset, and branch
  45  *      to what would be the reset vector.
  46  *
  47  *      - loc   - location to jump to for soft reset
  48  *
  49  *      This code must be executed using a flat identity mapping with
  50  *      caches disabled.
  51  */
  52         .align  5
  53         .pushsection    .idmap.text, "ax"
  54 ENTRY(cpu_v7_reset)
  55         mrc     p15, 0, r1, c1, c0, 0           @ ctrl register
  56         bic     r1, r1, #0x1                    @ ...............m
  57  THUMB( bic     r1, r1, #1 << 30 )              @ SCTLR.TE (Thumb exceptions)
  58         mcr     p15, 0, r1, c1, c0, 0           @ disable MMU
  59         isb
  60         bx      r0
  61 ENDPROC(cpu_v7_reset)
  62         .popsection
  63
  64 /*
  65  *      cpu_v7_do_idle()
  66  *
  67  *      Idle the processor (eg, wait for interrupt).
  68  *
  69  *      IRQs are already disabled.
  70  */
  71 ENTRY(cpu_v7_do_idle)
  72         dsb                                     @ WFI may enter a low-power mode
  73         wfi
  74         mov     pc, lr
  75 ENDPROC(cpu_v7_do_idle)
  76
  77 ENTRY(cpu_v7_dcache_clean_area)
  78         ALT_SMP(mov     pc, lr)                 @ MP extensions imply L1 PTW
  79         ALT_UP(W(nop))
  80         dcache_line_size r2, r3
  81 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
  82         add     r0, r0, r2
  83         subs    r1, r1, r2
  84         bhi     1b
  85         dsb
  86         mov     pc, lr
  87 ENDPROC(cpu_v7_dcache_clean_area)
  88
  89         string  cpu_v7_name, "ARMv7 Processor"
  90         .align
  91
  92 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
  93 .globl  cpu_v7_suspend_size
  94 .equ    cpu_v7_suspend_size, 4 * 8
  95 #ifdef CONFIG_ARM_CPU_SUSPEND
  96 ENTRY(cpu_v7_do_suspend)
  97         stmfd   sp!, {r4 - r10, lr}
  98         mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
  99         mrc     p15, 0, r5, c13, c0, 3  @ User r/o thread ID
 100         stmia   r0!, {r4 - r5}
 101 #ifdef CONFIG_MMU
 102         mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
 103         mrc     p15, 0, r7, c2, c0, 1   @ TTB 1
 104         mrc     p15, 0, r11, c2, c0, 2  @ TTB control register
 105 #endif
 106         mrc     p15, 0, r8, c1, c0, 0   @ Control register
 107         mrc     p15, 0, r9, c1, c0, 1   @ Auxiliary control register
 108         mrc     p15, 0, r10, c1, c0, 2  @ Co-processor access control
 109         stmia   r0, {r6 - r11}
 110         ldmfd   sp!, {r4 - r10, pc}
 111 ENDPROC(cpu_v7_do_suspend)
 112
 113 ENTRY(cpu_v7_do_resume)
 114         mov     ip, #0
 115         mcr     p15, 0, ip, c7, c5, 0   @ invalidate I cache
 116         mcr     p15, 0, ip, c13, c0, 1  @ set reserved context ID
 117         ldmia   r0!, {r4 - r5}
 118         mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
 119         mcr     p15, 0, r5, c13, c0, 3  @ User r/o thread ID
 120         ldmia   r0, {r6 - r11}
 121 #ifdef CONFIG_MMU
 122         mcr     p15, 0, ip, c8, c7, 0   @ invalidate TLBs
 123         mcr     p15, 0, r6, c3, c0, 0   @ Domain ID
 124 #ifndef CONFIG_ARM_LPAE
 125         ALT_SMP(orr     r1, r1, #TTB_FLAGS_SMP)
 126         ALT_UP(orr      r1, r1, #TTB_FLAGS_UP)
 127 #endif
 128         mcr     p15, 0, r1, c2, c0, 0   @ TTB 0
 129         mcr     p15, 0, r7, c2, c0, 1   @ TTB 1
 130         mcr     p15, 0, r11, c2, c0, 2  @ TTB control register
 131         ldr     r4, =PRRR               @ PRRR
 132         ldr     r5, =NMRR               @ NMRR
 133         mcr     p15, 0, r4, c10, c2, 0  @ write PRRR
 134         mcr     p15, 0, r5, c10, c2, 1  @ write NMRR
 135 #endif  /* CONFIG_MMU */
 136         mrc     p15, 0, r4, c1, c0, 1   @ Read Auxiliary control register
 137         teq     r4, r9                  @ Is it already set?
 138         mcrne   p15, 0, r9, c1, c0, 1   @ No, so write it
 139         mcr     p15, 0, r10, c1, c0, 2  @ Co-processor access control
 140         isb
 141         dsb
 142         mov     r0, r8                  @ control register
 143         b       cpu_resume_mmu
 144 ENDPROC(cpu_v7_do_resume)
 145 #endif
 146
 147 #ifdef CONFIG_CPU_PJ4B
 148         globl_equ       cpu_pj4b_switch_mm,     cpu_v7_switch_mm
 149         globl_equ       cpu_pj4b_set_pte_ext,   cpu_v7_set_pte_ext
 150         globl_equ       cpu_pj4b_proc_init,     cpu_v7_proc_init
 151         globl_equ       cpu_pj4b_proc_fin,      cpu_v7_proc_fin
 152         globl_equ       cpu_pj4b_reset,         cpu_v7_reset
 153 #ifdef CONFIG_PJ4B_ERRATA_4742
 154 ENTRY(cpu_pj4b_do_idle)
 155         dsb                                     @ WFI may enter a low-power mode
 156         wfi
 157         dsb                                     @barrier
 158         mov     pc, lr
 159 ENDPROC(cpu_pj4b_do_idle)
 160 #else
 161         globl_equ       cpu_pj4b_do_idle,       cpu_v7_do_idle
 162 #endif
 163         globl_equ       cpu_pj4b_dcache_clean_area,     cpu_v7_dcache_clean_area
 164         globl_equ       cpu_pj4b_do_suspend,    cpu_v7_do_suspend
 165         globl_equ       cpu_pj4b_do_resume,     cpu_v7_do_resume
 166         globl_equ       cpu_pj4b_suspend_size,  cpu_v7_suspend_size
 167
 168 #endif
 169
 170         __CPUINIT
 171
 172 /*
 173  *      __v7_setup
 174  *
 175  *      Initialise TLB, Caches, and MMU state ready to switch the MMU
 176  *      on.  Return in r0 the new CP15 C1 control register setting.
 177  *
 178  *      This should be able to cover all ARMv7 cores.
 179  *
 180  *      It is assumed that:
 181  *      - cache type register is implemented
 182  */
 183 __v7_ca5mp_setup:
 184 __v7_ca9mp_setup:
 185 __v7_cr7mp_setup:
 186         mov     r10, #(1 << 0)                  @ Cache/TLB ops broadcasting
 187         b       1f
 188 __v7_ca7mp_setup:
 189 __v7_ca15mp_setup:
 190         mov     r10, #0
 191 1:
 192 #ifdef CONFIG_SMP
 193         ALT_SMP(mrc     p15, 0, r0, c1, c0, 1)
 194         ALT_UP(mov      r0, #(1 << 6))          @ fake it for UP
 195         tst     r0, #(1 << 6)                   @ SMP/nAMP mode enabled?
 196         orreq   r0, r0, #(1 << 6)               @ Enable SMP/nAMP mode
 197         orreq   r0, r0, r10                     @ Enable CPU-specific SMP bits
 198         mcreq   p15, 0, r0, c1, c0, 1
 199 #endif
 200         b       __v7_setup
 201
 202 __v7_pj4b_setup:
 203 #ifdef CONFIG_CPU_PJ4B
 204
 205 /* Auxiliary Debug Modes Control 1 Register */
 206 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
 207 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
 208 #define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
 209 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
 210
 211 /* Auxiliary Debug Modes Control 2 Register */
 212 #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
 213 #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
 214 #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
 215 #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
 216 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
 217 #define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
 218                             PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
 219
 220 /* Auxiliary Functional Modes Control Register 0 */
 221 #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
 222 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
 223 #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
 224
 225 /* Auxiliary Debug Modes Control 0 Register */
 226 #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
 227
 228         /* Auxiliary Debug Modes Control 1 Register */
 229         mrc     p15, 1, r0, c15, c1, 1
 230         orr     r0, r0, #PJ4B_CLEAN_LINE
 231         orr     r0, r0, #PJ4B_BCK_OFF_STREX
 232         orr     r0, r0, #PJ4B_INTER_PARITY
 233         bic     r0, r0, #PJ4B_STATIC_BP
 234         mcr     p15, 1, r0, c15, c1, 1
 235
 236         /* Auxiliary Debug Modes Control 2 Register */
 237         mrc     p15, 1, r0, c15, c1, 2
 238         bic     r0, r0, #PJ4B_FAST_LDR
 239         orr     r0, r0, #PJ4B_AUX_DBG_CTRL2
 240         mcr     p15, 1, r0, c15, c1, 2
 241
 242         /* Auxiliary Functional Modes Control Register 0 */
 243         mrc     p15, 1, r0, c15, c2, 0
 244 #ifdef CONFIG_SMP
 245         orr     r0, r0, #PJ4B_SMP_CFB
 246 #endif
 247         orr     r0, r0, #PJ4B_L1_PAR_CHK
 248         orr     r0, r0, #PJ4B_BROADCAST_CACHE
 249         mcr     p15, 1, r0, c15, c2, 0
 250
 251         /* Auxiliary Debug Modes Control 0 Register */
 252         mrc     p15, 1, r0, c15, c1, 0
 253         orr     r0, r0, #PJ4B_WFI_WFE
 254         mcr     p15, 1, r0, c15, c1, 0
 255
 256 #endif /* CONFIG_CPU_PJ4B */
 257
 258 __v7_setup:
 259         adr     r12, __v7_setup_stack           @ the local stack
 260         stmia   r12, {r0-r5, r7, r9, r11, lr}
 261         bl      v7_flush_dcache_louis
 262         ldmia   r12, {r0-r5, r7, r9, r11, lr}
 263
 264         mrc     p15, 0, r0, c0, c0, 0           @ read main ID register
 265         and     r10, r0, #0xff000000            @ ARM?
 266         teq     r10, #0x41000000
 267         bne     3f
 268         and     r5, r0, #0x00f00000             @ variant
 269         and     r6, r0, #0x0000000f             @ revision
 270         orr     r6, r6, r5, lsr #20-4           @ combine variant and revision
 271         ubfx    r0, r0, #4, #12                 @ primary part number
 272
 273         /* Cortex-A8 Errata */
 274         ldr     r10, =0x00000c08                @ Cortex-A8 primary part number
 275         teq     r0, r10
 276         bne     2f
 277 #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
 278
 279         teq     r5, #0x00100000                 @ only present in r1p*
 280         mrceq   p15, 0, r10, c1, c0, 1          @ read aux control register
 281         orreq   r10, r10, #(1 << 6)             @ set IBE to 1
 282         mcreq   p15, 0, r10, c1, c0, 1          @ write aux control register
 283 #endif
 284 #ifdef CONFIG_ARM_ERRATA_458693
 285         teq     r6, #0x20                       @ only present in r2p0
 286         mrceq   p15, 0, r10, c1, c0, 1          @ read aux control register
 287         orreq   r10, r10, #(1 << 5)             @ set L1NEON to 1
 288         orreq   r10, r10, #(1 << 9)             @ set PLDNOP to 1
 289         mcreq   p15, 0, r10, c1, c0, 1          @ write aux control register
 290 #endif
 291 #ifdef CONFIG_ARM_ERRATA_460075
 292         teq     r6, #0x20                       @ only present in r2p0
 293         mrceq   p15, 1, r10, c9, c0, 2          @ read L2 cache aux ctrl register
 294         tsteq   r10, #1 << 22
 295         orreq   r10, r10, #(1 << 22)            @ set the Write Allocate disable bit
 296         mcreq   p15, 1, r10, c9, c0, 2          @ write the L2 cache aux ctrl register
 297 #endif
 298         b       3f
 299
 300         /* Cortex-A9 Errata */
 301 2:      ldr     r10, =0x00000c09                @ Cortex-A9 primary part number
 302         teq     r0, r10
 303         bne     3f
 304 #ifdef CONFIG_ARM_ERRATA_742230
 305         cmp     r6, #0x22                       @ only present up to r2p2
 306         mrcle   p15, 0, r10, c15, c0, 1         @ read diagnostic register
 307         orrle   r10, r10, #1 << 4               @ set bit #4
 308         mcrle   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 309 #endif
 310 #ifdef CONFIG_ARM_ERRATA_742231
 311         teq     r6, #0x20                       @ present in r2p0
 312         teqne   r6, #0x21                       @ present in r2p1
 313         teqne   r6, #0x22                       @ present in r2p2
 314         mrceq   p15, 0, r10, c15, c0, 1         @ read diagnostic register
 315         orreq   r10, r10, #1 << 12              @ set bit #12
 316         orreq   r10, r10, #1 << 22              @ set bit #22
 317         mcreq   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 318 #endif
 319 #ifdef CONFIG_ARM_ERRATA_743622
 320         teq     r5, #0x00200000                 @ only present in r2p*
 321         mrceq   p15, 0, r10, c15, c0, 1         @ read diagnostic register
 322         orreq   r10, r10, #1 << 6               @ set bit #6
 323         mcreq   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 324 #endif
 325 #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
 326         ALT_SMP(cmp r6, #0x30)                  @ present prior to r3p0
 327         ALT_UP_B(1f)
 328         mrclt   p15, 0, r10, c15, c0, 1         @ read diagnostic register
 329         orrlt   r10, r10, #1 << 11              @ set bit #11
 330         mcrlt   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 331 1:
 332 #endif
 333
 334 3:      mov     r10, #0
 335         mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
 336         dsb
 337 #ifdef CONFIG_MMU
 338         mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs
 339         v7_ttb_setup r10, r4, r8, r5            @ TTBCR, TTBRx setup
 340         ldr     r5, =PRRR                       @ PRRR
 341         ldr     r6, =NMRR                       @ NMRR
 342         mcr     p15, 0, r5, c10, c2, 0          @ write PRRR
 343         mcr     p15, 0, r6, c10, c2, 1          @ write NMRR
 344 #endif
 345 #ifndef CONFIG_ARM_THUMBEE
 346         mrc     p15, 0, r0, c0, c1, 0           @ read ID_PFR0 for ThumbEE
 347         and     r0, r0, #(0xf << 12)            @ ThumbEE enabled field
 348         teq     r0, #(1 << 12)                  @ check if ThumbEE is present
 349         bne     1f
 350         mov     r5, #0
 351         mcr     p14, 6, r5, c1, c0, 0           @ Initialize TEEHBR to 0
 352         mrc     p14, 6, r0, c0, c0, 0           @ load TEECR
 353         orr     r0, r0, #1                      @ set the 1st bit in order to
 354         mcr     p14, 6, r0, c0, c0, 0           @ stop userspace TEEHBR access
 355 1:
 356 #endif
 357         adr     r5, v7_crval
 358         ldmia   r5, {r5, r6}
 359 #ifdef CONFIG_CPU_ENDIAN_BE8
 360         orr     r6, r6, #1 << 25                @ big-endian page tables
 361 #endif
 362 #ifdef CONFIG_SWP_EMULATE
 363         orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
 364         bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
 365 #endif
 366         mrc     p15, 0, r0, c1, c0, 0           @ read control register
 367         bic     r0, r0, r5                      @ clear bits them
 368         orr     r0, r0, r6                      @ set them
 369  THUMB( orr     r0, r0, #1 << 30        )       @ Thumb exceptions
 370         mov     pc, lr                          @ return to head.S:__ret
 371 ENDPROC(__v7_setup)
 372
 373         .align  2
 374 __v7_setup_stack:
 375         .space  4 * 11                          @ 11 registers
 376
 377         __INITDATA
 378
 379         @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
 380         define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
 381 #ifdef CONFIG_CPU_PJ4B
 382         define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
 383 #endif
 384
 385         .section ".rodata"
 386
 387         string  cpu_arch_name, "armv7"
 388         string  cpu_elf_name, "v7"
 389         .align
 390
 391         .section ".proc.info.init", #alloc, #execinstr
 392
 393         /*
 394          * Standard v7 proc info content
 395          */
 396 .macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
 397         ALT_SMP(.long   PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
 398                         PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
 399         ALT_UP(.long    PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
 400                         PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
 401         .long   PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
 402                 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
 403         W(b)    \initfunc
 404         .long   cpu_arch_name
 405         .long   cpu_elf_name
 406         .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
 407                 HWCAP_EDSP | HWCAP_TLS | \hwcaps
 408         .long   cpu_v7_name
 409         .long   \proc_fns
 410         .long   v7wbi_tlb_fns
 411         .long   v6_user_fns
 412         .long   v7_cache_fns
 413 .endm
 414
 415 #ifndef CONFIG_ARM_LPAE
 416         /*
 417          * ARM Ltd. Cortex A5 processor.
 418          */
 419         .type   __v7_ca5mp_proc_info, #object
 420 __v7_ca5mp_proc_info:
 421         .long   0x410fc050
 422         .long   0xff0ffff0
 423         __v7_proc __v7_ca5mp_setup
 424         .size   __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
 425
 426         /*
 427          * ARM Ltd. Cortex A9 processor.
 428          */
 429         .type   __v7_ca9mp_proc_info, #object
 430 __v7_ca9mp_proc_info:
 431         .long   0x410fc090
 432         .long   0xff0ffff0
 433         __v7_proc __v7_ca9mp_setup
 434         .size   __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
 435
 436 #endif  /* CONFIG_ARM_LPAE */
 437
 438         /*
 439          * Marvell PJ4B processor.
 440          */
 441 #ifdef CONFIG_CPU_PJ4B
 442         .type   __v7_pj4b_proc_info, #object
 443 __v7_pj4b_proc_info:
 444         .long   0x560f5800
 445         .long   0xff0fff00
 446         __v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions
 447         .size   __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
 448 #endif
 449
 450         /*
 451          * ARM Ltd. Cortex R7 processor.
 452          */
 453         .type   __v7_cr7mp_proc_info, #object
 454 __v7_cr7mp_proc_info:
 455         .long   0x410fc170
 456         .long   0xff0ffff0
 457         __v7_proc __v7_cr7mp_setup
 458         .size   __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
 459
 460         /*
 461          * ARM Ltd. Cortex A7 processor.
 462          */
 463         .type   __v7_ca7mp_proc_info, #object
 464 __v7_ca7mp_proc_info:
 465         .long   0x410fc070
 466         .long   0xff0ffff0
 467         __v7_proc __v7_ca7mp_setup
 468         .size   __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
 469
 470         /*
 471          * ARM Ltd. Cortex A15 processor.
 472          */
 473         .type   __v7_ca15mp_proc_info, #object
 474 __v7_ca15mp_proc_info:
 475         .long   0x410fc0f0
 476         .long   0xff0ffff0
 477         __v7_proc __v7_ca15mp_setup
 478         .size   __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
 479
 480         /*
 481          * Qualcomm Inc. Krait processors.
 482          */
 483         .type   __krait_proc_info, #object
 484 __krait_proc_info:
 485         .long   0x510f0400              @ Required ID value
 486         .long   0xff0ffc00              @ Mask for ID
 487         /*
 488          * Some Krait processors don't indicate support for SDIV and UDIV
 489          * instructions in the ARM instruction set, even though they actually
 490          * do support them.
 491          */
 492         __v7_proc __v7_setup, hwcaps = HWCAP_IDIV
 493         .size   __krait_proc_info, . - __krait_proc_info
 494
 495         /*
 496          * Match any ARMv7 processor core.
 497          */
 498         .type   __v7_proc_info, #object
 499 __v7_proc_info:
 500         .long   0x000f0000              @ Required ID value
 501         .long   0x000f0000              @ Mask for ID
 502         __v7_proc __v7_setup
 503         .size   __v7_proc_info, . - __v7_proc_info