arch/arm/mm/proc-v7.S

   1 /*
   2  *  linux/arch/arm/mm/proc-v7.S
   3  *
   4  *  Copyright (C) 2001 Deep Blue Solutions Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  *  This is the "shell" of the ARMv7 processor support.
  11  */
  12 #include <linux/init.h>
  13 #include <linux/linkage.h>
  14 #include <asm/assembler.h>
  15 #include <asm/asm-offsets.h>
  16 #include <asm/hwcap.h>
  17 #include <asm/pgtable-hwdef.h>
  18 #include <asm/pgtable.h>
  19
  20 #include "proc-macros.S"
  21
  22 #ifdef CONFIG_ARM_LPAE
  23 #include "proc-v7-3level.S"
  24 #else
  25 #include "proc-v7-2level.S"
  26 #endif
  27
  28 ENTRY(cpu_v7_proc_init)
  29         ret     lr
  30 ENDPROC(cpu_v7_proc_init)
  31
  32 ENTRY(cpu_v7_proc_fin)
  33         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
  34         bic     r0, r0, #0x1000                 @ ...i............
  35         bic     r0, r0, #0x0006                 @ .............ca.
  36         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
  37         ret     lr
  38 ENDPROC(cpu_v7_proc_fin)
  39
  40 /*
  41  *      cpu_v7_reset(loc)
  42  *
  43  *      Perform a soft reset of the system.  Put the CPU into the
  44  *      same state as it would be if it had been reset, and branch
  45  *      to what would be the reset vector.
  46  *
  47  *      - loc   - location to jump to for soft reset
  48  *
  49  *      This code must be executed using a flat identity mapping with
  50  *      caches disabled.
  51  */
  52         .align  5
  53         .pushsection    .idmap.text, "ax"
  54 ENTRY(cpu_v7_reset)
  55         mrc     p15, 0, r1, c1, c0, 0           @ ctrl register
  56         bic     r1, r1, #0x1                    @ ...............m
  57  THUMB( bic     r1, r1, #1 << 30 )              @ SCTLR.TE (Thumb exceptions)
  58         mcr     p15, 0, r1, c1, c0, 0           @ disable MMU
  59         isb
  60         bx      r0
  61 ENDPROC(cpu_v7_reset)
  62         .popsection
  63
  64 /*
  65  *      cpu_v7_do_idle()
  66  *
  67  *      Idle the processor (eg, wait for interrupt).
  68  *
  69  *      IRQs are already disabled.
  70  */
  71 ENTRY(cpu_v7_do_idle)
  72         dsb                                     @ WFI may enter a low-power mode
  73         wfi
  74         ret     lr
  75 ENDPROC(cpu_v7_do_idle)
  76
  77 ENTRY(cpu_v7_dcache_clean_area)
  78         ALT_SMP(W(nop))                 @ MP extensions imply L1 PTW
  79         ALT_UP_B(1f)
  80         ret     lr
  81 1:      dcache_line_size r2, r3
  82 2:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
  83         add     r0, r0, r2
  84         subs    r1, r1, r2
  85         bhi     2b
  86         dsb     ishst
  87         ret     lr
  88 ENDPROC(cpu_v7_dcache_clean_area)
  89
  90         string  cpu_v7_name, "ARMv7 Processor"
  91         .align
  92
  93 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
  94 .globl  cpu_v7_suspend_size
  95 .equ    cpu_v7_suspend_size, 4 * 9
  96 #ifdef CONFIG_ARM_CPU_SUSPEND
  97 ENTRY(cpu_v7_do_suspend)
  98         stmfd   sp!, {r4 - r10, lr}
  99         mrc     p15, 0, r4, c13, c0, 0  @ FCSE/PID
 100         mrc     p15, 0, r5, c13, c0, 3  @ User r/o thread ID
 101         stmia   r0!, {r4 - r5}
 102 #ifdef CONFIG_MMU
 103         mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
 104 #ifdef CONFIG_ARM_LPAE
 105         mrrc    p15, 1, r5, r7, c2      @ TTB 1
 106 #else
 107         mrc     p15, 0, r7, c2, c0, 1   @ TTB 1
 108 #endif
 109         mrc     p15, 0, r11, c2, c0, 2  @ TTB control register
 110 #endif
 111         mrc     p15, 0, r8, c1, c0, 0   @ Control register
 112         mrc     p15, 0, r9, c1, c0, 1   @ Auxiliary control register
 113         mrc     p15, 0, r10, c1, c0, 2  @ Co-processor access control
 114         stmia   r0, {r5 - r11}
 115         ldmfd   sp!, {r4 - r10, pc}
 116 ENDPROC(cpu_v7_do_suspend)
 117
 118 ENTRY(cpu_v7_do_resume)
 119         mov     ip, #0
 120         mcr     p15, 0, ip, c7, c5, 0   @ invalidate I cache
 121         mcr     p15, 0, ip, c13, c0, 1  @ set reserved context ID
 122         ldmia   r0!, {r4 - r5}
 123         mcr     p15, 0, r4, c13, c0, 0  @ FCSE/PID
 124         mcr     p15, 0, r5, c13, c0, 3  @ User r/o thread ID
 125         ldmia   r0, {r5 - r11}
 126 #ifdef CONFIG_MMU
 127         mcr     p15, 0, ip, c8, c7, 0   @ invalidate TLBs
 128         mcr     p15, 0, r6, c3, c0, 0   @ Domain ID
 129 #ifdef CONFIG_ARM_LPAE
 130         mcrr    p15, 0, r1, ip, c2      @ TTB 0
 131         mcrr    p15, 1, r5, r7, c2      @ TTB 1
 132 #else
 133         ALT_SMP(orr     r1, r1, #TTB_FLAGS_SMP)
 134         ALT_UP(orr      r1, r1, #TTB_FLAGS_UP)
 135         mcr     p15, 0, r1, c2, c0, 0   @ TTB 0
 136         mcr     p15, 0, r7, c2, c0, 1   @ TTB 1
 137 #endif
 138         mcr     p15, 0, r11, c2, c0, 2  @ TTB control register
 139         ldr     r4, =PRRR               @ PRRR
 140         ldr     r5, =NMRR               @ NMRR
 141         mcr     p15, 0, r4, c10, c2, 0  @ write PRRR
 142         mcr     p15, 0, r5, c10, c2, 1  @ write NMRR
 143 #endif  /* CONFIG_MMU */
 144         mrc     p15, 0, r4, c1, c0, 1   @ Read Auxiliary control register
 145         teq     r4, r9                  @ Is it already set?
 146         mcrne   p15, 0, r9, c1, c0, 1   @ No, so write it
 147         mcr     p15, 0, r10, c1, c0, 2  @ Co-processor access control
 148         isb
 149         dsb
 150         mov     r0, r8                  @ control register
 151         b       cpu_resume_mmu
 152 ENDPROC(cpu_v7_do_resume)
 153 #endif
 154
 155 /*
 156  * Cortex-A8
 157  */
 158         globl_equ       cpu_ca8_proc_init,      cpu_v7_proc_init
 159         globl_equ       cpu_ca8_proc_fin,       cpu_v7_proc_fin
 160         globl_equ       cpu_ca8_reset,          cpu_v7_reset
 161         globl_equ       cpu_ca8_do_idle,        cpu_v7_do_idle
 162         globl_equ       cpu_ca8_dcache_clean_area, cpu_v7_dcache_clean_area
 163         globl_equ       cpu_ca8_set_pte_ext,    cpu_v7_set_pte_ext
 164         globl_equ       cpu_ca8_suspend_size,   cpu_v7_suspend_size
 165 #ifdef CONFIG_ARM_CPU_SUSPEND
 166         globl_equ       cpu_ca8_do_suspend,     cpu_v7_do_suspend
 167         globl_equ       cpu_ca8_do_resume,      cpu_v7_do_resume
 168 #endif
 169
 170 /*
 171  * Cortex-A9 processor functions
 172  */
 173         globl_equ       cpu_ca9mp_proc_init,    cpu_v7_proc_init
 174         globl_equ       cpu_ca9mp_proc_fin,     cpu_v7_proc_fin
 175         globl_equ       cpu_ca9mp_reset,        cpu_v7_reset
 176         globl_equ       cpu_ca9mp_do_idle,      cpu_v7_do_idle
 177         globl_equ       cpu_ca9mp_dcache_clean_area, cpu_v7_dcache_clean_area
 178         globl_equ       cpu_ca9mp_switch_mm,    cpu_v7_switch_mm
 179         globl_equ       cpu_ca9mp_set_pte_ext,  cpu_v7_set_pte_ext
 180 .globl  cpu_ca9mp_suspend_size
 181 .equ    cpu_ca9mp_suspend_size, cpu_v7_suspend_size + 4 * 2
 182 #ifdef CONFIG_ARM_CPU_SUSPEND
 183 ENTRY(cpu_ca9mp_do_suspend)
 184         stmfd   sp!, {r4 - r5}
 185         mrc     p15, 0, r4, c15, c0, 1          @ Diagnostic register
 186         mrc     p15, 0, r5, c15, c0, 0          @ Power register
 187         stmia   r0!, {r4 - r5}
 188         ldmfd   sp!, {r4 - r5}
 189         b       cpu_v7_do_suspend
 190 ENDPROC(cpu_ca9mp_do_suspend)
 191
 192 ENTRY(cpu_ca9mp_do_resume)
 193         ldmia   r0!, {r4 - r5}
 194         mrc     p15, 0, r10, c15, c0, 1         @ Read Diagnostic register
 195         teq     r4, r10                         @ Already restored?
 196         mcrne   p15, 0, r4, c15, c0, 1          @ No, so restore it
 197         mrc     p15, 0, r10, c15, c0, 0         @ Read Power register
 198         teq     r5, r10                         @ Already restored?
 199         mcrne   p15, 0, r5, c15, c0, 0          @ No, so restore it
 200         b       cpu_v7_do_resume
 201 ENDPROC(cpu_ca9mp_do_resume)
 202 #endif
 203
 204 #ifdef CONFIG_CPU_PJ4B
 205         globl_equ       cpu_pj4b_switch_mm,     cpu_v7_switch_mm
 206         globl_equ       cpu_pj4b_set_pte_ext,   cpu_v7_set_pte_ext
 207         globl_equ       cpu_pj4b_proc_init,     cpu_v7_proc_init
 208         globl_equ       cpu_pj4b_proc_fin,      cpu_v7_proc_fin
 209         globl_equ       cpu_pj4b_reset,         cpu_v7_reset
 210 #ifdef CONFIG_PJ4B_ERRATA_4742
 211 ENTRY(cpu_pj4b_do_idle)
 212         dsb                                     @ WFI may enter a low-power mode
 213         wfi
 214         dsb                                     @barrier
 215         ret     lr
 216 ENDPROC(cpu_pj4b_do_idle)
 217 #else
 218         globl_equ       cpu_pj4b_do_idle,       cpu_v7_do_idle
 219 #endif
 220         globl_equ       cpu_pj4b_dcache_clean_area,     cpu_v7_dcache_clean_area
 221 #ifdef CONFIG_ARM_CPU_SUSPEND
 222 ENTRY(cpu_pj4b_do_suspend)
 223         stmfd   sp!, {r6 - r10}
 224         mrc     p15, 1, r6, c15, c1, 0  @ save CP15 - extra features
 225         mrc     p15, 1, r7, c15, c2, 0  @ save CP15 - Aux Func Modes Ctrl 0
 226         mrc     p15, 1, r8, c15, c1, 2  @ save CP15 - Aux Debug Modes Ctrl 2
 227         mrc     p15, 1, r9, c15, c1, 1  @ save CP15 - Aux Debug Modes Ctrl 1
 228         mrc     p15, 0, r10, c9, c14, 0  @ save CP15 - PMC
 229         stmia   r0!, {r6 - r10}
 230         ldmfd   sp!, {r6 - r10}
 231         b cpu_v7_do_suspend
 232 ENDPROC(cpu_pj4b_do_suspend)
 233
 234 ENTRY(cpu_pj4b_do_resume)
 235         ldmia   r0!, {r6 - r10}
 236         mcr     p15, 1, r6, c15, c1, 0  @ restore CP15 - extra features
 237         mcr     p15, 1, r7, c15, c2, 0  @ restore CP15 - Aux Func Modes Ctrl 0
 238         mcr     p15, 1, r8, c15, c1, 2  @ restore CP15 - Aux Debug Modes Ctrl 2
 239         mcr     p15, 1, r9, c15, c1, 1  @ restore CP15 - Aux Debug Modes Ctrl 1
 240         mcr     p15, 0, r10, c9, c14, 0  @ restore CP15 - PMC
 241         b cpu_v7_do_resume
 242 ENDPROC(cpu_pj4b_do_resume)
 243 #endif
 244 .globl  cpu_pj4b_suspend_size
 245 .equ    cpu_pj4b_suspend_size, cpu_v7_suspend_size + 4 * 5
 246
 247 #endif
 248
 249 /*
 250  *      __v7_setup
 251  *
 252  *      Initialise TLB, Caches, and MMU state ready to switch the MMU
 253  *      on.  Return in r0 the new CP15 C1 control register setting.
 254  *
 255  *      This should be able to cover all ARMv7 cores.
 256  *
 257  *      It is assumed that:
 258  *      - cache type register is implemented
 259  */
 260 __v7_ca5mp_setup:
 261 __v7_ca9mp_setup:
 262 __v7_cr7mp_setup:
 263         mov     r10, #(1 << 0)                  @ Cache/TLB ops broadcasting
 264         b       1f
 265 __v7_ca7mp_setup:
 266 __v7_ca12mp_setup:
 267 __v7_ca15mp_setup:
 268 __v7_b15mp_setup:
 269 __v7_ca17mp_setup:
 270         mov     r10, #0
 271 1:
 272 #ifdef CONFIG_SMP
 273         ALT_SMP(mrc     p15, 0, r0, c1, c0, 1)
 274         ALT_UP(mov      r0, #(1 << 6))          @ fake it for UP
 275         tst     r0, #(1 << 6)                   @ SMP/nAMP mode enabled?
 276         orreq   r0, r0, #(1 << 6)               @ Enable SMP/nAMP mode
 277         orreq   r0, r0, r10                     @ Enable CPU-specific SMP bits
 278         mcreq   p15, 0, r0, c1, c0, 1
 279 #endif
 280         b       __v7_setup
 281
 282 __v7_pj4b_setup:
 283 #ifdef CONFIG_CPU_PJ4B
 284
 285 /* Auxiliary Debug Modes Control 1 Register */
 286 #define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
 287 #define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
 288 #define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
 289
 290 /* Auxiliary Debug Modes Control 2 Register */
 291 #define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
 292 #define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
 293 #define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
 294 #define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
 295 #define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
 296 #define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
 297                             PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)
 298
 299 /* Auxiliary Functional Modes Control Register 0 */
 300 #define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
 301 #define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
 302 #define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
 303
 304 /* Auxiliary Debug Modes Control 0 Register */
 305 #define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
 306
 307         /* Auxiliary Debug Modes Control 1 Register */
 308         mrc     p15, 1, r0, c15, c1, 1
 309         orr     r0, r0, #PJ4B_CLEAN_LINE
 310         orr     r0, r0, #PJ4B_INTER_PARITY
 311         bic     r0, r0, #PJ4B_STATIC_BP
 312         mcr     p15, 1, r0, c15, c1, 1
 313
 314         /* Auxiliary Debug Modes Control 2 Register */
 315         mrc     p15, 1, r0, c15, c1, 2
 316         bic     r0, r0, #PJ4B_FAST_LDR
 317         orr     r0, r0, #PJ4B_AUX_DBG_CTRL2
 318         mcr     p15, 1, r0, c15, c1, 2
 319
 320         /* Auxiliary Functional Modes Control Register 0 */
 321         mrc     p15, 1, r0, c15, c2, 0
 322 #ifdef CONFIG_SMP
 323         orr     r0, r0, #PJ4B_SMP_CFB
 324 #endif
 325         orr     r0, r0, #PJ4B_L1_PAR_CHK
 326         orr     r0, r0, #PJ4B_BROADCAST_CACHE
 327         mcr     p15, 1, r0, c15, c2, 0
 328
 329         /* Auxiliary Debug Modes Control 0 Register */
 330         mrc     p15, 1, r0, c15, c1, 0
 331         orr     r0, r0, #PJ4B_WFI_WFE
 332         mcr     p15, 1, r0, c15, c1, 0
 333
 334 #endif /* CONFIG_CPU_PJ4B */
 335
 336 __v7_setup:
 337         adr     r12, __v7_setup_stack           @ the local stack
 338         stmia   r12, {r0-r5, r7, r9, r11, lr}
 339         bl      v7_flush_dcache_louis
 340         ldmia   r12, {r0-r5, r7, r9, r11, lr}
 341
 342         mrc     p15, 0, r0, c0, c0, 0           @ read main ID register
 343         and     r10, r0, #0xff000000            @ ARM?
 344         teq     r10, #0x41000000
 345         bne     3f
 346         and     r5, r0, #0x00f00000             @ variant
 347         and     r6, r0, #0x0000000f             @ revision
 348         orr     r6, r6, r5, lsr #20-4           @ combine variant and revision
 349         ubfx    r0, r0, #4, #12                 @ primary part number
 350
 351         /* Cortex-A8 Errata */
 352         ldr     r10, =0x00000c08                @ Cortex-A8 primary part number
 353         teq     r0, r10
 354         bne     2f
 355 #if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
 356
 357         teq     r5, #0x00100000                 @ only present in r1p*
 358         mrceq   p15, 0, r10, c1, c0, 1          @ read aux control register
 359         orreq   r10, r10, #(1 << 6)             @ set IBE to 1
 360         mcreq   p15, 0, r10, c1, c0, 1          @ write aux control register
 361 #endif
 362 #ifdef CONFIG_ARM_ERRATA_458693
 363         teq     r6, #0x20                       @ only present in r2p0
 364         mrceq   p15, 0, r10, c1, c0, 1          @ read aux control register
 365         orreq   r10, r10, #(1 << 5)             @ set L1NEON to 1
 366         orreq   r10, r10, #(1 << 9)             @ set PLDNOP to 1
 367         mcreq   p15, 0, r10, c1, c0, 1          @ write aux control register
 368 #endif
 369 #ifdef CONFIG_ARM_ERRATA_460075
 370         teq     r6, #0x20                       @ only present in r2p0
 371         mrceq   p15, 1, r10, c9, c0, 2          @ read L2 cache aux ctrl register
 372         tsteq   r10, #1 << 22
 373         orreq   r10, r10, #(1 << 22)            @ set the Write Allocate disable bit
 374         mcreq   p15, 1, r10, c9, c0, 2          @ write the L2 cache aux ctrl register
 375 #endif
 376         b       3f
 377
 378         /* Cortex-A9 Errata */
 379 2:      ldr     r10, =0x00000c09                @ Cortex-A9 primary part number
 380         teq     r0, r10
 381         bne     3f
 382 #ifdef CONFIG_ARM_ERRATA_742230
 383         cmp     r6, #0x22                       @ only present up to r2p2
 384         mrcle   p15, 0, r10, c15, c0, 1         @ read diagnostic register
 385         orrle   r10, r10, #1 << 4               @ set bit #4
 386         mcrle   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 387 #endif
 388 #ifdef CONFIG_ARM_ERRATA_742231
 389         teq     r6, #0x20                       @ present in r2p0
 390         teqne   r6, #0x21                       @ present in r2p1
 391         teqne   r6, #0x22                       @ present in r2p2
 392         mrceq   p15, 0, r10, c15, c0, 1         @ read diagnostic register
 393         orreq   r10, r10, #1 << 12              @ set bit #12
 394         orreq   r10, r10, #1 << 22              @ set bit #22
 395         mcreq   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 396 #endif
 397 #ifdef CONFIG_ARM_ERRATA_743622
 398         teq     r5, #0x00200000                 @ only present in r2p*
 399         mrceq   p15, 0, r10, c15, c0, 1         @ read diagnostic register
 400         orreq   r10, r10, #1 << 6               @ set bit #6
 401         mcreq   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 402 #endif
 403 #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
 404         ALT_SMP(cmp r6, #0x30)                  @ present prior to r3p0
 405         ALT_UP_B(1f)
 406         mrclt   p15, 0, r10, c15, c0, 1         @ read diagnostic register
 407         orrlt   r10, r10, #1 << 11              @ set bit #11
 408         mcrlt   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 409 1:
 410 #endif
 411
 412         /* Cortex-A15 Errata */
 413 3:      ldr     r10, =0x00000c0f                @ Cortex-A15 primary part number
 414         teq     r0, r10
 415         bne     4f
 416
 417 #ifdef CONFIG_ARM_ERRATA_773022
 418         cmp     r6, #0x4                        @ only present up to r0p4
 419         mrcle   p15, 0, r10, c1, c0, 1          @ read aux control register
 420         orrle   r10, r10, #1 << 1               @ disable loop buffer
 421         mcrle   p15, 0, r10, c1, c0, 1          @ write aux control register
 422 #endif
 423
 424 4:      mov     r10, #0
 425         mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
 426 #ifdef CONFIG_MMU
 427         mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs
 428         v7_ttb_setup r10, r4, r8, r5            @ TTBCR, TTBRx setup
 429         ldr     r5, =PRRR                       @ PRRR
 430         ldr     r6, =NMRR                       @ NMRR
 431         mcr     p15, 0, r5, c10, c2, 0          @ write PRRR
 432         mcr     p15, 0, r6, c10, c2, 1          @ write NMRR
 433 #endif
 434         dsb                                     @ Complete invalidations
 435 #ifndef CONFIG_ARM_THUMBEE
 436         mrc     p15, 0, r0, c0, c1, 0           @ read ID_PFR0 for ThumbEE
 437         and     r0, r0, #(0xf << 12)            @ ThumbEE enabled field
 438         teq     r0, #(1 << 12)                  @ check if ThumbEE is present
 439         bne     1f
 440         mov     r5, #0
 441         mcr     p14, 6, r5, c1, c0, 0           @ Initialize TEEHBR to 0
 442         mrc     p14, 6, r0, c0, c0, 0           @ load TEECR
 443         orr     r0, r0, #1                      @ set the 1st bit in order to
 444         mcr     p14, 6, r0, c0, c0, 0           @ stop userspace TEEHBR access
 445 1:
 446 #endif
 447         adr     r5, v7_crval
 448         ldmia   r5, {r5, r6}
 449  ARM_BE8(orr    r6, r6, #1 << 25)               @ big-endian page tables
 450 #ifdef CONFIG_SWP_EMULATE
 451         orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
 452         bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
 453 #endif
 454         mrc     p15, 0, r0, c1, c0, 0           @ read control register
 455         bic     r0, r0, r5                      @ clear bits them
 456         orr     r0, r0, r6                      @ set them
 457  THUMB( orr     r0, r0, #1 << 30        )       @ Thumb exceptions
 458         ret     lr                              @ return to head.S:__ret
 459 ENDPROC(__v7_setup)
 460
 461         .align  2
 462 __v7_setup_stack:
 463         .space  4 * 11                          @ 11 registers
 464
 465         __INITDATA
 466
 467         @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
 468         define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
 469 #ifndef CONFIG_ARM_LPAE
 470         define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
 471         define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
 472 #endif
 473 #ifdef CONFIG_CPU_PJ4B
 474         define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
 475 #endif
 476
 477         .section ".rodata"
 478
 479         string  cpu_arch_name, "armv7"
 480         string  cpu_elf_name, "v7"
 481         .align
 482
 483         .section ".proc.info.init", #alloc
 484
 485         /*
 486          * Standard v7 proc info content
 487          */
 488 .macro __v7_proc name, initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
 489         ALT_SMP(.long   PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
 490                         PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
 491         ALT_UP(.long    PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
 492                         PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
 493         .long   PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
 494                 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
 495         initfn  \initfunc, \name
 496         .long   cpu_arch_name
 497         .long   cpu_elf_name
 498         .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
 499                 HWCAP_EDSP | HWCAP_TLS | \hwcaps
 500         .long   cpu_v7_name
 501         .long   \proc_fns
 502         .long   v7wbi_tlb_fns
 503         .long   v6_user_fns
 504         .long   v7_cache_fns
 505 .endm
 506
 507 #ifndef CONFIG_ARM_LPAE
 508         /*
 509          * ARM Ltd. Cortex A5 processor.
 510          */
 511         .type   __v7_ca5mp_proc_info, #object
 512 __v7_ca5mp_proc_info:
 513         .long   0x410fc050
 514         .long   0xff0ffff0
 515         __v7_proc __v7_ca5mp_proc_info, __v7_ca5mp_setup
 516         .size   __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
 517
 518         /*
 519          * ARM Ltd. Cortex A9 processor.
 520          */
 521         .type   __v7_ca9mp_proc_info, #object
 522 __v7_ca9mp_proc_info:
 523         .long   0x410fc090
 524         .long   0xff0ffff0
 525         __v7_proc __v7_ca9mp_proc_info, __v7_ca9mp_setup, proc_fns = ca9mp_processor_functions
 526         .size   __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
 527
 528         /*
 529          * ARM Ltd. Cortex A8 processor.
 530          */
 531         .type   __v7_ca8_proc_info, #object
 532 __v7_ca8_proc_info:
 533         .long   0x410fc080
 534         .long   0xff0ffff0
 535         __v7_proc __v7_ca8_proc_info, __v7_setup, proc_fns = ca8_processor_functions
 536         .size   __v7_ca8_proc_info, . - __v7_ca8_proc_info
 537
 538 #endif  /* CONFIG_ARM_LPAE */
 539
 540         /*
 541          * Marvell PJ4B processor.
 542          */
 543 #ifdef CONFIG_CPU_PJ4B
 544         .type   __v7_pj4b_proc_info, #object
 545 __v7_pj4b_proc_info:
 546         .long   0x560f5800
 547         .long   0xff0fff00
 548         __v7_proc __v7_pj4b_proc_info, __v7_pj4b_setup, proc_fns = pj4b_processor_functions
 549         .size   __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
 550 #endif
 551
 552         /*
 553          * ARM Ltd. Cortex R7 processor.
 554          */
 555         .type   __v7_cr7mp_proc_info, #object
 556 __v7_cr7mp_proc_info:
 557         .long   0x410fc170
 558         .long   0xff0ffff0
 559         __v7_proc __v7_cr7mp_proc_info, __v7_cr7mp_setup
 560         .size   __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
 561
 562         /*
 563          * ARM Ltd. Cortex A7 processor.
 564          */
 565         .type   __v7_ca7mp_proc_info, #object
 566 __v7_ca7mp_proc_info:
 567         .long   0x410fc070
 568         .long   0xff0ffff0
 569         __v7_proc __v7_ca7mp_proc_info, __v7_ca7mp_setup
 570         .size   __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
 571
 572         /*
 573          * ARM Ltd. Cortex A12 processor.
 574          */
 575         .type   __v7_ca12mp_proc_info, #object
 576 __v7_ca12mp_proc_info:
 577         .long   0x410fc0d0
 578         .long   0xff0ffff0
 579         __v7_proc __v7_ca12mp_proc_info, __v7_ca12mp_setup
 580         .size   __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
 581
 582         /*
 583          * ARM Ltd. Cortex A15 processor.
 584          */
 585         .type   __v7_ca15mp_proc_info, #object
 586 __v7_ca15mp_proc_info:
 587         .long   0x410fc0f0
 588         .long   0xff0ffff0
 589         __v7_proc __v7_ca15mp_proc_info, __v7_ca15mp_setup
 590         .size   __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
 591
 592         /*
 593          * Broadcom Corporation Brahma-B15 processor.
 594          */
 595         .type   __v7_b15mp_proc_info, #object
 596 __v7_b15mp_proc_info:
 597         .long   0x420f00f0
 598         .long   0xff0ffff0
 599         __v7_proc __v7_b15mp_proc_info, __v7_b15mp_setup
 600         .size   __v7_b15mp_proc_info, . - __v7_b15mp_proc_info
 601
 602         /*
 603          * ARM Ltd. Cortex A17 processor.
 604          */
 605         .type   __v7_ca17mp_proc_info, #object
 606 __v7_ca17mp_proc_info:
 607         .long   0x410fc0e0
 608         .long   0xff0ffff0
 609         __v7_proc __v7_ca17mp_proc_info, __v7_ca17mp_setup
 610         .size   __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info
 611
 612         /*
 613          * Qualcomm Inc. Krait processors.
 614          */
 615         .type   __krait_proc_info, #object
 616 __krait_proc_info:
 617         .long   0x510f0400              @ Required ID value
 618         .long   0xff0ffc00              @ Mask for ID
 619         /*
 620          * Some Krait processors don't indicate support for SDIV and UDIV
 621          * instructions in the ARM instruction set, even though they actually
 622          * do support them. They also don't indicate support for fused multiply
 623          * instructions even though they actually do support them.
 624          */
 625         __v7_proc __krait_proc_info, __v7_setup, hwcaps = HWCAP_IDIV | HWCAP_VFPv4
 626         .size   __krait_proc_info, . - __krait_proc_info
 627
 628         /*
 629          * Match any ARMv7 processor core.
 630          */
 631         .type   __v7_proc_info, #object
 632 __v7_proc_info:
 633         .long   0x000f0000              @ Required ID value
 634         .long   0x000f0000              @ Mask for ID
 635         __v7_proc __v7_proc_info, __v7_setup
 636         .size   __v7_proc_info, . - __v7_proc_info