arch/arm/mm/proc-xscale.S

   1 /*
   2  *  linux/arch/arm/mm/proc-xscale.S
   3  *
   4  *  Author:     Nicolas Pitre
   5  *  Created:    November 2000
   6  *  Copyright:  (C) 2000, 2001 MontaVista Software Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * MMU functions for the Intel XScale CPUs
  13  *
  14  * 2001 Aug 21:
  15  *      some contributions by Brett Gaines <brett.w.gaines@intel.com>
  16  *      Copyright 2001 by Intel Corp.
  17  *
  18  * 2001 Sep 08:
  19  *      Completely revisited, many important fixes
  20  *      Nicolas Pitre <nico@fluxnic.net>
  21  */
  22
  23 #include <linux/linkage.h>
  24 #include <linux/init.h>
  25 #include <asm/assembler.h>
  26 #include <asm/hwcap.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/pgtable-hwdef.h>
  29 #include <asm/page.h>
  30 #include <asm/ptrace.h>
  31 #include "proc-macros.S"
  32
  33 /*
  34  * This is the maximum size of an area which will be flushed.  If the area
  35  * is larger than this, then we flush the whole cache
  36  */
  37 #define MAX_AREA_SIZE   32768
  38
  39 /*
  40  * the cache line size of the I and D cache
  41  */
  42 #define CACHELINESIZE   32
  43
  44 /*
  45  * the size of the data cache
  46  */
  47 #define CACHESIZE       32768
  48
  49 /*
  50  * Virtual address used to allocate the cache when flushed
  51  *
  52  * This must be an address range which is _never_ used.  It should
  53  * apparently have a mapping in the corresponding page table for
  54  * compatibility with future CPUs that _could_ require it.  For instance we
  55  * don't care.
  56  *
  57  * This must be aligned on a 2*CACHESIZE boundary.  The code selects one of
  58  * the 2 areas in alternance each time the clean_d_cache macro is used.
  59  * Without this the XScale core exhibits cache eviction problems and no one
  60  * knows why.
  61  *
  62  * Reminder: the vector table is located at 0xffff0000-0xffff0fff.
  63  */
  64 #define CLEAN_ADDR      0xfffe0000
  65
  66 /*
  67  * This macro is used to wait for a CP15 write and is needed
  68  * when we have to ensure that the last operation to the co-pro
  69  * was completed before continuing with operation.
  70  */
  71         .macro  cpwait, rd
  72         mrc     p15, 0, \rd, c2, c0, 0          @ arbitrary read of cp15
  73         mov     \rd, \rd                        @ wait for completion
  74         sub     pc, pc, #4                      @ flush instruction pipeline
  75         .endm
  76
  77         .macro  cpwait_ret, lr, rd
  78         mrc     p15, 0, \rd, c2, c0, 0          @ arbitrary read of cp15
  79         sub     pc, \lr, \rd, LSR #32           @ wait for completion and
  80                                                 @ flush instruction pipeline
  81         .endm
  82
  83 /*
  84  * This macro cleans the entire dcache using line allocate.
  85  * The main loop has been unrolled to reduce loop overhead.
  86  * rd and rs are two scratch registers.
  87  */
  88         .macro  clean_d_cache, rd, rs
  89         ldr     \rs, =clean_addr
  90         ldr     \rd, [\rs]
  91         eor     \rd, \rd, #CACHESIZE
  92         str     \rd, [\rs]
  93         add     \rs, \rd, #CACHESIZE
  94 1:      mcr     p15, 0, \rd, c7, c2, 5          @ allocate D cache line
  95         add     \rd, \rd, #CACHELINESIZE
  96         mcr     p15, 0, \rd, c7, c2, 5          @ allocate D cache line
  97         add     \rd, \rd, #CACHELINESIZE
  98         mcr     p15, 0, \rd, c7, c2, 5          @ allocate D cache line
  99         add     \rd, \rd, #CACHELINESIZE
 100         mcr     p15, 0, \rd, c7, c2, 5          @ allocate D cache line
 101         add     \rd, \rd, #CACHELINESIZE
 102         teq     \rd, \rs
 103         bne     1b
 104         .endm
 105
 106         .data
 107 clean_addr:     .word   CLEAN_ADDR
 108
 109         .text
 110
 111 /*
 112  * cpu_xscale_proc_init()
 113  *
 114  * Nothing too exciting at the moment
 115  */
 116 ENTRY(cpu_xscale_proc_init)
 117         @ enable write buffer coalescing. Some bootloader disable it
 118         mrc     p15, 0, r1, c1, c0, 1
 119         bic     r1, r1, #1
 120         mcr     p15, 0, r1, c1, c0, 1
 121         mov     pc, lr
 122
 123 /*
 124  * cpu_xscale_proc_fin()
 125  */
 126 ENTRY(cpu_xscale_proc_fin)
 127         str     lr, [sp, #-4]!
 128         mov     r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
 129         msr     cpsr_c, r0
 130         bl      xscale_flush_kern_cache_all     @ clean caches
 131         mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
 132         bic     r0, r0, #0x1800                 @ ...IZ...........
 133         bic     r0, r0, #0x0006                 @ .............CA.
 134         mcr     p15, 0, r0, c1, c0, 0           @ disable caches
 135         ldr     pc, [sp], #4
 136
 137 /*
 138  * cpu_xscale_reset(loc)
 139  *
 140  * Perform a soft reset of the system.  Put the CPU into the
 141  * same state as it would be if it had been reset, and branch
 142  * to what would be the reset vector.
 143  *
 144  * loc: location to jump to for soft reset
 145  *
 146  * Beware PXA270 erratum E7.
 147  */
 148         .align  5
 149 ENTRY(cpu_xscale_reset)
 150         mov     r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
 151         msr     cpsr_c, r1                      @ reset CPSR
 152         mcr     p15, 0, r1, c10, c4, 1          @ unlock I-TLB
 153         mcr     p15, 0, r1, c8, c5, 0           @ invalidate I-TLB
 154         mrc     p15, 0, r1, c1, c0, 0           @ ctrl register
 155         bic     r1, r1, #0x0086                 @ ........B....CA.
 156         bic     r1, r1, #0x3900                 @ ..VIZ..S........
 157         sub     pc, pc, #4                      @ flush pipeline
 158         @ *** cache line aligned ***
 159         mcr     p15, 0, r1, c1, c0, 0           @ ctrl register
 160         bic     r1, r1, #0x0001                 @ ...............M
 161         mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches & BTB
 162         mcr     p15, 0, r1, c1, c0, 0           @ ctrl register
 163         @ CAUTION: MMU turned off from this point. We count on the pipeline
 164         @ already containing those two last instructions to survive.
 165         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
 166         mov     pc, r0
 167
 168 /*
 169  * cpu_xscale_do_idle()
 170  *
 171  * Cause the processor to idle
 172  *
 173  * For now we do nothing but go to idle mode for every case
 174  *
 175  * XScale supports clock switching, but using idle mode support
 176  * allows external hardware to react to system state changes.
 177  */
 178         .align  5
 179
 180 ENTRY(cpu_xscale_do_idle)
 181         mov     r0, #1
 182         mcr     p14, 0, r0, c7, c0, 0           @ Go to IDLE
 183         mov     pc, lr
 184
 185 /* ================================= CACHE ================================ */
 186
 187 /*
 188  *      flush_user_cache_all()
 189  *
 190  *      Invalidate all cache entries in a particular address
 191  *      space.
 192  */
 193 ENTRY(xscale_flush_user_cache_all)
 194         /* FALLTHROUGH */
 195
 196 /*
 197  *      flush_kern_cache_all()
 198  *
 199  *      Clean and invalidate the entire cache.
 200  */
 201 ENTRY(xscale_flush_kern_cache_all)
 202         mov     r2, #VM_EXEC
 203         mov     ip, #0
 204 __flush_whole_cache:
 205         clean_d_cache r0, r1
 206         tst     r2, #VM_EXEC
 207         mcrne   p15, 0, ip, c7, c5, 0           @ Invalidate I cache & BTB
 208         mcrne   p15, 0, ip, c7, c10, 4          @ Drain Write (& Fill) Buffer
 209         mov     pc, lr
 210
 211 /*
 212  *      flush_user_cache_range(start, end, vm_flags)
 213  *
 214  *      Invalidate a range of cache entries in the specified
 215  *      address space.
 216  *
 217  *      - start - start address (may not be aligned)
 218  *      - end   - end address (exclusive, may not be aligned)
 219  *      - vma   - vma_area_struct describing address space
 220  */
 221         .align  5
 222 ENTRY(xscale_flush_user_cache_range)
 223         mov     ip, #0
 224         sub     r3, r1, r0                      @ calculate total size
 225         cmp     r3, #MAX_AREA_SIZE
 226         bhs     __flush_whole_cache
 227
 228 1:      tst     r2, #VM_EXEC
 229         mcrne   p15, 0, r0, c7, c5, 1           @ Invalidate I cache line
 230         mcr     p15, 0, r0, c7, c10, 1          @ Clean D cache line
 231         mcr     p15, 0, r0, c7, c6, 1           @ Invalidate D cache line
 232         add     r0, r0, #CACHELINESIZE
 233         cmp     r0, r1
 234         blo     1b
 235         tst     r2, #VM_EXEC
 236         mcrne   p15, 0, ip, c7, c5, 6           @ Invalidate BTB
 237         mcrne   p15, 0, ip, c7, c10, 4          @ Drain Write (& Fill) Buffer
 238         mov     pc, lr
 239
 240 /*
 241  *      coherent_kern_range(start, end)
 242  *
 243  *      Ensure coherency between the Icache and the Dcache in the
 244  *      region described by start.  If you have non-snooping
 245  *      Harvard caches, you need to implement this function.
 246  *
 247  *      - start  - virtual start address
 248  *      - end    - virtual end address
 249  *
 250  *      Note: single I-cache line invalidation isn't used here since
 251  *      it also trashes the mini I-cache used by JTAG debuggers.
 252  */
 253 ENTRY(xscale_coherent_kern_range)
 254         bic     r0, r0, #CACHELINESIZE - 1
 255 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 256         add     r0, r0, #CACHELINESIZE
 257         cmp     r0, r1
 258         blo     1b
 259         mov     r0, #0
 260         mcr     p15, 0, r0, c7, c5, 0           @ Invalidate I cache & BTB
 261         mcr     p15, 0, r0, c7, c10, 4          @ Drain Write (& Fill) Buffer
 262         mov     pc, lr
 263
 264 /*
 265  *      coherent_user_range(start, end)
 266  *
 267  *      Ensure coherency between the Icache and the Dcache in the
 268  *      region described by start.  If you have non-snooping
 269  *      Harvard caches, you need to implement this function.
 270  *
 271  *      - start  - virtual start address
 272  *      - end    - virtual end address
 273  */
 274 ENTRY(xscale_coherent_user_range)
 275         bic     r0, r0, #CACHELINESIZE - 1
 276 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 277         mcr     p15, 0, r0, c7, c5, 1           @ Invalidate I cache entry
 278         add     r0, r0, #CACHELINESIZE
 279         cmp     r0, r1
 280         blo     1b
 281         mov     r0, #0
 282         mcr     p15, 0, r0, c7, c5, 6           @ Invalidate BTB
 283         mcr     p15, 0, r0, c7, c10, 4          @ Drain Write (& Fill) Buffer
 284         mov     pc, lr
 285
 286 /*
 287  *      flush_kern_dcache_area(void *addr, size_t size)
 288  *
 289  *      Ensure no D cache aliasing occurs, either with itself or
 290  *      the I cache
 291  *
 292  *      - addr  - kernel address
 293  *      - size  - region size
 294  */
 295 ENTRY(xscale_flush_kern_dcache_area)
 296         add     r1, r0, r1
 297 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 298         mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
 299         add     r0, r0, #CACHELINESIZE
 300         cmp     r0, r1
 301         blo     1b
 302         mov     r0, #0
 303         mcr     p15, 0, r0, c7, c5, 0           @ Invalidate I cache & BTB
 304         mcr     p15, 0, r0, c7, c10, 4          @ Drain Write (& Fill) Buffer
 305         mov     pc, lr
 306
 307 /*
 308  *      dma_inv_range(start, end)
 309  *
 310  *      Invalidate (discard) the specified virtual address range.
 311  *      May not write back any entries.  If 'start' or 'end'
 312  *      are not cache line aligned, those lines must be written
 313  *      back.
 314  *
 315  *      - start  - virtual start address
 316  *      - end    - virtual end address
 317  */
 318 ENTRY(xscale_dma_inv_range)
 319         tst     r0, #CACHELINESIZE - 1
 320         bic     r0, r0, #CACHELINESIZE - 1
 321         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
 322         tst     r1, #CACHELINESIZE - 1
 323         mcrne   p15, 0, r1, c7, c10, 1          @ clean D entry
 324 1:      mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
 325         add     r0, r0, #CACHELINESIZE
 326         cmp     r0, r1
 327         blo     1b
 328         mcr     p15, 0, r0, c7, c10, 4          @ Drain Write (& Fill) Buffer
 329         mov     pc, lr
 330
 331 /*
 332  *      dma_clean_range(start, end)
 333  *
 334  *      Clean the specified virtual address range.
 335  *
 336  *      - start  - virtual start address
 337  *      - end    - virtual end address
 338  */
 339 ENTRY(xscale_dma_clean_range)
 340         bic     r0, r0, #CACHELINESIZE - 1
 341 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 342         add     r0, r0, #CACHELINESIZE
 343         cmp     r0, r1
 344         blo     1b
 345         mcr     p15, 0, r0, c7, c10, 4          @ Drain Write (& Fill) Buffer
 346         mov     pc, lr
 347
 348 /*
 349  *      dma_flush_range(start, end)
 350  *
 351  *      Clean and invalidate the specified virtual address range.
 352  *
 353  *      - start  - virtual start address
 354  *      - end    - virtual end address
 355  */
 356 ENTRY(xscale_dma_flush_range)
 357         bic     r0, r0, #CACHELINESIZE - 1
 358 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 359         mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
 360         add     r0, r0, #CACHELINESIZE
 361         cmp     r0, r1
 362         blo     1b
 363         mcr     p15, 0, r0, c7, c10, 4          @ Drain Write (& Fill) Buffer
 364         mov     pc, lr
 365
 366 /*
 367  *      dma_map_area(start, size, dir)
 368  *      - start - kernel virtual start address
 369  *      - size  - size of region
 370  *      - dir   - DMA direction
 371  */
 372 ENTRY(xscale_dma_map_area)
 373         add     r1, r1, r0
 374         cmp     r2, #DMA_TO_DEVICE
 375         beq     xscale_dma_clean_range
 376         bcs     xscale_dma_inv_range
 377         b       xscale_dma_flush_range
 378 ENDPROC(xscale_dma_map_area)
 379
 380 /*
 381  *      dma_map_area(start, size, dir)
 382  *      - start - kernel virtual start address
 383  *      - size  - size of region
 384  *      - dir   - DMA direction
 385  */
 386 ENTRY(xscale_dma_a0_map_area)
 387         add     r1, r1, r0
 388         teq     r2, #DMA_TO_DEVICE
 389         beq     xscale_dma_clean_range
 390         b       xscale_dma_flush_range
 391 ENDPROC(xscsale_dma_a0_map_area)
 392
 393 /*
 394  *      dma_unmap_area(start, size, dir)
 395  *      - start - kernel virtual start address
 396  *      - size  - size of region
 397  *      - dir   - DMA direction
 398  */
 399 ENTRY(xscale_dma_unmap_area)
 400         mov     pc, lr
 401 ENDPROC(xscale_dma_unmap_area)
 402
 403 ENTRY(xscale_cache_fns)
 404         .long   xscale_flush_kern_cache_all
 405         .long   xscale_flush_user_cache_all
 406         .long   xscale_flush_user_cache_range
 407         .long   xscale_coherent_kern_range
 408         .long   xscale_coherent_user_range
 409         .long   xscale_flush_kern_dcache_area
 410         .long   xscale_dma_map_area
 411         .long   xscale_dma_unmap_area
 412         .long   xscale_dma_inv_range
 413         .long   xscale_dma_clean_range
 414         .long   xscale_dma_flush_range
 415
 416 /*
 417  * On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't
 418  * clear the dirty bits, which means that if we invalidate a dirty line,
 419  * the dirty data can still be written back to external memory later on.
 420  *
 421  * The recommended workaround is to always do a clean D-cache line before
 422  * doing an invalidate D-cache line, so on the affected processors,
 423  * dma_inv_range() is implemented as dma_flush_range().
 424  *
 425  * See erratum #25 of "Intel 80200 Processor Specification Update",
 426  * revision January 22, 2003, available at:
 427  *     http://www.intel.com/design/iio/specupdt/273415.htm
 428  */
 429 ENTRY(xscale_80200_A0_A1_cache_fns)
 430         .long   xscale_flush_kern_cache_all
 431         .long   xscale_flush_user_cache_all
 432         .long   xscale_flush_user_cache_range
 433         .long   xscale_coherent_kern_range
 434         .long   xscale_coherent_user_range
 435         .long   xscale_flush_kern_dcache_area
 436         .long   xscale_dma_a0_map_area
 437         .long   xscale_dma_unmap_area
 438         .long   xscale_dma_flush_range
 439         .long   xscale_dma_clean_range
 440         .long   xscale_dma_flush_range
 441
 442 ENTRY(cpu_xscale_dcache_clean_area)
 443 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
 444         add     r0, r0, #CACHELINESIZE
 445         subs    r1, r1, #CACHELINESIZE
 446         bhi     1b
 447         mov     pc, lr
 448
 449 /* =============================== PageTable ============================== */
 450
 451 /*
 452  * cpu_xscale_switch_mm(pgd)
 453  *
 454  * Set the translation base pointer to be as described by pgd.
 455  *
 456  * pgd: new page tables
 457  */
 458         .align  5
 459 ENTRY(cpu_xscale_switch_mm)
 460         clean_d_cache r1, r2
 461         mcr     p15, 0, ip, c7, c5, 0           @ Invalidate I cache & BTB
 462         mcr     p15, 0, ip, c7, c10, 4          @ Drain Write (& Fill) Buffer
 463         mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
 464         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
 465         cpwait_ret lr, ip
 466
 467 /*
 468  * cpu_xscale_set_pte_ext(ptep, pte, ext)
 469  *
 470  * Set a PTE and flush it out
 471  *
 472  * Errata 40: must set memory to write-through for user read-only pages.
 473  */
 474 cpu_xscale_mt_table:
 475         .long   0x00                                            @ L_PTE_MT_UNCACHED
 476         .long   PTE_BUFFERABLE                                  @ L_PTE_MT_BUFFERABLE
 477         .long   PTE_CACHEABLE                                   @ L_PTE_MT_WRITETHROUGH
 478         .long   PTE_CACHEABLE | PTE_BUFFERABLE                  @ L_PTE_MT_WRITEBACK
 479         .long   PTE_EXT_TEX(1) | PTE_BUFFERABLE                 @ L_PTE_MT_DEV_SHARED
 480         .long   0x00                                            @ unused
 481         .long   PTE_EXT_TEX(1) | PTE_CACHEABLE                  @ L_PTE_MT_MINICACHE
 482         .long   PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
 483         .long   0x00                                            @ unused
 484         .long   PTE_BUFFERABLE                                  @ L_PTE_MT_DEV_WC
 485         .long   0x00                                            @ unused
 486         .long   PTE_CACHEABLE | PTE_BUFFERABLE                  @ L_PTE_MT_DEV_CACHED
 487         .long   0x00                                            @ L_PTE_MT_DEV_NONSHARED
 488         .long   0x00                                            @ unused
 489         .long   0x00                                            @ unused
 490         .long   0x00                                            @ unused
 491
 492         .align  5
 493 ENTRY(cpu_xscale_set_pte_ext)
 494         xscale_set_pte_ext_prologue
 495
 496         @
 497         @ Erratum 40: must set memory to write-through for user read-only pages
 498         @
 499         and     ip, r1, #(L_PTE_MT_MASK | L_PTE_USER | L_PTE_WRITE) & ~(4 << 2)
 500         teq     ip, #L_PTE_MT_WRITEBACK | L_PTE_USER
 501
 502         moveq   r1, #L_PTE_MT_WRITETHROUGH
 503         and     r1, r1, #L_PTE_MT_MASK
 504         adr     ip, cpu_xscale_mt_table
 505         ldr     ip, [ip, r1]
 506         bic     r2, r2, #0x0c
 507         orr     r2, r2, ip
 508
 509         xscale_set_pte_ext_epilogue
 510         mov     pc, lr
 511
 512
 513         .ltorg
 514
 515         .align
 516
 517         __INIT
 518
 519         .type   __xscale_setup, #function
 520 __xscale_setup:
 521         mcr     p15, 0, ip, c7, c7, 0           @ invalidate I, D caches & BTB
 522         mcr     p15, 0, ip, c7, c10, 4          @ Drain Write (& Fill) Buffer
 523         mcr     p15, 0, ip, c8, c7, 0           @ invalidate I, D TLBs
 524         mov     r0, #1 << 6                     @ cp6 for IOP3xx and Bulverde
 525         orr     r0, r0, #1 << 13                @ Its undefined whether this
 526         mcr     p15, 0, r0, c15, c1, 0          @ affects USR or SVC modes
 527
 528         adr     r5, xscale_crval
 529         ldmia   r5, {r5, r6}
 530         mrc     p15, 0, r0, c1, c0, 0           @ get control register
 531         bic     r0, r0, r5
 532         orr     r0, r0, r6
 533         mov     pc, lr
 534         .size   __xscale_setup, . - __xscale_setup
 535
 536         /*
 537          *  R
 538          * .RVI ZFRS BLDP WCAM
 539          * ..11 1.01 .... .101
 540          *
 541          */
 542         .type   xscale_crval, #object
 543 xscale_crval:
 544         crval   clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900
 545
 546         __INITDATA
 547
 548 /*
 549  * Purpose : Function pointers used to access above functions - all calls
 550  *           come through these
 551  */
 552
 553         .type   xscale_processor_functions, #object
 554 ENTRY(xscale_processor_functions)
 555         .word   v5t_early_abort
 556         .word   legacy_pabort
 557         .word   cpu_xscale_proc_init
 558         .word   cpu_xscale_proc_fin
 559         .word   cpu_xscale_reset
 560         .word   cpu_xscale_do_idle
 561         .word   cpu_xscale_dcache_clean_area
 562         .word   cpu_xscale_switch_mm
 563         .word   cpu_xscale_set_pte_ext
 564         .size   xscale_processor_functions, . - xscale_processor_functions
 565
 566         .section ".rodata"
 567
 568         .type   cpu_arch_name, #object
 569 cpu_arch_name:
 570         .asciz  "armv5te"
 571         .size   cpu_arch_name, . - cpu_arch_name
 572
 573         .type   cpu_elf_name, #object
 574 cpu_elf_name:
 575         .asciz  "v5"
 576         .size   cpu_elf_name, . - cpu_elf_name
 577
 578         .type   cpu_80200_A0_A1_name, #object
 579 cpu_80200_A0_A1_name:
 580         .asciz  "XScale-80200 A0/A1"
 581         .size   cpu_80200_A0_A1_name, . - cpu_80200_A0_A1_name
 582
 583         .type   cpu_80200_name, #object
 584 cpu_80200_name:
 585         .asciz  "XScale-80200"
 586         .size   cpu_80200_name, . - cpu_80200_name
 587
 588         .type   cpu_80219_name, #object
 589 cpu_80219_name:
 590         .asciz  "XScale-80219"
 591         .size   cpu_80219_name, . - cpu_80219_name
 592
 593         .type   cpu_8032x_name, #object
 594 cpu_8032x_name:
 595         .asciz  "XScale-IOP8032x Family"
 596         .size   cpu_8032x_name, . - cpu_8032x_name
 597
 598         .type   cpu_8033x_name, #object
 599 cpu_8033x_name:
 600         .asciz  "XScale-IOP8033x Family"
 601         .size   cpu_8033x_name, . - cpu_8033x_name
 602
 603         .type   cpu_pxa250_name, #object
 604 cpu_pxa250_name:
 605         .asciz  "XScale-PXA250"
 606         .size   cpu_pxa250_name, . - cpu_pxa250_name
 607
 608         .type   cpu_pxa210_name, #object
 609 cpu_pxa210_name:
 610         .asciz  "XScale-PXA210"
 611         .size   cpu_pxa210_name, . - cpu_pxa210_name
 612
 613         .type   cpu_ixp42x_name, #object
 614 cpu_ixp42x_name:
 615         .asciz  "XScale-IXP42x Family"
 616         .size   cpu_ixp42x_name, . - cpu_ixp42x_name
 617
 618         .type   cpu_ixp43x_name, #object
 619 cpu_ixp43x_name:
 620         .asciz  "XScale-IXP43x Family"
 621         .size   cpu_ixp43x_name, . - cpu_ixp43x_name
 622
 623         .type   cpu_ixp46x_name, #object
 624 cpu_ixp46x_name:
 625         .asciz  "XScale-IXP46x Family"
 626         .size   cpu_ixp46x_name, . - cpu_ixp46x_name
 627
 628         .type   cpu_ixp2400_name, #object
 629 cpu_ixp2400_name:
 630         .asciz  "XScale-IXP2400"
 631         .size   cpu_ixp2400_name, . - cpu_ixp2400_name
 632
 633         .type   cpu_ixp2800_name, #object
 634 cpu_ixp2800_name:
 635         .asciz  "XScale-IXP2800"
 636         .size   cpu_ixp2800_name, . - cpu_ixp2800_name
 637
 638         .type   cpu_pxa255_name, #object
 639 cpu_pxa255_name:
 640         .asciz  "XScale-PXA255"
 641         .size   cpu_pxa255_name, . - cpu_pxa255_name
 642
 643         .type   cpu_pxa270_name, #object
 644 cpu_pxa270_name:
 645         .asciz  "XScale-PXA270"
 646         .size   cpu_pxa270_name, . - cpu_pxa270_name
 647
 648         .align
 649
 650         .section ".proc.info.init", #alloc, #execinstr
 651
 652         .type   __80200_A0_A1_proc_info,#object
 653 __80200_A0_A1_proc_info:
 654         .long   0x69052000
 655         .long   0xfffffffe
 656         .long   PMD_TYPE_SECT | \
 657                 PMD_SECT_BUFFERABLE | \
 658                 PMD_SECT_CACHEABLE | \
 659                 PMD_SECT_AP_WRITE | \
 660                 PMD_SECT_AP_READ
 661         .long   PMD_TYPE_SECT | \
 662                 PMD_SECT_AP_WRITE | \
 663                 PMD_SECT_AP_READ
 664         b       __xscale_setup
 665         .long   cpu_arch_name
 666         .long   cpu_elf_name
 667         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 668         .long   cpu_80200_name
 669         .long   xscale_processor_functions
 670         .long   v4wbi_tlb_fns
 671         .long   xscale_mc_user_fns
 672         .long   xscale_80200_A0_A1_cache_fns
 673         .size   __80200_A0_A1_proc_info, . - __80200_A0_A1_proc_info
 674
 675         .type   __80200_proc_info,#object
 676 __80200_proc_info:
 677         .long   0x69052000
 678         .long   0xfffffff0
 679         .long   PMD_TYPE_SECT | \
 680                 PMD_SECT_BUFFERABLE | \
 681                 PMD_SECT_CACHEABLE | \
 682                 PMD_SECT_AP_WRITE | \
 683                 PMD_SECT_AP_READ
 684         .long   PMD_TYPE_SECT | \
 685                 PMD_SECT_AP_WRITE | \
 686                 PMD_SECT_AP_READ
 687         b       __xscale_setup
 688         .long   cpu_arch_name
 689         .long   cpu_elf_name
 690         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 691         .long   cpu_80200_name
 692         .long   xscale_processor_functions
 693         .long   v4wbi_tlb_fns
 694         .long   xscale_mc_user_fns
 695         .long   xscale_cache_fns
 696         .size   __80200_proc_info, . - __80200_proc_info
 697
 698         .type   __80219_proc_info,#object
 699 __80219_proc_info:
 700         .long   0x69052e20
 701         .long   0xffffffe0
 702         .long   PMD_TYPE_SECT | \
 703                 PMD_SECT_BUFFERABLE | \
 704                 PMD_SECT_CACHEABLE | \
 705                 PMD_SECT_AP_WRITE | \
 706                 PMD_SECT_AP_READ
 707         .long   PMD_TYPE_SECT | \
 708                 PMD_SECT_AP_WRITE | \
 709                 PMD_SECT_AP_READ
 710         b       __xscale_setup
 711         .long   cpu_arch_name
 712         .long   cpu_elf_name
 713         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 714         .long   cpu_80219_name
 715         .long   xscale_processor_functions
 716         .long   v4wbi_tlb_fns
 717         .long   xscale_mc_user_fns
 718         .long   xscale_cache_fns
 719         .size   __80219_proc_info, . - __80219_proc_info
 720
 721         .type   __8032x_proc_info,#object
 722 __8032x_proc_info:
 723         .long   0x69052420
 724         .long   0xfffff7e0
 725         .long   PMD_TYPE_SECT | \
 726                 PMD_SECT_BUFFERABLE | \
 727                 PMD_SECT_CACHEABLE | \
 728                 PMD_SECT_AP_WRITE | \
 729                 PMD_SECT_AP_READ
 730         .long   PMD_TYPE_SECT | \
 731                 PMD_SECT_AP_WRITE | \
 732                 PMD_SECT_AP_READ
 733         b       __xscale_setup
 734         .long   cpu_arch_name
 735         .long   cpu_elf_name
 736         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 737         .long   cpu_8032x_name
 738         .long   xscale_processor_functions
 739         .long   v4wbi_tlb_fns
 740         .long   xscale_mc_user_fns
 741         .long   xscale_cache_fns
 742         .size   __8032x_proc_info, . - __8032x_proc_info
 743
 744         .type   __8033x_proc_info,#object
 745 __8033x_proc_info:
 746         .long   0x69054010
 747         .long   0xfffffd30
 748         .long   PMD_TYPE_SECT | \
 749                 PMD_SECT_BUFFERABLE | \
 750                 PMD_SECT_CACHEABLE | \
 751                 PMD_SECT_AP_WRITE | \
 752                 PMD_SECT_AP_READ
 753         .long   PMD_TYPE_SECT | \
 754                 PMD_SECT_AP_WRITE | \
 755                 PMD_SECT_AP_READ
 756         b       __xscale_setup
 757         .long   cpu_arch_name
 758         .long   cpu_elf_name
 759         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 760         .long   cpu_8033x_name
 761         .long   xscale_processor_functions
 762         .long   v4wbi_tlb_fns
 763         .long   xscale_mc_user_fns
 764         .long   xscale_cache_fns
 765         .size   __8033x_proc_info, . - __8033x_proc_info
 766
 767         .type   __pxa250_proc_info,#object
 768 __pxa250_proc_info:
 769         .long   0x69052100
 770         .long   0xfffff7f0
 771         .long   PMD_TYPE_SECT | \
 772                 PMD_SECT_BUFFERABLE | \
 773                 PMD_SECT_CACHEABLE | \
 774                 PMD_SECT_AP_WRITE | \
 775                 PMD_SECT_AP_READ
 776         .long   PMD_TYPE_SECT | \
 777                 PMD_SECT_AP_WRITE | \
 778                 PMD_SECT_AP_READ
 779         b       __xscale_setup
 780         .long   cpu_arch_name
 781         .long   cpu_elf_name
 782         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 783         .long   cpu_pxa250_name
 784         .long   xscale_processor_functions
 785         .long   v4wbi_tlb_fns
 786         .long   xscale_mc_user_fns
 787         .long   xscale_cache_fns
 788         .size   __pxa250_proc_info, . - __pxa250_proc_info
 789
 790         .type   __pxa210_proc_info,#object
 791 __pxa210_proc_info:
 792         .long   0x69052120
 793         .long   0xfffff3f0
 794         .long   PMD_TYPE_SECT | \
 795                 PMD_SECT_BUFFERABLE | \
 796                 PMD_SECT_CACHEABLE | \
 797                 PMD_SECT_AP_WRITE | \
 798                 PMD_SECT_AP_READ
 799         .long   PMD_TYPE_SECT | \
 800                 PMD_SECT_AP_WRITE | \
 801                 PMD_SECT_AP_READ
 802         b       __xscale_setup
 803         .long   cpu_arch_name
 804         .long   cpu_elf_name
 805         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 806         .long   cpu_pxa210_name
 807         .long   xscale_processor_functions
 808         .long   v4wbi_tlb_fns
 809         .long   xscale_mc_user_fns
 810         .long   xscale_cache_fns
 811         .size   __pxa210_proc_info, . - __pxa210_proc_info
 812
 813         .type   __ixp2400_proc_info, #object
 814 __ixp2400_proc_info:
 815         .long   0x69054190
 816         .long   0xfffffff0
 817         .long   PMD_TYPE_SECT | \
 818                 PMD_SECT_BUFFERABLE | \
 819                 PMD_SECT_CACHEABLE | \
 820                 PMD_SECT_AP_WRITE | \
 821                 PMD_SECT_AP_READ
 822         .long   PMD_TYPE_SECT | \
 823                 PMD_SECT_AP_WRITE | \
 824                 PMD_SECT_AP_READ
 825         b       __xscale_setup
 826         .long   cpu_arch_name
 827         .long   cpu_elf_name
 828         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 829         .long   cpu_ixp2400_name
 830         .long   xscale_processor_functions
 831         .long   v4wbi_tlb_fns
 832         .long   xscale_mc_user_fns
 833         .long   xscale_cache_fns
 834         .size   __ixp2400_proc_info, . - __ixp2400_proc_info
 835
 836         .type   __ixp2800_proc_info, #object
 837 __ixp2800_proc_info:
 838         .long   0x690541a0
 839         .long   0xfffffff0
 840         .long   PMD_TYPE_SECT | \
 841                 PMD_SECT_BUFFERABLE | \
 842                 PMD_SECT_CACHEABLE | \
 843                 PMD_SECT_AP_WRITE | \
 844                 PMD_SECT_AP_READ
 845         .long   PMD_TYPE_SECT | \
 846                 PMD_SECT_AP_WRITE | \
 847                 PMD_SECT_AP_READ
 848         b       __xscale_setup
 849         .long   cpu_arch_name
 850         .long   cpu_elf_name
 851         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 852         .long   cpu_ixp2800_name
 853         .long   xscale_processor_functions
 854         .long   v4wbi_tlb_fns
 855         .long   xscale_mc_user_fns
 856         .long   xscale_cache_fns
 857         .size   __ixp2800_proc_info, . - __ixp2800_proc_info
 858
 859         .type   __ixp42x_proc_info, #object
 860 __ixp42x_proc_info:
 861         .long   0x690541c0
 862         .long   0xffffffc0
 863         .long   PMD_TYPE_SECT | \
 864                 PMD_SECT_BUFFERABLE | \
 865                 PMD_SECT_CACHEABLE | \
 866                 PMD_SECT_AP_WRITE | \
 867                 PMD_SECT_AP_READ
 868         .long   PMD_TYPE_SECT | \
 869                 PMD_SECT_AP_WRITE | \
 870                 PMD_SECT_AP_READ
 871         b       __xscale_setup
 872         .long   cpu_arch_name
 873         .long   cpu_elf_name
 874         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 875         .long   cpu_ixp42x_name
 876         .long   xscale_processor_functions
 877         .long   v4wbi_tlb_fns
 878         .long   xscale_mc_user_fns
 879         .long   xscale_cache_fns
 880         .size   __ixp42x_proc_info, . - __ixp42x_proc_info
 881
 882         .type   __ixp43x_proc_info, #object
 883 __ixp43x_proc_info:
 884         .long   0x69054040
 885         .long   0xfffffff0
 886         .long   PMD_TYPE_SECT | \
 887                 PMD_SECT_BUFFERABLE | \
 888                 PMD_SECT_CACHEABLE | \
 889                 PMD_SECT_AP_WRITE | \
 890                 PMD_SECT_AP_READ
 891         .long   PMD_TYPE_SECT | \
 892                 PMD_SECT_AP_WRITE | \
 893                 PMD_SECT_AP_READ
 894         b       __xscale_setup
 895         .long   cpu_arch_name
 896         .long   cpu_elf_name
 897         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 898         .long   cpu_ixp43x_name
 899         .long   xscale_processor_functions
 900         .long   v4wbi_tlb_fns
 901         .long   xscale_mc_user_fns
 902         .long   xscale_cache_fns
 903         .size   __ixp43x_proc_info, . - __ixp43x_proc_info
 904
 905         .type   __ixp46x_proc_info, #object
 906 __ixp46x_proc_info:
 907         .long   0x69054200
 908         .long   0xffffff00
 909         .long   PMD_TYPE_SECT | \
 910                 PMD_SECT_BUFFERABLE | \
 911                 PMD_SECT_CACHEABLE | \
 912                 PMD_SECT_AP_WRITE | \
 913                 PMD_SECT_AP_READ
 914         .long   PMD_TYPE_SECT | \
 915                 PMD_SECT_AP_WRITE | \
 916                 PMD_SECT_AP_READ
 917         b       __xscale_setup
 918         .long   cpu_arch_name
 919         .long   cpu_elf_name
 920         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 921         .long   cpu_ixp46x_name
 922         .long   xscale_processor_functions
 923         .long   v4wbi_tlb_fns
 924         .long   xscale_mc_user_fns
 925         .long   xscale_cache_fns
 926         .size   __ixp46x_proc_info, . - __ixp46x_proc_info
 927
 928         .type   __pxa255_proc_info,#object
 929 __pxa255_proc_info:
 930         .long   0x69052d00
 931         .long   0xfffffff0
 932         .long   PMD_TYPE_SECT | \
 933                 PMD_SECT_BUFFERABLE | \
 934                 PMD_SECT_CACHEABLE | \
 935                 PMD_SECT_AP_WRITE | \
 936                 PMD_SECT_AP_READ
 937         .long   PMD_TYPE_SECT | \
 938                 PMD_SECT_AP_WRITE | \
 939                 PMD_SECT_AP_READ
 940         b       __xscale_setup
 941         .long   cpu_arch_name
 942         .long   cpu_elf_name
 943         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 944         .long   cpu_pxa255_name
 945         .long   xscale_processor_functions
 946         .long   v4wbi_tlb_fns
 947         .long   xscale_mc_user_fns
 948         .long   xscale_cache_fns
 949         .size   __pxa255_proc_info, . - __pxa255_proc_info
 950
 951         .type   __pxa270_proc_info,#object
 952 __pxa270_proc_info:
 953         .long   0x69054110
 954         .long   0xfffffff0
 955         .long   PMD_TYPE_SECT | \
 956                 PMD_SECT_BUFFERABLE | \
 957                 PMD_SECT_CACHEABLE | \
 958                 PMD_SECT_AP_WRITE | \
 959                 PMD_SECT_AP_READ
 960         .long   PMD_TYPE_SECT | \
 961                 PMD_SECT_AP_WRITE | \
 962                 PMD_SECT_AP_READ
 963         b       __xscale_setup
 964         .long   cpu_arch_name
 965         .long   cpu_elf_name
 966         .long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
 967         .long   cpu_pxa270_name
 968         .long   xscale_processor_functions
 969         .long   v4wbi_tlb_fns
 970         .long   xscale_mc_user_fns
 971         .long   xscale_cache_fns
 972         .size   __pxa270_proc_info, . - __pxa270_proc_info
 973