arch/arm/plat-iop/time.c

   1 /*
   2  * arch/arm/plat-iop/time.c
   3  *
   4  * Timer code for IOP32x and IOP33x based systems
   5  *
   6  * Author: Deepak Saxena <dsaxena@mvista.com>
   7  *
   8  * Copyright 2002-2003 MontaVista Software Inc.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License as published by the
  12  * Free Software Foundation; either version 2 of the License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/time.h>
  19 #include <linux/init.h>
  20 #include <linux/timex.h>
  21 #include <linux/sched.h>
  22 #include <linux/io.h>
  23 #include <linux/clocksource.h>
  24 #include <linux/clockchips.h>
  25 #include <mach/hardware.h>
  26 #include <asm/irq.h>
  27 #include <asm/uaccess.h>
  28 #include <asm/mach/irq.h>
  29 #include <asm/mach/time.h>
  30 #include <mach/time.h>
  31
  32 /*
  33  * Minimum clocksource/clockevent timer range in seconds
  34  */
  35 #define IOP_MIN_RANGE 4
  36
  37 /*
  38  * IOP clocksource (free-running timer 1).
  39  */
  40 static cycle_t notrace iop_clocksource_read(struct clocksource *unused)
  41 {
  42         return 0xffffffffu - read_tcr1();
  43 }
  44
  45 static struct clocksource iop_clocksource = {
  46         .name           = "iop_timer1",
  47         .rating         = 300,
  48         .read           = iop_clocksource_read,
  49         .mask           = CLOCKSOURCE_MASK(32),
  50         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  51 };
  52
  53 /*
  54  * IOP sched_clock() implementation via its clocksource.
  55  */
  56 unsigned long long sched_clock(void)
  57 {
  58         cycle_t cyc = iop_clocksource_read(NULL);
  59         struct clocksource *cs = &iop_clocksource;
  60
  61         return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
  62 }
  63
  64 /*
  65  * IOP clockevents (interrupting timer 0).
  66  */
  67 static int iop_set_next_event(unsigned long delta,
  68                               struct clock_event_device *unused)
  69 {
  70         u32 tmr = IOP_TMR_PRIVILEGED | IOP_TMR_RATIO_1_1;
  71
  72         BUG_ON(delta == 0);
  73         write_tmr0(tmr & ~(IOP_TMR_EN | IOP_TMR_RELOAD));
  74         write_tcr0(delta);
  75         write_tmr0((tmr & ~IOP_TMR_RELOAD) | IOP_TMR_EN);
  76
  77         return 0;
  78 }
  79
  80 static unsigned long ticks_per_jiffy;
  81
  82 static void iop_set_mode(enum clock_event_mode mode,
  83                          struct clock_event_device *unused)
  84 {
  85         u32 tmr = read_tmr0();
  86
  87         switch (mode) {
  88         case CLOCK_EVT_MODE_PERIODIC:
  89                 write_tmr0(tmr & ~IOP_TMR_EN);
  90                 write_tcr0(ticks_per_jiffy - 1);
  91                 tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN);
  92                 break;
  93         case CLOCK_EVT_MODE_ONESHOT:
  94                 /* ->set_next_event sets period and enables timer */
  95                 tmr &= ~(IOP_TMR_RELOAD | IOP_TMR_EN);
  96                 break;
  97         case CLOCK_EVT_MODE_RESUME:
  98                 tmr |= IOP_TMR_EN;
  99                 break;
 100         case CLOCK_EVT_MODE_SHUTDOWN:
 101         case CLOCK_EVT_MODE_UNUSED:
 102         default:
 103                 tmr &= ~IOP_TMR_EN;
 104                 break;
 105         }
 106
 107         write_tmr0(tmr);
 108 }
 109
 110 static struct clock_event_device iop_clockevent = {
 111         .name           = "iop_timer0",
 112         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 113         .rating         = 300,
 114         .set_next_event = iop_set_next_event,
 115         .set_mode       = iop_set_mode,
 116 };
 117
 118 static irqreturn_t
 119 iop_timer_interrupt(int irq, void *dev_id)
 120 {
 121         struct clock_event_device *evt = dev_id;
 122
 123         write_tisr(1);
 124         evt->event_handler(evt);
 125         return IRQ_HANDLED;
 126 }
 127
 128 static struct irqaction iop_timer_irq = {
 129         .name           = "IOP Timer Tick",
 130         .handler        = iop_timer_interrupt,
 131         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 132         .dev_id         = &iop_clockevent,
 133 };
 134
 135 static unsigned long iop_tick_rate;
 136 unsigned long get_iop_tick_rate(void)
 137 {
 138         return iop_tick_rate;
 139 }
 140 EXPORT_SYMBOL(get_iop_tick_rate);
 141
 142 void __init iop_init_time(unsigned long tick_rate)
 143 {
 144         u32 timer_ctl;
 145
 146         ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ);
 147         iop_tick_rate = tick_rate;
 148
 149         timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED |
 150                         IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1;
 151
 152         /*
 153          * Set up interrupting clockevent timer 0.
 154          */
 155         write_tmr0(timer_ctl & ~IOP_TMR_EN);
 156         setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
 157         clockevents_calc_mult_shift(&iop_clockevent,
 158                                     tick_rate, IOP_MIN_RANGE);
 159         iop_clockevent.max_delta_ns =
 160                 clockevent_delta2ns(0xfffffffe, &iop_clockevent);
 161         iop_clockevent.min_delta_ns =
 162                 clockevent_delta2ns(0xf, &iop_clockevent);
 163         iop_clockevent.cpumask = cpumask_of(0);
 164         clockevents_register_device(&iop_clockevent);
 165         write_trr0(ticks_per_jiffy - 1);
 166         write_tcr0(ticks_per_jiffy - 1);
 167         write_tmr0(timer_ctl);
 168
 169         /*
 170          * Set up free-running clocksource timer 1.
 171          */
 172         write_trr1(0xffffffff);
 173         write_tcr1(0xffffffff);
 174         write_tmr1(timer_ctl);
 175         clocksource_calc_mult_shift(&iop_clocksource, tick_rate,
 176                                     IOP_MIN_RANGE);
 177         clocksource_register(&iop_clocksource);
 178 }