arm/imx/irq: order definitions of MXC_GPIO_IRQS numerically
[deliverable/linux.git] / arch / arm / plat-mxc / include / mach / irqs.h
1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5 /*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #ifndef __ASM_ARCH_MXC_IRQS_H__
12 #define __ASM_ARCH_MXC_IRQS_H__
13
14 /*
15 * So far all i.MX SoCs have 64 internal interrupts
16 */
17 #define MXC_INTERNAL_IRQS 64
18
19 #define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
20
21 /* these are ordered by size to support multi-SoC kernels */
22 #if defined CONFIG_ARCH_MX2
23 #define MXC_GPIO_IRQS (32 * 6)
24 #elif defined CONFIG_ARCH_MX1
25 #define MXC_GPIO_IRQS (32 * 4)
26 #elif defined CONFIG_ARCH_MX25
27 #define MXC_GPIO_IRQS (32 * 4)
28 #elif defined CONFIG_ARCH_MXC91231
29 #define MXC_GPIO_IRQS (32 * 4)
30 #elif defined CONFIG_ARCH_MX3
31 #define MXC_GPIO_IRQS (32 * 3)
32 #endif
33
34 /*
35 * The next 16 interrupts are for board specific purposes. Since
36 * the kernel can only run on one machine at a time, we can re-use
37 * these. If you need more, increase MXC_BOARD_IRQS, but keep it
38 * within sensible limits.
39 */
40 #define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS)
41
42 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
43 #define MXC_BOARD_IRQS 80
44 #else
45 #define MXC_BOARD_IRQS 16
46 #endif
47
48 #define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
49
50 #ifdef CONFIG_MX3_IPU_IRQS
51 #define MX3_IPU_IRQS CONFIG_MX3_IPU_IRQS
52 #else
53 #define MX3_IPU_IRQS 0
54 #endif
55
56 #define NR_IRQS (MXC_IPU_IRQ_START + MX3_IPU_IRQS)
57
58 extern int imx_irq_set_priority(unsigned char irq, unsigned char prio);
59
60 /* all normal IRQs can be FIQs */
61 #define FIQ_START 0
62 /* switch betwean IRQ and FIQ */
63 extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type);
64
65 #endif /* __ASM_ARCH_MXC_IRQS_H__ */
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